S. Reda EN1600 SP’08

Design and Implementation of VLSI Systems(EN1600S08)

Lecture12: Logical Effort (1/2)

Prof. Sherief RedaDivision of Engineering, Brown University

Spring 2008

[sources: Weste/Addison Wesley – Rabaey/Pearson]

S. Reda EN1600 SP’08

Impact of transistor sizing

What happens to the delay if we increase the transistor sizes by K?

Is it the case that increasing the size of the transistor always reduces delay?

S. Reda EN1600 SP’08

Impact of sizing in a path

Cout×K

Less output resistance; increase output capacitance→ delay reduces (parasitic delay stays the same)

Larger input capacitance → increases delay of previous stage!

What is the final outcome? Should we size? By how much?

S. Reda EN1600 SP’08

Impact of gate sizing

3

3

222

3

9C

3C

3C3

3

3

222

5C5C

5C

If you decide to increase everything by a factor of k

How about an inverter? 12 ps in 180 nm process

40 ps in 0.6 m process

Unloaded delay =3RC

S. Reda EN1600 SP’08

Expressing delay as a linear model

C is the capacitance of unit width transistord = R/k(4h’C+ 6kC)d = RC(4h’/k + 6)

parasiticdelay

effortdelay

Normalize with respect to 3RC (delay of unloaded inverter)d = 4/3 * h’/k + 2

logical effort(affected by gate type or geometry)

electric effort

S. Reda EN1600 SP’08

Summary of linear delay model

• g: logical effort = ratio between input capacitance of the gate to the input capacitance of the inverter that would deliver the same current• h: electric effort = ratio between load capacitance and the gate input capacitance (sometimes called fanout)• p: parasitic delay

• represents delay of gate driving no load• set by internal parasitic capacitance

S. Reda EN1600 SP’08

Computing logical effort

S. Reda EN1600 SP’08

Computing parasitic delay

S. Reda EN1600 SP’08

Example: Ring oscillator

• Estimate the frequency of an N-stage ring oscillator

Logical Effort: g = Electrical Effort: h =Parasitic Delay: p =Stage Delay: d =Frequency: fosc =

S. Reda EN1600 SP’08

Example: Ring oscillator

• Estimate the frequency of an N-stage ring oscillator

Logical Effort: g = 1Electrical Effort: h = 1Parasitic Delay: p = 1Stage Delay: d = 2Frequency: fosc = 1/(2*N*d) = 1/4N

31 stage ring oscillator in 0.6 m process has frequency of ~ 200 MHz

S. Reda EN1600 SP’08

Example: FO4 Inverter

• Estimate the delay of a fanout-of-4 (FO4) inverter

Logical Effort: g = Electrical Effort: h =Parasitic Delay: p =Stage Delay: d =

d

S. Reda EN1600 SP’08

Example: FO4 Inverter

• Estimate the delay of a fanout-of-4 (FO4) inverter

Logical Effort: g = 1Electrical Effort: h = 4Parasitic Delay: p = 1Stage Delay: d = 5

d

The FO4 delay is about

200 ps in 0.6 m process

60 ps in a 180 nm process

f/3 ns in an f m process