Setting up your working Environment (Only for first time users)• Login to your Linux machine with User ID and Password• Open your “Home” folder on the desktop• Click on “View” and check “Show Hidden Files”

• Find the “.cshrc” file from the list◦ Right click on the file and choose “Properties”◦ Go to “Permissions” tab and select “Read and write” from Owner Access◦ Click “Close”

• Right click on “.cshrc” file and choose open with Text Editor• Find the code “source/usr/local/etc/ALLSET” and “Delete” this line.• Add two lines to the file

◦ source /opt/cds/class/cds_setup

◦ source /opt/cds/class/setup_files/vhdl/.vhdl_setup• Save and close the editor

• Open new terminal by right clicking on desktop and choosing “Open in Terminal”

• Type the following commands◦ cd $home

• Create a new directory named “Cadence”, under home directory◦ mkdir cadence◦ cd cadence

• Create a “vhdl” directory under cadence directory.◦ mkdir vhdl◦ cd vhdl

Writing the Verilog Code• Make a directory inside “vhdl” folder with some name.

◦ mkdir Grad• Copy and paste the “.v” verilog code of program and test bench written in test editor that you

want to execute to the Grad folder (Ex: “smpl_circuit.v” and “smpl_circuit_tb.v”)

smpl_circuit.v

module smpl_circuit(A,B,C,x,y);

input A,B,C;

output x,y;

wire e;

and g1(e,A,B);

not g2(y,C);

or g3(x,e,y);

endmodule

smpl_circuit_tb.v

module smpl_circuit_tb;

reg A,B,C;

wire x,y;

smpl_circuit sc(A,B,C,x,y);

initial

begin

#25 A=0; B=0; C=0;

#25 A=0; B=0; C=1;

#25 A=0; B=1; C=0;

#25 A=0; B=1; C=1;

#25 A=1; B=0; C=0;

#25 A=1; B=0; C=1;

#25 A=1; B=1; C=0;

#25 A=1; B=1; C=1;

end

initial

#200 $finish;

endmodule

NCLaunch• Once the initial settings are over, further processing can be started from here.• Open the terminal and type the following commands

◦ cd $home/cadence/vhdl◦ cp $NCVHDL/cds.lib $CDSVHDL◦ cp $NCVHDL/hdl.var $CDSVHDL◦ nclaunch &

• Select your verilog source file from the file browser area

• Compile the selected file either by double clicking the file or choosing Tools -> Verilog Compiler and press OK in the Compile Verilog window without changing anything.

• After compilation the file will appear on the right hand side of the window in the folder name either worklib or vhdl. You can see the file by clicking the plus sign of the corresponding folder.

• Repeat the same for test bench (Ex: smpl_circuit_tb.v) file also.

• Select the compiled test bench file (Ex: smpl_circuit_tb.v) from the worklib or vhdl folder.• Either right click the file and select NCElab... or select Tools -> Elaborator

• Press OK in the Elaborator menu without changing anything.

• Once Elaboration is over the :module (Ex: vhdl.smpl_circuit_tb:module) file will be available in Snapshots folder

• Select the test bench:module (Ex: vhdl.smpl_circuit_tb:module) file from the Snapshots andeither right click on the file and select NCSim... or select Tools -> Simulator to run the simulation

• Press OK without changing anything in the Simulate window

• Two new windows (Design Browser 1 -SimVision, Console - SimVision) will appear on clicking OK in the simulate window

• From the Design browser Select your program• On the right side of the Design Browser the variables and their values are displayed.• Click on the Waveform Sign in the upper right corner and the Waveform window will open.

• Click on the Run button to see the waveform

ENCOUNTER1. Setting up the Encounter

• Open cadence/vhdl/cds.lib file and add the following line DEFINE NCSU_TechLib_ami06 /opt/cds/class/local/lib/oa/NCSU_TechLib_ami06

The cadence/VHDL/cds.lib file will look like include $CDS_INST_DIR/tools/inca/files/cds.lib #DEFINE ieee /opt/cds/ldv/tools/inca/files/IEEE #DEFINE std /opt/cds/ldv/tools/inca/files/STD DEFINE vhdl ~/cadence/vhdl DEFINE NCSU_TechLib_ami06 /opt/cds/class/local/lib/oa/NCSU_TechLib_ami06

2. Type these commands in you terminal cd $CDSVHDL mkdir fe cd fe cp $DSMSE/ece753.conf ece753.conf

Go the folder in which you have the verilog file.3. Open terminal and type “encounter”4. Type bgx_shell inside the encounter terminal and create a netlist using the following commands

read_tlf ami06.tlfset_global hdl_vhdl_environment synopsysread_verilog smpl_circuit.vdo_build_genericdo_optimizewrite_verilog -hier smpl_circuit_net.vexit

(After entering all these commands a netlist is created with name smpl_circuit_net.v in the folder)5. Now go to the GUI of encounter6. Select File -> Import Design

Encounter window

7. In Import Design window click on load and select ece753.conf which is located in the folder fe inside vhdl

7. Click OK8. Click on Files under verilog in the design import window (By clicking ... on the right side of the screen)

Importing Configuration

Design Import Screen

8. Click on the designated netlist verilog file (In this example smpl_circuit.v)9. Click close10. Check the top cell to Auto Assign in the Netlist verilog box.

11. Click OK

Selecting Netlist File

Design Import Window Top Cell selection

12. After clicking the OK button the Encounter window will look like this

13. Select Floorplan -> Specify Floorplan

14. Click OK without changing anything in the window.15. Select Power -> Power Planning -> Add Rings16. Change Top and Bottom to metal3H17. Change all Width to 418. Click OK

Encounter window after Design Import

Setting Floorplan

Add Rings Window with changes

Encounter window after adding rings

19. Click Route -> Special Route

20. Click OK without changing anything in the window, The Blue line should appear in the encounter window.

21. Perform the following operations without changing anythingPlace -> Place Jtag -> OKPlace -> Place Standard Cells -> OKRoute -> Nanoroute -> Route -> OK

Special Route window

Encounter window after special route operation

22. After these operations the Encounter window will look like this:

23. Select Place -> Physical Cell -> Add Filler

24. Click on Select and Select Fill from Select Filler Cells Window and click close

Encounter window after place and route operations

Selecting Cell Name

Selecting Filler Cells

25. In Add Filler Window check the Mark Fixed

26. Click OK, the encounter window will appear as filled and shaded inside

27. Click Verify -> Verify Connectivity -> OK, without changing anything.28. Click File -> Save -> GDS/OASIS

Making Changes in the Add Filler Window

Encounter Window after step 26

29. Enter desired verilog name and give extension .gds2 (In this example smpl_circuit_enc.gds2) and check Structure Name and then press OK

Saving as GDS/OASIS

Saving as .gds2 file

30. Click File -> Save -> DEF31. Check all the save options except Save Scan as shown in figure, and click OK

32. Now close the Encounter window

Save DEF window

VIRTUOSO1. Go to terminal and type virtuoso and press enter2. Often during the process, a license upgrade screen may pop up. Simply press Yes3. Close all the screens except Library Manager and Log Window

Library Manager and Log window

4. Library window select: File -> New -> Library to create a new library.5. Give a name to the library and click OK (In this example we are giving a name CadenceLibrary)

Note: After creating the library once, you can use the same library again. Hence this step is required only in the first time use. If you want to create a library at any time you can follow the above procedure.

6. Now go to the Log window and click: File -> Import -> Stream and click on options

• Select Geometry and check Snap To Grid

XStream In Window

Creating a new library

• Select Layers ->Load File

Snap To Grid Selection

Load File from StreamIn