cadence icfb design tutorial

DIMES03 Design Tutorial - Introduction

This tutorial describes how a integrated circuit in the DIMES03 technology can be designed,

from schematic to GDS file, using the Cadence design system. As an example a simple

differential amplifier is created that consists of 4 bipolar transistors and 5 resistors. All important

aspects of integrated circuit design are discussed, such as schematic entry, simulation, layout

synthesis, DRC, extraction, LVS, re-simulation and GDS file generation.

This tutorial was created using Cadence version 4.4.3. Note that at Delft University, currently,

only Cadence version 4.4.5 and version 4.4.6 are supported. These versions can also be used for

this tutorial, but you will find out that some window appearances and command names may be

slightly different from what is shown in this tutorial.

The tutorial uses the Cadence DIMES03 design kit installed under

/opt/cad/cadence/DesignKits/dimes03 on TU-Delft Micro-Electronics machines, or available for

ftp as dimes03Lib.tar.gz. The design kit contains a cell library that is described in the DIMES03

library.

An example of the design data that is created during the tutorial can be found in the directory

tutorial/cad/dimes03 of the tutorial tree (installed under /opt/cad/cadence/DesignKits/dimes03 on

TU-Delft Micro-Electronics machines or available for ftp as dimes03Tutorial.tar.gz).

For more information about the DIMES03 technology, see the DIMES03 Design Manual,

version 1.0, nov. 2002, Editor: Tjander Nathoeni, DIMES IC Processing.

http://icdfs0.et.tudelft.nl/cadmgr/dimes03Lib.tar.gz

http://warga.et.tudelft.nl/cadmgr/dimes03CellLib/cells.html


http://icdfs0.et.tudelft.nl/cadmgr/dimes03Tutorial.tar.gz

http://paramex.dimes.tudelft.nl/design/DIMES03manual.pdf


DIMES03 Design Tutorial - Basics

Setting search paths and environment variables

Search paths and environment variables that are necessary to run Cadence can be set as follows:

$ source /opt/cad/cadence/4.4.6/sourceme

$ setenv CDS_Netlisting_Mode Analog

Note that it is best to include these lines in your .cshrc file (or similar file that you use to set paths during

login).

Creating a DIMES03 working directory

You can create an appropriate working directory ~/cad/dimes03 that contains the required initialization

files for Cadence (.cdsinit and cds.lib), as follows:

$ source /opt/cad/cadence/DesignKits/dimes03/sourceme

Starting Cadence

Start Cadence in the DIMES03 working directory as follows:

$ cd ~/cad/dimes03

$ icfb &

The Command Interpreter Window (CIW) will appear, which is the central window to start Cadence tools

etc.. Note that by Clicking on "Help" in the upper right corner of most of the Cadence windows, the

Cadence OpenBook documentation will show up.

The library manager

To bring up the library manager, click on Tools -> Library Manager in the CIW window.

The library manger window shows the libraries that are known during this Cadence session and

initially shows the libraries analogLib, basic, cdsDefTechLib and dimes03Lib. (The library

manager reads its information from the file cds.lib in your working directory.) The library

analogLib, basic and cdsDefTechLib are delivered with the Cadence software and contain

general cells like input sources, supply and ground connections etc. The library dimes03Lib

contains a cell library, including layouts, especially for components (transistors, resistors etc.) in

the DIMES 03 process (see http://warga.et.tudelft.nl/cadmgr/dimes03CellLib/cells.html).

Note that all of the above library names are in fact links to libraries that are physically stored at

other places, and that they are read-only for the user. The libraries can not be used to create your

own design data in. Therefore, you should create your own, local, library, which is explained in

the following.

Creating a new library

To create a new library in which you will create your design, click on File -> New -> Library in the

Library Manager window. Next, type the name of the new library that you will create after the field

Name: dimes03Tutorial, and click on OK. After that, select Attach to an existing techfile and click on


OK. Set Technology Library to dimes03Lib and again click on OK. The name of the new library will

now be present in the Library Manager window.

DIMES03 Design Tutorial - Schematic Entry

Starting the schematic entry tool

To create a new schematic cell view and start the schematic entry tool Composer, first select the library

dimes03Tutorial in the Library Manager window by clicking on it with the left mouse button. Next click

on File -> New -> Cell View in the Library Manager window. The following window will appear:

Type after Cell Name the name of the cell that you will create: diffamp, select for Tool

Composer-Schematic (for View Name automatically schematic will be filled in) and next click on

OK. The schematic cell view will be created and the Composer window will appear:

To start the schematic entry tool on an existing cell view, select from the Library Manager the

appropriate library, cell and view. Next click on File -> Open, or position the cursor on

schematic, click the right mouse button and select Open

Editing your schematic

Create your schematic with Composer using the commands from the menus Add and Edit, or using the

command buttons at the left side of the window. E.g. to add an instance of a component click on Add ->

Instance or on the 10th. button at the left side of the window. The Add Instance window will appear. To

select the name of the component click on Browse and select the library, cell and view for the component.

For the latter, use symbol. As an example, the following will add an instance of a npn2x1 transistor from

the dimes03Lib library.

Move the component to the appropriate position with the cursor and place it by clicking on the

left mouse button. For our example, place the following components from the dimes03Lib

library, similar to the schematic as shown in the picture below.

component number

npn2x1 2

npn4x1 2

res500lp 2

res10klb 3

To close the Library Browser and Add Instance window, click on respectively Close and Cancel, or press

the Escape key.

You can move a component that has already been placed by first clicking on Edit -> Move, next

clicking on the component with the left mouse button to select it, moving the component to its

new position, and next clicking on the left mouse button again. You can rotate a component by

first clicking on Edit -> Rotate and next clicking on the component with left mouse button. You

can mirror a component by first clicking on Edit -> Rotate, next pressing on F3, selecting

Sideways in the Rotate window that pops up, and next clicking on the component with left

mouse button. Finally, a component can be deleted using Edit -> Delete and selecting it with the

left mouse button. All of the above commands are finished by pressing the Escape key or, if

appropriate, by clicking Cancel in the corresponding window.

To add pins/ports for the cell, click on Add -> Pin or on the 14th. button at the left side of the

window. The Add Pin form appears. Type the name of the pin after Pin Names, choose the

Direction of the pin (input, output or inpoutOutput), possibly change the Orientation of the pin,

and place the pin with the cursor by clicking on the left mouse button. Add the following pins:

pin name direction

vcc input

vee input

in input

gnd input

out output

Click on Cancel or press Escape to finish the Add Pin form. You can move, rotate and mirror pins in a

similar way as components.

To add a wire, click on Add -> Wire (narrow) or on the 11th. button from above at the left side

of the window. Create the wire by moving with the cursor to the required positions and clicking

the left mouse button to start and finish wires or to create corners. To finish the add wire

command, press the Escape key. Complete the circuit as follows:

Save the schematic by clicking on Design -> Save. Exit the program by clicking on Window ->

Close.

Creating a symbol view for your schematic

The inclusion of a schematic view of a cell as an instance in the schematic view of another cell (as is done

for simulation in the next section) requires the existence of a symbol view for that cell. A symbol view

can be created fully by hand, using Composer-Symbol, but it is easier to automatically generate it from its

corresponding schematic view. To create a symbol view for cell diffamp from its schematic view, open

the schematic view for cell diffamp, e.g. by selecting it in the library manager and clicking on File ->

Open. From the the Composer window click on Design -> Create Cellview -> From Cellview. The

Cellview From Cellview form appears. Make sure that the contents of the form is as follows, and next

click on OK:

In the Symbol Generation Options form that appears, use after Left Pins: in gnd, after Right Pins:

out, after Top Pins: vcc, and after Bottom Pins: vee. Next, click on OK.

The symbol view will be generated and shown by Composer-Symbol as follows:

Exit Composer-Schematic and Composer-Symbol by clicking Window -> Close.

DIMES03 Design Tutorial – Simulation

Creating a schematic view for simulation

To simulate the diffamp circuit we will create a new cell called diffampConfig. This cell will call an

instance of cell diffamp and it will additionally define the simulation environment (simulation input

sources and load capacitance) for the diffamp cell.

Create a schematic cell diffampConfig in library dimes03Tutorial, using File -> New -> Cell

View in the library manager, similar as described in the previous section. Add an instance of the

cell diffamp and complete the circuit as shown below. Use the following components with the

following parameters. The value of a parameter is specified in the corresponding field of the Add

Instance form before the component is placed

component library parameters

diffamp dimes03Tutorial -

vdc analogLib DC voltage: 15

vdc analogLib DC voltage: -15

vsin analogLib AC magnitude: 0.1

cap analogLib Capacitance: 1p

gnd analogLib -

Use Add -> Wire Name, or the 13th button from above at the left side of the window, to add the

names "in" and "out" to the wires connected to respectively the input and output of the diffamp

circuit.

Save the design using Design -> Check and Save.

Starting the simulation interface

The simulation interface is started from the diffampConfig schematic window using Tools -> Analog

Artist. The following window will then appear:

Defining simulation control data

Important: when running Cadence version 4.4.3 on an HP computer, please first read the note at the end

of this section.

To specify simulation analyses, click on Analyses -> Choose in the Analog Artist Simulation

window. To specify an ac analysis select the ac button. Complete the form as follows and click

on OK.

To specify the outputs during simulation click on Outputs -> To Be Saved -> Select On

Schematic. Click on respectively the wire named "in" and the wire named "out" in the

Composer-Schematic window and finish the selection by clicking on the Escape key. Select the

two lines that have now appeared in the Outputs field by clicking on them with the left mouse

button while pressing the Shift key. Click on Outputs -> To Be Plotted -> Add To to select

plotting of the outputs. The Analog Artist window will then have the following contents:

Note: When running Cadence version 4.4.3 on an HP computer, Cadence will fail when

Analyses -> Choose has been clicked and the ac button is selected. To enter an ac analysis

without using the Choosing Analysis window, quit from Analog Artists, create the following file,

e.g. called artistenv:

cdsSpice.ac from string "100"

cdsSpice.ac lin string ""

cdsSpice.ac incrType string "Logarithmic"

cdsSpice.ac to string "1e9"

cdsSpice.ac enable toggle (t)

cdsSpice.ac log string "5"

and read it by entering the following line in the CIW window.

envLoadFile("artistenv")

Next, when Analog Artist is started again, an ac analysis will be specified. After this, continue with the

specification of the outputs as described above.

Running the simulator

In the Analog Artist Simulation Window click on Simulation -> Run or on the button with the green

traffic light. In the CIW window messages about the netlisting and the simulation will be printed. When

the simulation has finished, the waveforms will automatically be plotted in a Waveform Window:

Saving the simulation state

The simulation interface state can be saved for later simulations (after you quit Analog Artist). To do this

click on Session -> Save State .... The Saving State window will appear as shown below.

After the Save As field, a name for the state can be specified (default is state1). Next click on

OK.

Displaying phase waveforms

To watch the phase of the signals (without running on a new simulation) click on Results -> Direct Plot -

> AC Phase. The user is asked to select the nets from the Composer-Schematic window. Now, only nets

can be selected for which outputs have been saved during the last simulation run, which are in our case

net "in" and net "out". After clicking on the wire connected to "out" and finishing the selection by

pressing the Escape key, the following window will appear:

Displaying current waveforms

The following demonstrates the plotting of a current through a pin of a component (transistor) inside the

diffamp circuit. In this case we have to run a new simulation since no simulation results were saved for

this pin during the last simulation.

In the Analog Artist window, click on Outputs -> To Be Saved -> Select On Schematic. In the

Composer window, click on Design -> Hierarchy -> Descend Read and next click on the

diffamp block. In the Descend window that will appear then, check that for View Name

schematic is selected, and click on OK. The Composer window will now show the schematic

view of the diffamp cell. Click on the collector pin of the transistor that is connected to the

emitters of the two input transistors. In the Analog Artist window, in the Outputs field, a line will

then appear with a name similar to I0/Q2/C. Finish the selection by clicking on the Escape key.

In the Composer window, return to cell diffampConfig by clicking on Design -> Hierarchy ->

Return.

In the Analog Artist window, select the new line in the Outputs field with the cursor and the left

mouse button and click on Outputs -> To Be Plotted -> Add To. Select the two other lines in

the Outputs field with the cursor and the left mouse button, while pressing the Shift key for the

second line. Click on Outputs -> To Be Plotted -> Remove From. Run a new simulation by

clicking on the button with the green traffic light. The following window will then appear:

DIMES03 Design Tutorial - Layout Synthesis

Starting the layout synthesis environment

In this section we will generate a layout for the diffamp circuit using the placement and routing tools that

are available in Virtuoso XL.

To start the Virtuoso XL environment, open the schematic view of cell diffamp. Next, in the

Composer window, click on Tools -> Design Synthesis -> Layout XL. The Virtuoso XL

Startup Option window will appear, asking whether a new layout cell view should be created or

an existing layout cell should be used. Enable Create New and click on OK. A Create New File

window will then appear. Use for Library Name dimes03Tutorial, for Cell Name diffamp, for

View Name layout, and for Tool Virtuoso, and click on OK. The following layout of windows

will be shown:

The upper middle window is the Composer window that shows the schematic view of the

diffamp cell. The right window is the Virtuoso XL window that will later show the layout view

of the diffamp cell. The upper left window is the LSW window (see also below) that shows the

layers that are available in the layout view and that can be selected for editing. Finally, the lower

left window is the CIW window.

Generating layout from schematic

To start the generation of the layout from the schematic, click on Design -> Gen from Source ... in the

Virtuoso XL window. The Layout Generation Options window, as shown below, will appear. Under I/O

Pins, switch off the Create button for Defaults to prevent the creation of a pin "BULK!" for the epi

connections of the layout instance cells.

Next, click on OK. The Virtuoso XL window will show a large purple rectangle, which

describes the boundary for placement and routing, and several small red rectangles describing the

bounding boxes of the layout of the instance cells. Also the pins of the layout will be present in

the layout shown by the Virtuoso XL window. To obtain an initial placement with the instances

and pins inside the place and route boundary, click on Edit -> Place from Schematic in the

Virtuoso XL window. Press the f key or click Window -> Fit All to fit the total design in the

Virtuoso window. A picture similar as below will be obtained.

To see which layout instance corresponds to which schematic instance, click on an instance in

one of the views and the corresponding instance in the other view will be highlighted.

Viewing the contents of the instances

To view the contents of the instances, press Shift-f:

To view only the bounding boxes again, press Ctrl-f.

Viewing the unconnected nets

Virtuoso XL can show so called flight lines for the nets in the layout that are not yet connected. The flight

lines connect the pins that belong to the same net, and flight lines that belong to the same net have the

same color. To show the flight lines for the unconnected nets, click on Connectivity -> Show

Incomplete Nets. The Show Incomplete Nets form will appear from which the nets that are shown are

selected. Click on OK and a picture similar to below will be obtained:

To hide the flight lines again, click on Connectivity -> Hide Incomplete Nets.

Placement

An initial placement was obtained using Edit -> Place from Schematic. Often, the placement can or

must be improved by moving the instances and/or pins. The instance and pins should be close enough to

minimize the total chip area and wire length, while they should be far enough from each other to have

enough space between them to connect all wires. Also, note that instances should not be closer than 4

micron to prevent that the dp regions of the instances are to close to each other (design rule DP.2.1). The

latter can e.g. be checked by runing a DRC on the layout of the placement, as described in Section

"Design-Rule Checking".

To move an instance or pin, select the instance or pin by clicking on it with the left mouse button

or by drawing a selection rectangle around it. Next, click on Edit -> Move or press the m key.

Move the object by first clicking a reference point with the left mouse button and next clicking

the new position for the reference point.

Also the bounding box for placement and routing can be adjusted to better fit the placement area,

and the area that will be needed for routing. The bounding box for placement and routing is

http://icdfs0.et.tudelft.nl/cadmgr/dimes03Tutorial/drc.html

defined by a prBndry layer rectangle and this rectangle is edited similar to the way how other

layout polygons are edited. The prBndry rectangle can e.g. be changed by first deleting the

existing one and next adding a new one.

To delete the prBndry layer rectangle, first select it by clicking on it with the left mouse button

and next click on Edit -> Delete. To add a prBndry layer rectangle, first click with the left

mouse button in the prBndry rectangle in the LSW window to select this layer as edit layer.

Next, create the rectangle by first clicking Create -> Rectangle and next click on the position

for the first corner and the position for the opposite corner respectively

The final result of the placement may be something like as shown below.

Routing

Routing is done in Virtuoso XL by using IC Craftsman. Before starting IC Craftsman, a directory

cellImages, where cell is the name of the cell that we are are going to route, has to be created in you

directory ~/cad/dimes03. This directory should contain links to the image files for the library cells that we

are going to use. These image files are present in the directory

/opt/cad/cadence/DesignKits/dimes03/iccImages. In our case, for cell diffamp, this directory can then be

created as follows:

$ cd ~/cad/dimes03

$ mkdir diffampImages

$ ln -s /opt/cad/cadence/DesignKits/dimes03/iccImages/* diffampImages

To export the layout and connectivity data from Virtuoso XL to IC Craftsman, click on Route -> Export

to ICC... in the Virtuoso XL window. The Export to IC Craftsman window as shown below will appear.

Enable the option Use Rules File and specify in the field below it the file name

/opt/cad/cadence/DesignKits/dimes03/icc.rules. Check that the options Full Connectivity and Incremental

Update are enabled and click on OK.

After some time, the IC Craftsman window will appear showing the placement for cell diffamp

and flight lines for the unconnected nets:

To start the routing, click on Autoroute -> Route... in the IC Craftsman window. Next, in the

AutoRoute form click OK. After the routing has finished, IC Craftsman will show a picture as

shown below:

To read the routing results into Virtuoso XL the results have first to be written by IC Craftsman.

This is done by clicking on File -> Write -> Session in IC Craftsman. In the Write Session form

that appears it is specified that routing data will be written as diffamp.ses. Click on OK. On a

warning about same net checking, click Yes.

To read the results of IC Craftsman into Virtuoso, click Route -> Import from ICC... in the

Virtuoso window. Check that the form has the following contents and click OK.

Virtuoso XL will then show the routed layout:

To quit IC Craftsman, click on File -> Quit.

Probing: finding pins, nets and devices

With probing it is easy to find information about pins, net and devices in the layout and schematic view,

and to see how an object in one view corresponds to an object in the other view. To enable probing, click

on Connectivity -> XL Probe in the Virtuoso XL window. Next, press key F3 to obtain the Virtuoso XL

Probe Options form.

Click on a pin, net or device in the layout or schematic. The object and the corresponding object

in the other view will be highlighted and the names of the objects will be printed in the Probe

Options form.

To find a particular net in the schematic or layout view, based on its name, click on List Nets...

in the Virtuoso XL Probe Options form. A Probe Net List form will appear from which a net

name can be selected, e.g. net out. After clicking on Apply, this net is then highlighted in the

schematic and the layout view:

To find a particular device in the schematic or layout view, based on its name, click on

Connectivity -> Change Instance View... in the Virtuoso XL window. The Change Instance

View form will appear. Click on List Devices... and next the Change Inst View Device List form

will appear listing the names of all the devices that are present in the layout. When selecting a

device in the list and next clicking on Apply, the corresponding device will be highlighted both

in the layout view and the schematic view.

Epi and substrate connections

In the routed layout, the epi connections of all resistors will be connected to each other via a net called

BULK! However, this net still needs to be connected to a positive supply voltage, i.e. to pin vcc in our

case. Therefore, create a path, using the command Create -> Path, that connects the net BULK! to the

net vcc: After clicking Create -> Path, select layer icm in the LSW window by clicking on it with the left

mouse button, click with the left mouse on the position where the path should start, click once for a bend

in the path, and double click to finish the path. Press Escape to finish the create path command. When the

path has been created, a marker will be flashing to indicate that a short has been created between two nets

that are not connected in the schematic view.

Also, the substrate should be connected to the negative supply voltage, i.e. to pin vee. Therefore,

use the command Create -> Contact to add a substrate contact of type "substr_icm" somewhere

on the net vee.

Click on Design -> Save to save the design.

DIMES03 Design Tutorial - Using

Parameterized Cells

Parameterized cells

In the previous sections we have seen how to use library cells that have fixed parameter values and, as a

consequence, fixed layout dimensions. However, the cell library for the DIMES 03 process also contains

some parameterized cells, or pcells, that allow you to specify e.g. the resistance or the capacitance of a

cell as a parameter. See the DIMES03 library.

As an example we will replace one of the resistors in our schematic design by a parameterized

cell, update the layout instances and perform incremental routing to connect the new instance in

the layout.

Creating parameterized cells in the schematic

In the Composer window use Edit -> Delete to delete the lower-left resistor cell res500lp. Next, use Add

-> Instance to add a symbol instance of cell res100_1klp from the library dimes03Lib. Specify a

resistance value of e.g. 700 Ohms in the Add Instance form and place the instance in the schematic.


Updating the layout instances

Here we assume that you are still running Virtuoso XL, as discussed in the Section "Layout Synthesis". If

not click Tools -> Design Synthesis -> Layout XL in the Composer window and open the existing

layout view for cell diffamp.

First, remove the resistor cell res500lp in the layout that corresponds to the cell res500lp that was

removed from the schematic. Use the command Edit -> Delete. Also delete some wires around

it, such that the following layout is obtained:

Next, click Connectivity -> Update -> Components and Nets. If a window pops up with the

message "Schematic extraction is needed ...", click OK. In the Layout Generation Options form

that appears, in the section I/O Pins, at the end of the line starting with Defaults, disable the

button below "Create" and click on OK.

Now, an instance of the layout view of cell res100_1klb with correct layout dimensions, will

automatically be placed under the prBoundary area. If you do not immediately see the instance,

press key f in the Virtuoso window to fit the total layout onto the Virtuoso window. Use Edit ->

Move to move the new instance to the position where the deleted cell res500lp was. When

enabling Connectivity -> Show Incomplete Nets you will see a picture as shown below:

If you want you can now try to change the value of the resistance for cell res100_1klp in the in

the schematic view and update the layout of the cell accordingly. Therefore, first select the

instance in the schematic view by clicking on it with the left mouse button, press q to bring up

the Edit Object Properties window, change the value for the resistance and click on OK. Then, in

the Virtuoso XL window, click on Connectivity -> Update -> Layout Parameters and watch

how the layout is updated.

Incremental routing

Click on Route -> Export to ICC to bring up the Export to ICC Craftsman window. Next, start the

routing tool. by clicking on OK. The following window will appear, showing the wires that have already

been routed and flight lines for the nets that still need to be routed.

Click on Autoroute -> Route ... to start an incremental routing for the nets that still need to be

routed. A result similar to as shown below will be obtained.

DIMES03 Design Tutorial - Design-Rule

Checking

Running the design-rule checker

The layout can be checked on design-rule errors by clicking Verify -> DRC... in the Virtuoso window.

The DRC window will then appear as shown below. By clicking on OK the design-rule checker will be

started. The layout design rules as described in the DIMES03 Design Manual, version 1.0, nov. 2002,

Editor: Tjander Nathoeni, DIMES IC Processing will be checked.

Error messages and markers

The rule violations that occur are presented in two ways. First, a list of rule violations is printed in the

CIW window as shown below:

********* Summary of rule violation for cell "diffamp layout" *********

# errors Violated Rules

18 WN.0.3 co to epi without wn

48 IC.3.1 icm on co enclosure < 1.0

8 LB.4.2 lb dn sep < 3.0

8 CO.6.3 min extension of lb inside co < 0.5

4 CO.1.2 co dimen > 10.0

19 IC.2.1 icm sep < 2.0



8 LB.6.1 min lp extension inside lb < 1.0

113 Total errors found

Second, the location of the errors is shown in the layout by means of flashing areas.

In our example we notice that are a lot of design-rule errors. This is because the cells in the

dimes03Lib library are designed with some optimizations that do not obey the general design-

rules. In the next section it will be shown how to skip these error messages, but here we use them

to see how DRC errors are presented.

To see which errors occur for areas that are flashing, click on Verify -> Markers -> Explain in

the Virtuoso window. Next click on an area with the left mouse button. In a new window the

corresponding error(s) will be listed, as for example shown below. The marker explain command

can be finished by pressing the Escape key.

DRC and DIMES03 library cells

As we saw above, the cells in the dimes03Lib library contain some violations against the general DIMES

03 design-rules as default checked by the design-rule checker. It is possible to let the design-rule checker

suppress the messages that correspond to these errors by setting the switch noLibDRC in the DRC

window. This is done by clicking Set Switches in the DRC window, next selecting the switch noLibDRC

and finally clicking on OK in the Set Switches window. The DRC window will then look as follows.

Now, when OK is clicked in the DRC window, no errors will be found.

DRC switches

The switch noLibDRC is only one of the switches that can be used during design-rule checking. The

following gives an overview of the switches that can be used with design-rule checking.

emergencyICrules

Use the (less strict) emergency rules for layer icm, as described in the DIMES03 Design Manual,

Section 3.1.

noLibDRC

Suppress design-rule error messages for the DIMES03 library cells.

singleMetalSCPrules

Use the single metal rules for mask scp instead of the double metal rules. With the single metal

rules, layer icm is used in combination with scp for boundaing pads, and with double metal rules,

layer in is used in combination with scp.


DIMES03 Design Tutorial - Extraction

Running the extractor

A netlist can be extracted from the layout view of cell diffamp by clicking on Verify -> Extract... in the

Virtuoso window. The following form will appear then:

Default the extractor will extract all transistors, lp and lb resistors, and junction and interconnect

capacitances. By setting one or more switches, using the Set Switches command in the Extractor

form, the elements that are extracted can be controlled:

no_resistance: No lp and lb resistors are extracted.

epi_resistance: Epi resistors are also extracted.

no_capcitance: No junction and interconnect capacitances are extracted.

diodes: Junction capacitances are extracted as diodes. Unfortunately this option will not work in

combination with resistance extraction. Therefore it implies switch "no_resistance" and it will reset

switch "epi_resistance" when it has been turned on.

To start the extractor, click on OK in the Extractor form.

The extracted view

After extraction has finished, an extracted view will be present for cell diffamp. This view can be opened

in Virtuoso in the same way as the layout view is opened.

Virtuoso will show the layout that has been extracted including bounding boxes for the extracted

components. To see a symbol representation of the extracted components, press Shift-f in the

Virtuoso window. After zooming in it can clearly be seen that for the extracted components also

the parameters are shown.

Netlisting

The extracted netlist can be viewed by starting from Virtuoso the tool Analog Artist. Click in Virtuoso

Tools -> Analog Artist. Next, in the Analog Artist window, click Setup -> Simulator/Directory/Host ...

and choose for Simulator spectreS. We use the spectre format to view the netlist since this format is better

readable than e.g. the SPICE netlist format. Click OK to finish the Setup Simulator/Directory/Host

window. Next, click Simulation -> Netlist -> Create Final in the Analog Artist window and the

extracted netlist will appear after some time in a separate window:

* # FILE NAME: /U/38/38/ARJAN/SIMULATION/DIFFAMP/SPECTRES/EXTRACTED/

* begin cppStatements

#include

* end cppStatements

* netlist/diffamp.c.raw

* Netlist output for spectreS.

* Generated on Aug 9 13:25:36 2001

simulator lang= spectre

* File name: dimes03Tutorial_diffamp_extracted.s.

* Subcircuit for cell: diffamp.

* Generated for: spectreS.

* Generated on Aug 9 13:25:39 2001.

c26 (vee 5) capacitor c=36.5700003645327e-15





c36 (vcc vee) capacitor c=158.944702560206e-15

c38 (gnd vee) capacitor c=83.4840009622528e-15

c40 (out vee) capacitor c=108.811139894367e-15

c42 (in vee) capacitor c=30.3480012658636e-15

c44 (vcc 5) capacitor c=52.9920007072242e-15





c54 (gnd vcc) capacitor c=13.8240003686309e-15

c56 (out vcc) capacitor c=13.8240003686309e-15









c74 (out vcc) capacitor c=3.53199991159187e-15

q76 (4 4 5) npn4x1 area=1

q78 (3 gnd 1) npn2x1 area=1

q80 (out in 1) npn2x1 area=1

q82 (1 4 2) npn4x1 area=1

r84 (vcc 3) resistor isnoisy= yes r=10.0271162611408e3

r86 (gnd 4) resistor isnoisy= yes r=10.0271162611398e3

r88 (vcc out) resistor isnoisy= yes r=10.0271162612117e3

r90 (5 vee) resistor isnoisy= yes r=414.198315710745

r92 (2 vee) resistor isnoisy= yes r=414.198315691536

simulator lang= spice



.model npn2x1 npn IS=6.1E-18 NC=1.6000 VJC=.4 BF=195

+MJC=.2 NF=1.0080 RE=60 CJS=123E-15 VAF=45

+RB=600 VJS=.5 IKF=10.000E-3 RC=250 MJS=.1

+ISE=1.300E-18 RBM=100 TF=10E-12 NE=1.9000 IRB=8E-6

+XTF=25 BR=9 CJE=11.0000E-15 VTF=2 VAR=1.6000

+VJE=1 ITF=8.0000E-3 IKR=10.000E-3 MJE=.6 PTF=60

+ISC=2.100E-18 CJC=16.0000E-15 TR=1.0000E-9

* FOR PSPICE: NK=.57063

.model npn4x1 npn IS=12.200E-18 RE=30 CJS=138E-15 BF=195

+ RB=300 VJS=.5 NF=1.0080 RC=125 MJS=.1 VAF=45

+ RBM=50 IKF=16.000E-3 IRB=16E-6 XTF=25

+ISE=2.6000E-18 CJE=20.000E-15 VTF=2 BR=9 VJE=1

+ITF=16.00E-3 VAR=1.6000 MJE=.6 PTF=60 IKR=200.00E-6

+CJC=22.000E-15 TR=1.0000E-9 ISC=4.2000E-18 VJC=.4 NC=1.6000

+MJC=.2

* FOR PSPICE: TP=9.0000E-12



* Include files


* End of Netlist

*

simulator lang=spectre

tempOptions options

+ temp= 27

keepAllVoltages options save=allpub

simOptions options

+ reltol=1m

+ vabstol=1u

+ iabstol=1p

+ tnom=27

+ scalem=1

+ scale=1

+ gmin=1p

+ rforce=1

+ maxwarns=5

+ digits=5

+ cols=80

+ pivrel=1m

+ ckptclock=1.8K

modelParameter info what=models where=rawfile

element info what=inst where=rawfile

outputParameter info what=output where=rawfile

DIMES03 Design Tutorial - LVS

Running LVS

Open the extracted view of cell diffamp. Click on Verify -> LVS.... For Rules File use divaLVSr.rul.

This LVS rule will compare the transistors and resistors. To compare only transistors, use divaLVS.rul.

To compare transistors and capacitors, use divaLVSc.rul. To compare transistors, resistors and capacitors,

use divaLVSrc.rul.

In the LVS window, click on Run. If a window pops up with the question to save the extracted

cell view, click OK. However, it has been noted that on an HP Cadence sometimes crashes then.

Therefore it is better to first save the open design(s) from their Virtuoso window using Design ->

Save.

After some time, the Analysis Job Succeeded window will appear to notify that the LVS job has

finished. Click on OK in that window.

Viewing LVS output

To view the LVS output, click on Output in the LVS window. A window will appear showing the results

of the LVS:

@(#)$CDS: LVS version 4.4.3 08/26/1999 02:08 (cds10500) $

Like matching is enabled.

Net swapping is enabled.

Using terminal names as correspondence points.

Net-list summary for /u/38/38/arjan/cad/dimes03/LVS/layout/netlist

count

10 nets

5 terminals

2 npn2x1

2 npn4x1

5 res

25 cap

Net-list summary for /u/38/38/arjan/cad/dimes03/LVS/schematic/netlist

count

10 nets

5 terminals

2 npn2x1

2 npn4x1

5 res

Terminal correspondence points

1 gnd

2 in

3 out

4 vcc

5 vee

The net-lists match.

layout schematic

instances

un-matched 0 0

rewired 0 0

size errors 0 0

pruned 0 0

active 34 9

total 34 9

nets

un-matched 0 0

merged 0 0

pruned 0 0

active 10 10

total 10 10

terminals

un-matched 0 0

matched but

different type 0 0

total 5 5

Probe files from /u/38/38/arjan/cad/dimes03/LVS/schematic

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:

prunedev.out:

audit.out:

Probe files from /u/38/38/arjan/cad/dimes03/LVS/layout

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:

prunedev.out:

I /+33

? Device removed because of user's 'removeDevice' request.

I /+32


I /+31


I /+30


I /+29


I /+28


I /+27


I /+26


I /+25


I /+24


I /+23


I /+22


I /+21


I /+20


I /+19


I /+18


I /+17


I /+16


I /+15


I /+14


I /+13


I /+12


I /+11


I /+10


I /+9


audit.out:

Note that the output shows that capacitors have been removed from the extracted view (Device removed

because of user's 'removeDevice' request) before the netlists were compared. This was done since we are

use an LVS rule file in which only transistors and resistors are comapred.

Viewing LVS errors

As an example of viewing LVS errors we will intentionally create an error in the layout view of cell

config by deleting the layout instance res500lp that is connected to the npn4x1 transistor of the input

stage (or the the lower left resistor in the layout, see also the layout that is shown below). Extract the

layout and run LVS again, similar to as described above. When the LVS job has finished, click on

Output and see that now the netlists failed to match.

@(#)$CDS: LVS version 4.4.3 08/26/1999 02:08 (cds10500) $

Like matching is enabled.

Net swapping is enabled.

Using terminal names as correspondence points.

Net-list summary for /u/38/38/arjan/cad/dimes03/LVS/layout/netlist

count

10 nets

5 terminals

2 npn2x1

2 npn4x1

4 res

23 cap

Net-list summary for /u/38/38/arjan/cad/dimes03/LVS/schematic/netlist

count

10 nets

5 terminals

2 npn2x1

2 npn4x1

5 res

Terminal correspondence points

1 gnd

2 in

3 out

4 vcc

5 vee

Ill-defined correspondence points.

N8 N4 Accepted because one is a subset of the other

Device summary for schematic

bad total

res 1 5

The net-lists failed to match.

layout schematic

instances

un-matched 0 1

rewired 0 0

size errors 0 0

pruned 0 0

active 31 9

total 31 9

nets

un-matched 2 2

merged 0 0

pruned 0 0

active 10 10

total 10 10

terminals

un-matched 1 1

matched but

different type 0 0

total 5 5

Probe files from /u/38/38/arjan/cad/dimes03/LVS/schematic

devbad.out:

I /R0

? Device does not cross-match.

netbad.out:

N /vee

? Net does not cross-match. It has 3 connections.

N /net24


mergenet.out:

termbad.out:

T -1 vee /vee

? Terminal vee in the schematic failed to match any terminal in the layout.

prunenet.out:

prunedev.out:

audit.out:

Probe files from /u/38/38/arjan/cad/dimes03/LVS/layout

devbad.out:

netbad.out:

N /7


N /vee


mergenet.out:

termbad.out:

T -1 vee /vee

? Terminal vee in the layout failed to match any terminal in the schematic.

prunenet.out:

prunedev.out:

I /+30


... etc ..

To view the errors in the extracted view, click on Error Display in the LVS window. The LVS

Error Display window appears. Next, click on the Virtuoso window that displays the extracted

view of cell diffamp (or open it if it is not yet open). Click on First in the LVS Error Display

window to see the first error that is found for the extracted view. A net in the layout for which no

matching net was found in the schematic view, is highlighted. Next, click on Next and Prev to

browse through the other errors.

To view the errors in the schematic view, open the schematic view of diffamp or click in the

corresponding Composer window when the view is already open. Next, use the button First,

Next, Prev etc. to browse through the errors that are found for the schematic view.

Click on OK to close the LVS Error Display Window and close the schematic and extracted

windows.

DIMES03 Design Tutorial - Re-simulation

Creating a config view for simulation

To re-simulate the diffampConfig circuit we will create a so-called config view in which we can specify

that for the instance of the diffamp cell we use the extracted view rather than the schematic view. The

config view will allow us to use for the simulation of the extracted view of cell diffamp, the same

simulation environment as defined in Section Simulation.

To create a config view for cell diffampConfig, in the library manager, select library

sic3aTutorial and click on File -> New -> Cell View. In the Create New File form, use for

Library Name sic3aTutorial, for Cell Name diffampConfig, and for Tool Hierarchy-Editor.

Notice that automatically for View Name config will be filled in. After clicking OK the

Hierarchy Editor window will appear with the New Hierarchy window on top of it. In the New

Hierarchy window, choose cdsSpice for Template Built-in. Note that a config view is specific for

some kind of simulator. When you want to use a config view for another simulator, you have to

create another view with the Hierarchy Editor, e.g. called config2. Next, for Top Cell View type

schematic and in the Global Bindings View List add the word extracted at the end of the line.

Click on OK and the Hierarchy Editor will show the following contents:

http://icdfs0.et.tudelft.nl/cadmgr/dimes03Tutorial/simulation.html

The window lists the cells that are present in the diffampConfig cell hierarchy and the views that

are found and used for these cells.

Selecting the extracted view for simulation

To select the extracted view of diffamp for simulation rather than the schematic view, in the Hierarchy

Editor window, position the cursor on the View To Use rectangle after the cell diffamp, click the right

mouse button. and select Select -> extracted. Both in the rectangles View Found and the rectangle View

to Use after diffamp, the string extracted will now be displayed.

Next click on File -> Save to save the information.

Opening the schematic config view

In the Hierarchy Editor window, in the section Top Cell, click on Open. A Composer window will appear

for the schematic view of the diffampConfig cell.

Loading previous simulation settings

Open the simulation interface from the schematic window using Tools -> Analog Artist. Use Session ->

Load State .. to obtain the Loading State window. For State Name, select the name that you used in

Section Simulation. to store the simulation state. and next click on OK. Next the Analog Artist window

will display the reloaded simulation environment and a simulation can be performed similar as in Section

Simulation.



DIMES03 Design Tutorial - Chip Finishing

Introduction

After you have successfully performed all verification steps, you are almost ready to export your design

as a GDS file and send it to the fabrication facility. However, to finish the design, bondpads need to be

added, and the design should be placed (possibly together with other designs if you make a multi-project

chip) on the chip.

Adding bondpads

The dimes03Lib library contains two bondpad cells that can be used to make connection between your

chip design and the outside world. Cell `pad' is a bondpad cell that has dimensions 100 x 100 micron, and

cell `padHF' is a bondpad cell (for HF applications) that has dimensions 50 x 50 micron. Add either cell

`pad' or cell `padHF' to your schematic and next synthesize the layout again, similar as described in

Section Layout Synthesis. You can e.g. create a new schematic cell diffampChip, where you use cell

diffamp as an instance and next add the instances of the pad cells.

Then, when you synthesize the layout of diffampChip, the layout of cell diffamp, as created

previously, will be re-used as an instance.

http://icdfs0.et.tudelft.nl/cadmgr/dimes03Tutorial/layout.html

Usually, when designing a circuit, it is recommanded to perform also a DRC on the final layout

cell, as well as to extract and re-simulate the cell.

Placement of the Design(s) on the Chip

A DIMES03 chip has a maximum size of 1 x 1 cm. Thus, in principle, if the designs are small enough,

several different designs can be put on one IC, resulting in a so-called multi-project chip. Usually, if more

than one different design is put on the IC, it is best to create a new library where you collect all the

designs that are involved. In that case, copy the top level cell of each design, as well as all sub-cells that

are in the hierarchy below each top level cell (watch the possibility of the use of cells with the same name

in different design hierarchies !). In this tutorial, where we have only one design, we will assembly the

final IC layout in the dimes03Tutorial library.

The final layout should obey the rules as described in Section 4.2 and 4.3 in the DIMES03

Design Manual. For our single design chip, this can be achived as follows.

Create a new layout cell, e.g. called tutorialIC. Add an instance of the layout cell CADRE3 from

library dimes03Lib at position (0, 0). This instance denotes the area within which the design

should be placed. Expand the layout by pressing Shift-F to see where there is empty space, which

defines the area that is available. Finally, add an instance of diffampChip somewhere in the

middle and save the layout.



DIMES03 Design Tutorial - Generating a

GDS File

To generate a GDS file that contains a description of the layout of your design suitable for

sending to the IC processing department, click on File -> Export -> Stream .... The following

form will appear. For the field Library Name use dimes03Tutorial, for the field Top Cell Name

use tutorialIC, the name of teh cell that was created in the Section Chip Finishing, for View

Name use layout, and for Output Flile, use something like tutorialIC.gds.

If you want to store information about pin names and instance names in the GDS file as well,

click on User-Defined Data. Fill out the form that pops up as follows in order to convert pin

names and instance names to GDS attributes with number 99.

http://icdfs0.et.tudelft.nl/cadmgr/dimes03Tutorial/finish.html

Next click on OK in the Stream Out User-Defined Data form. Finally click on OK in the Stream

Out form and wait until a message appears that PIPO STRMOUT completed successfully and the

file tutorialIC.gds has been generated.

cadence icfb design tutorial

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