cadence soc encounter tutorial

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Cadence SOC Encounter Tutorial

Cadence SOC Enco n er T orialBa ed on P of. Mi cea S an' T o ial a he Uni e i of Vi ginia The follo ing Cadence CAD ool ill be ed in hi o ial:

SOC Enco n er fo backend de ign (floo planning, place and o e, po e and clock di ib ion). Yo ma an o e i i Sim la ion T o ial and Logic S n he i T o ial befo e doing hi ne o ial.

R nning he Cadence backend ool No o ho ld be able o n he Cadence ool . Ne e n Cadence f om o oo di ec o , i c ea e man e a file ha ill cl e o oo . In ead plea e c ea e a di ec o (e.g. cadence, o ho ld ha e hi al ead ) and ano he di ec o fo he de ign (e.g. o ial, ho ld ha e i ), link he lib a file o o di ec o ch ha i ill be ea ie o na iga e o hem, and finall one fo he enco n e file (e.g. enco n e ): c d oil a l - /p/aec/oa/ _o_27cdnelb m05lb. n o cdnelclo c ./aec/i/ c2/i md ec ne ki no c ec ne d no

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F om he enco n e di ec oec ne no

The command e c n e (no &) a no

SOC Enco n e in he fo eg o nd and o

ho ld ge he enco n e

a p indo :

eeweb.pol .edu/labs/nanovlsi/tutorials/soctutorials/Tutorial_Encounter.html

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The indo ha h ee main a ea : Menu Bar ( op) Select Bar ( igh ) Displa Area (middle) Plea e o familia i e o elf i h he main indo , click on he men , on he Toolba idge , e c. Fo mo e info ma ion on he a io Cadence ool I enco age o o ead he co e ponding man al . Yo can ge o he men efe ence man al fo Enco n e b p e ing Help on he igh of he Men Ba . Yo can al o di ec l acce doc men a /op /cadence/SOC62/doc/enco n e . Fo ho e ha an o lea n Enco n e in o mo e dep h he e a e ome eall nice o ial in /op /cadence/SOC62/ ha e/fe/gif / o ial /d mf/ o k_fe. Spend ome ime b o ing he man al o nde and ha i a ailable (a lo !). D ing he eme e o ill ha e o look fo info ma ion in he on-line man al o complemen he (limi ed) info p o ided in he e o ial . Yo can hink of hi o ial a a in b e of he one a ailable nde help. No e can a ing Enco n e . Fi e need o impo he n he i ed ne li ( he e l of RTL n he i i h RTL Compile ). Click on Design -> Import Design... and he De ign Impo indo ho ld pop- p (a an a ide, i eem o can al o impo RTL di ec l , I a me hi mean o can do RTL n he i in Enco n e di ec l i ho ing RC, i o ld be in e e ing o hi and ee ho i o k ). No o need o fill in he Ve ilog ne li ( e he b o e b on on he igh o na iga e o o n he i ed ne li , in m ca e acc _ n h. in ../ n he i , make e o click on Add, hen on Clo e

Then click on A o A ign fo he Top Cell a ignmen . Then e need o pecif he ph ical defini ion fo he lib a , do ha b clicking on he na iga e b on on he igh of he LEF File en hich ho ld pop- p he LEF File indo . Na iga e o he lib di ec o ( ha o j linked in o o o ial di ec o , in m ca e a ../lib) hen click on o 025_ dcell .lef, and finall on Add, hen on Clo e

Then e need o pecif he iming defini ion fo he lib a , do ha b clicking on he na iga e b on on he igh of he Common Timing Lib a ie en hich ho ld pop- p he Timing File indo (no e ha mo e ad anced lib a ie ill ha e Ma Timing and Min Timing Lib a ie in o de o be able o do "co ne anal i ", no j nominal anal i ). Na iga e o he lib di ec o ( ha o j linked in o o o ial di ec o , in m ca e a ../lib) hen click on o 018_ dcell . lf, and finall on Add, hen on Clo e


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No mall , if hi a a f ll chip de ign, e o ld al o ha e o pecif he I/O pad info ma ion no b he IO A ignmen File, b fo no ill no e I/O pad . Yo De ign Impo pop- p indo ho ld look like hi no

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No click on he Ad anced ab a he op follo ed b Po e on he lef . Fill in dd fo Po e Ne and gnd fo G o nd Ne (o of c io i o can check ha indeed he e a e he name of he po e and gnd ne in o Ve ilog ne li b opening he file in a e edi o ).


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N c ic he IPO/CTS a d fi b f f B ffe Na e/F i a d i f I e e Na e/F i ( i deed he e a e he f i a e b e a i i g he . f fie i he ib di ec ). A c ic Ge e a e F E i a e ce.

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Now we need to specif floorplaning information. Since our design is simple and flat there is not much that needs to be done, but in general now is the time to decide how the big blocks that make up the design should be placed with respect to each other. Click on Floorplan -> Specif Floorplan and change Core to Left, Core to Right, Core to Top and Core to Bottom to 100.00 (default is 0.00). Also, change Ratio (H/W) to 1.


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Click on Appl and the floorplan should change to reflect the 100 micron peripher around the core.

Now ou can also pla with the aspect ratio on the Specif floorplan window, change that to 0.5, click Appl , then to 2, click Appl again, finall back to 1 and click Appl . Note how the number of rows in our floorplan changes from 5 (for 1) to 7 (for 2) to 3 (for 0.5). It is a good idea toeeweb.pol .edu/labs/nanovlsi/tutorials/soctutorials/Tutorial_Encounter.html 6/15

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a e o

de ign f om ime o ime b Design -> Sa e Design As -> SoCE...

The ne ep i o c ea e he po e and g o nd connec ion , b fi o ha e o pecif he ne . Click on Floorplan -> Connect Global Nets... and hen fill he pop- p indo connec ing pin dd o global ne dd, and pin gnd o global ne gnd, making e he b on Appl All i checked (need o do hi one a a ime b adding o li ). Click Appl , hen Check (make e he e a e no a ning he e), hen Cancel o clo e he pop- p.

No e can finall c ea e he po e di ib ion fo o de ign. Click Po er -> Po er Planning -> Add Rings.... Choo e me al 4 and me al 5 i h he id h and pacing of 8 and 1 and i h off e of 1, hen click Appl , follo ed b Cancel.


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Click Po er -> Po er Planning -> Add Stripes.... Choose metal 5 with the width and spacing of 8 and 1 and with Y from bottom of 30, then click Appl , followed b OK.


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Then, in order to route the rest of the power distribution click Ro e -> Special Ro e..., deselect Pad pins, then click Appl , followed b OK.


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Now our floorplan should look like this.


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I i ime o place o

cell , go o Place -> S anda d Cell and Block ... hen click Appl , follo ed b OK.

In o de o a oid DRC e o la e , i i all a good idea o place fill cell o fill in he gap be een o placed anda d cell . To do hi , go o Place -> Fille -> Add Fille ... and in he indo ha come p, p e he op Selec b on ne o he Cell Name( ) fo m. A indo ill pop p and in he igh col mn o ho ld ee a line ha a FILL. Selec FILL f om he igh ide, click Add follo ed b OK. In he Add Fille indo o ho ld no ee FILL in he op fo m. Click Appl follo ed b OK.


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Now, if ou click on the Ph sical View widget (on the right of the second row of the widget menu, right to the left of All Colors, it looks like a transistor la out) ou will see our placed design.

Finall we can also route our design, go to Ro e -> NanoRo e -> Ro e... and click Appl followed b OK.


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And now our design should be also routed:


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Since we don't have pads in our design the tools route the primar inputs and outputs to the peripher of the floorplan such that the can in principle be connected in a hierarchical fashion to other blocks. Now that ou have completed the ph sical design of our circuit it is a good idea to verif it b running a DRC check. To do this in SoC Encounter, select Verif -> Verif Geometr ... and then click OK. Make sure there are no violations listed in the terminal window.


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Cong a la ion , hi i he end of he SoC Enco n e

o ial.


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