chapter 6 soc encounter

7/26/2019 Chapter 6 Soc Encounter

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Cell-Based IC Physical Design and Verification

- SOC Encounter

CIC 2006/02


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2

Class Schedule

Day1 Design Flow Over View

Prepare Data

Getting Started

Importing Design

Specify Floorplan

Power Planning

Placement Synthesize Clock Tree

Day2 Timing Analysis

Trial Route

Power Analysis

SRoute

NanoRoute

Fill Filler

Output Data DRC

LVS

extraction/nanosim


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3

Chapter1

Cell-Based Physical DesignSOC Encounter 4.2


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4

Cell-Based Design Flow

synthesis

Routed

design

Add LVS/Nanosim text

Replace layout

GDSII

DRC LVS

Post layout simulation

Tape out

Gate level

netlist

VerilogVHDL

Place & Route


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5

SOC Encounter P&R flow

IO,P/G Placement

Specify floorplan

Amoeba Placement

Power Planning

Timing Analysis

Clock Tree Synthesis

Timing Analysis

Post-CTS Optimization

Power Analysis

IO constraints

Power Route

SI Driven Route

Timing/SI Analysis

Output GDS, Netlist,Spef,DEF

Pre-CTS Optimization

Netlist (verilog)

Timing constraints (sdc)


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6

IO, P/G Placement

VDD

VSS

IOVDD IOVSS

I1

I2

I3

I4

O2

O1

O3

O4

Corner1 Corner2

Corner3 Corner4


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Specify Floorplan

Hight

Width


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Floorplan

VDD

VSS

IOVDD IOVSS

I1

I2

I3

I4

O2

O1

O3

O4

M2

M1 M3


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9

Amoeba Placement


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Power Planning


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Clock Tree Synthesis

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

CLK

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

CLK


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Power Analysis


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Add IO Filler


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Routing


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Prepare Data

Library Physical Library (LEF) Timing Library (LIB)

Capacitance Table

Celtic Library

FireIce/Voltage Storm Library

User Data

Gate-Level netlist (verilog)

SDC constraints

IO constraint


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LEF Format

-- Process Technology

Layers Design Rule ParasiticPOLY

Metal1

Metal2

Contact

Via1

Net widthNet spacing

AreaEnclosureWide metalslotAntennaCurrent density

ResistanceCapacitance


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LEF Format

-- APR technology : SITE

The Placement site give the placement grid of a family of

macros

a sitea row


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Row Based PR

VDD

VSS

VDD

VSS


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LEF Format

-- APR technology :routing pitch , default direction

metal2 routing pitch

metal1 routing pitch

Horizontal

routing

Vertical

routingMetal1

Metal3

Metal5

Metal2

Metal4

Metal6

via


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LEF Format

-- APR technology : via generate

To connect wide metal , create a via array toreduce via resistance

Defines formulas for generating via arrays

Layer Metal1

Direction HORIZONTAL

OVERHANG 0.2

Layer Metal2

Direction VERTICALOVERHANG 0.2

Layer Via1

RECT 0.14 0.140.140.14

SPACING 0.56 BY 0.56

Generated via

Default via


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LEF Format

-- APR technology : via stack

Without via stack With via stack

Higher density routing

Easier usage of upper layer

Must Follow minimum area rule


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LEF Format

-- APR technology : Double Cut Via

Metal2

Double cut Via12

Metal1


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LEF Format

-- APR technology : SameNet Spacing

SPACINGSAMENET Metal1 Metal1 0.23 ;

SAMENET Metal2 Metal2 0.28 STACK ;

SAMENET Metal3 Metal3 0.28 ;

SAMENET VIA12 VIA12 0.26 ;

SAMENET VIA23 VIA23 0.26 ;

SAMENET VIA12 VIA23 0.0 STACK ;

END SPACING

Metal1

0.23 same net spacing rule

Metal1 Metal3

VIA12 and VIA23

VIA12 and VIA23 allow stack


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LEF Format

-- APR technology : Physical Macros cont.

VDD

VSS

BA

Y

MACRO ADD1CLASS CORE ;

FOREIGN ADD1 0.0 0.0 ;ORIGEN 0.0 0.0 ;LEQ ADD ;SIZE 19.8 BY 6.4 ;SYMMETRY x y ;SITE coresite ;PIN A

DIRECTION INPUT ;PORTLAYER Metal1 ;RECT 19.2 8.2 19.5 10.3 ;

END

END APIN B

..END BOBS

END

END ADD1


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CeltIC Library

cdB model

The cdB noise library structure

SPICE Transistor Model

Noise Data for Cell 1

.subckt Transistor Description for Cell 1

Noise Data for Cell N

.subckt Transistor Description for Cell N


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FireIce/Voltage Storm Library

lefdef.layermap

#type layer_ict lefdef layer_lef

metal METAL_1 lefdef METAL1

metal METAL_2 lefdef METAL2

metal METAL_3 lefdef METAL3metal METAL_4 lefdef METAL4

via VIA_1 lefdef VIA12




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gate-level netlist

If designing a chip , IO pads , power pads and Corner

pads should be added before the netlist is imported.

Make sure that there is no assign statement and no *cell* cell name in the netlist.

Use the synthesis command below to remove assign statement.set_boundary_optimization

Use the synthesis commands below to remove *cell* cell namedefine_name_rules name_rulemap {{\\*cell\\* cell}}change_nameshierarchyoutput name_rule
http://%2Acell/*http://%2Acell/*http://%2Acell/*http://%2Acell/*


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SDC constraint

-- create_generated_clock

create_generated_clock [-add]

[-master_clock][-name clock_name]

[-source source_pin]

[-multiply_by mult]

[-divide_by div][-duty_cycle percent]

[-neg]

[-edges edge_list]

[-edge_shift edge_shift_list]clock_root_list

create_generated_clockname CLK2source [get_ports I_CLK]divide_by 2 [get_pins DF/QN]

QND

TopI_CLK

div_clk


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Static Timing Analysis

31

3

1

21

32

AT=2

AT=5

RAT=10

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3

1

21

32

AT=2

AT=5

RAT=10

AT=7RAT=7

AT=9RAT=8

AT=6RAT=5

AT=2RAT=5

AT=5RAT=4

AT=11

RAT=10

Path-based:

2+2+3 = 7 (OK)2+3+1+3 = 9 (OK)2+3+3+2 = 10 (OK)5+1+1+3 = 10 (OK)5+1+3+2 = 11 (Fail)

5+1+2 = 8 (OK)

Block-based:

Critical path is determinedas collection of gates withthe same, negative slack:In our case, we see one

critical path with slack = -1


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Static Timing Analysis

Reg to PO

Tarrival = Tclk1+ TDFF1(clk->Q)+TPATH Trequire = Tcycle- TPO(output delay) Tslack= Trequire- Tarrival

Setup time


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IO constraint

Version: 1

MicronPerUserUnit: value

Pin: pinName side |corner

Pad: padInstanceName side|corner [cellName]

Offset: length

Skip: length

Spacing: lengthKeepclear: side offset1 offset2

Create an I/O assignment file manualy using the following template:


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IO constraintcont.

Version: 1

Pad: CORNER0 NW PCORNERDGZPad: PAD_CLK N

Pad: PAD_HALT N

Pad: CORNER1 NE PCORNERDGZ

Pad: PAD_X1 WPad: PAD_X2 W

Pad: CORNER2 SW PCORNERDGZ

Pad: PAD_IOVDD1 S PVDD2DGZ

Pad: PAD_IOVSS1 S PVSS2DGZ

Pad: CORNER3 SE PCORNERDGZ

Pad: PAD_VDD1 E PVDD1DGZ

Pad: PAD_VSS1 E PVSS2DGZ

PA

D_CLK

PA

D_HALT

P

AD_IOVDD1

PAD_IOVSS1


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SSO Consideration

SSO

Simultaneously Switch OutputsSSN The noise produced by SSO buffers

DI maximum number of copies for one specific kind of I/O pad

switching from high to low simultaneously without makingground voltage level higher than 0.8 volt for one ground pad

DF Drive Factor, DF = 1/DI

SDF

Sum of Drive Factor


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Design Views

FloorplanView

displays the hierarchical module and blockguides,connection flight lines and floorplan objects

Amoeba View display the outline of modules after placement

Placement View display the detailed placements of cells, blocks.


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Display Control

Select Bar


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Common Used Bindkeys

Key Action

q Edit attribute

f Fits display

z Zoom in

Z Zoom out

Arrows pans design area in thedirection of the arrow

Escape Cancel

K Removes all rulers

Key Action

space Select Next

e popup Edit

T editTrim

0-9 toggle layer[0-9] visibility

h/H hierarchy up/down

x clear Drc

Looking for more bindkey:Design->Preference, Binding Key


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Import Design -- Power


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Specify the names of Power Nets and Ground Nets

Import Design IPO/CTS


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Import Design IPO/CTS


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Import Design Power


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Specify Floorplan


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Specify Floorplan

FloorplanSpecify Floorplan

Specify Floorplan Doube back rows


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Spec y oo p a oube bac ows

Double-back rows:Row Spacing > 0

Row Spacing = 0


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Place Blocks


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FloorplanPlace Blocks/ModulesPlace

automatic place blocks ( blackboxesand partitions) and hard macros at thetop-level design.

Block halo

Specifies the minimum amount ofspace around blocks that is preservedfor routing.


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Block Placement

Preserve enough power pad

Create power rings around blockFollow default routing direction rule

Reserve a rounded core row area for placer

Default direction

block


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Power Planning: Wire Group


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Use wire group

no interleavingnumber of bits = 2

Use wire group

interleavingnumber of bits = 2

Power Planning: Block Ring


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Power Planning: Add Stripes


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Edit Route cont.


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Trim wire

Fix wire wider

than max width


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Difference Floorplan

Difference Performance


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Difference Performance

Wire Load After Placement


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Logical wire load after placement


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Add Tiehi/Tielo cell


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Tiehi/Tielo cell connect tiehi/tielo net to supply voltage or

ground with resisterTiehi/Tielo cell is added for ESD protection.

Set add tiehi/tielo cell mode:

encounter>setTieHiLoMode maxFanOut #num maxDistance #num

PlaceTieHiLoAdd TieHiLo


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Synthesize Clock Tree


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Create Clock Tree Spec

clock spec

Specify Clock Tree Modify

Synthesis Clock Tree netlistsynthesis report

clock nets

routing guideDisplay Clock Tree


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CTS spec.


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A CTS spec. contain the following information.

Timing constraint file (optional) Naming attributes (optional)

Macro model data (optional)

Clock grouping data (optional)

Attributes used by NanoRoute routing solution (optional)

Requirement for manual CTS or automatic CTS

CTS spec.

--Naming Attributes Section


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TimingConstraintFilefilename

define a timing constraint file for use during CTS

NameDelimiter delimiter

name delimiter used when inserting buffers and updating clockroot and net names.

NameDelimiter # create names clk##L3#I2

default clk__L3_I2

UseSingleDelim YES|NO

YES clk_L3_I2

NO clk__L3_I2 (default)


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CTS Spec.

--Manually Define Clock Tree Topology


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ClockNetName netName

LevelNumber number Specify the clock tree level number

LevelSpec levelNumber numberOfBuffers bufferType levelNumber

Specify the level number in the clock tree

numberOfBuffer

the total number of buffers CTS should allow on the specified level

Example:LevelSpec 1 2 CLKBUFX2

LevelSpec 2 2 CLKBUFX2

End

CTS Spec.

-- Automatic Gated CTS Section


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AutoCTSRootPin clockRootPinName

MaxDelay number{ns|ps}MinDelay number{ns|ps}

SinkMaxTran number{ns|ps}

maximum input transition time for sinks(clock pins)BufMaxTran number{ns|ps}

maximum input transition time for buffers (defalut 400)

MaxSkew number{ns|ps}

CTS Spec.

-- Automatic Gated CTS Section cont.


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NoGating {rising|falling|NO}

rising : stops tracing through a gate(include buffers and inverters) and

treats the gate as a rising-edge-triggered flip-flop clock pin. falling: stops tracing through a gate(include buffers and inverters) and

treats the gate as a falling-edge-triggered flip-flop clock pin.

No: Allows CTS to trace through clock gating logic. (default)

AddDriverCell driver_cell_name

Place a driver cell at the cloest possiblelocation to the clock port location .


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Display IR Drop


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Crosstalk

Crosstalk problem are getting more serious in 0.25um andbelow for:


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below for:

Smaller pitches Greater height/width ratio Higher design frequency


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CeltIC Crosstalk Analysis

SIRun CeltIC Crosstalk Analysis


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Antenna Effect

In a chip manufacturing process, Metal is initially deposited


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so it covers the entire chip.Then, the unneeded portions of the metal are removed by

etching, typically in plasma(charged particles).

The exposed metal collect charge from plasma and formvoltage potential.

If the voltage potential across the gate oxide becomes large

enough, the current can damage the gate oxide.

Antenna Ratio

Plasmametal2 metal2

Plasma


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+ + + + + +

gate oxidepoly

metal1

via1

Antenna Ratio =Area of process antennas on a node

Area of gates to the node

via2 + + + + + + +


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Add bonding pads flow (stagger IO pads only)

A placed and routed

design in encounterrouted.def

routed.def

Export DEF

(In encounter)


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bondPads.ecobondPads.eco

bondPads.cmdbondPads.cmd

addbonding.pl routed.def

(In unix terminal)

source bondPads.cmd

(In encounter terminal)

finish

addbonding.pladdbonding.pl

ioPad.listioPad.list

Output Data

DesignSaveGDS

DesignSave->Netlist


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Export GDS for DRC,LVS,LPE,and tape out.

Export Netlist for LVS and simulation.

Export DEF for reordered scan chain.

DesignSave->DEF


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Post-Layout Verification Overview

Post-Layout Verification do the following things : DRC ( Design Rule Check )


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ERC (Electrical Rule Check )

LVS (Layout versus Schematic )

LPE/PRE (Layout Parasitic Extraction / Parasitic Resistance

Extraction) and Post-Layout Simulation.


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DRC flow

Prepare Layout stream in gds2


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add power pad text

stream out gds2

Prepare command file

run DRC

View DRC error (DRC summary/RVE)

Prepare Layout

Stream In design

S I d 2


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Add power Text

Stream Out

DFII

Library

GDSIIGDSII

Stream In core gds2

Stream In IO gds2

LEF in RAM lef


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Prepare Layout: Add Power Text

Add power text for LVS and Nanosim

Example: For TSMC18/artisan library


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Add text DVDD for IO power pad

Add text DVSS for IO ground pad

Add text VDD for core power pad

Add text VSS for core ground pad


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Using Calibre RVE

Add in .cdsinit


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setSkillPath(. ~/ /usr/memtor/Calibre_ss/cur/shared/pkgs/icb/tools/queryskl)

load(calibre.skl)

Using Calibre RVE


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Initial Correspondence Points

Initial correspondence points establish a starting place forlayout and schematic comparison.

Create initial correspondence node pairs by


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Create initial correspondence node pairs by adding text strings on layout database.

all pins in the top of schematic netlist will be treated as an initial

corresponding node if calibre finds a text string in layout whichmatches the node name in schematic.

a

b.

.

.

. . .

VDD

a

b. . .

initial correspondingnode pairs

global pin : VDD and GND

Black-Box LVS

Calibre black-box LVS

One type of hierarchical LVS.


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One type of hierarchical LVS. Black-box LVS treats every library cell as a black box.

Black-box LVS checks only the interconnections between librarycells in your design, but not cell inside.

You need not know the detail layout of every library cells.

Reduce CPU time.


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LVS flow

Prepare Layout

The same as DRC Prepare Layout


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p yPrepare Netlist v2lvs

Prepare calibre command file run calibre LVS

View LVS error (LVS summary/RVE)

Prepare Netlist for Calibre LVS

Prepare Netlist

Verilog

CHIP.v

Verilog

CHIP.vumc18lvs v

umc18lvs.v


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v2lvsv CHIP.vl umc18lvs.vo source.spis umc18lvs.spis1 VDDs0GND

If a macro DRAM64x16 is used

v2lvsv CHIP.vl umc18lvs.vl DRAM64x16.vo source.spisumc18lvs.spis DRAM64x16.spis1 VDDs0 GND

CHIP.spiCHIP.spi

v2lvs

umc18lvs.v

umc18lvs.spiumc18lvs.spi


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Black Box related file

Pseudo spice file.GLOBAL VDD VSS

.SUBCKT AN2D1 Z A1 A2 VDD GND.ENDS


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Pseudo verilog file

module AN2D1 (Z, A1, A2);output Z;

input A1;

input A2;

endmodule

Prepare command file for Calibre LVS

Edit Calibre LVS runset

LAYOUT PATH CHI P. cal i br e. gds

LAYOUT PI MARY CHI PLAYOUT SYSTEM GDSI I


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SOURCE PATH CHI P. spi SOURCE PRI MARY CHI P

I NCLUDE / cal i br e/ LVS/ Cal i br e- l vs- cur

Edit Calibre LVS rule file

LVS BOX PVSSCLVS BOX PVSSRLVS BOX DRAM64x4s

Submit Calibre LVS

calibre lvs spice layout.spi hierauto

umc18LVS.cal > lvs.log


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layout verilog

source.spilayout.spi

v2lvsextract


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Check Calibre LVS SummaryOVERALL COMPAISON RESULTS

OVERALL COMPARISON RESULTS


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# ################### _ _

# # # * *

# # # CORRECT # |

# # # # \___/

# ###################

Check Calibre LVS Summary

CELL SUMMARY

*************************************************

CELL SUMMARY

*************************************************


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Result Layout Source

----------- ----------- --------------

CORRECT CHIP CHIP


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Check Calibre LVS Summary

Initial Correspondence Points

o Initial Correspondence Points:

Nets: DVDD VDD DGND GND I_X[2] I_X[3] I_X[4]I X[5] I X[6] I X[7] I X[8] I X[9] I X[10] I X[11]


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I_X[5] I_X[6] I_X[7] I_X[8] I_X[9] I_X[10] I_X[11]O_SCAN_OUT O_Z[0] O_Z[1] O_Z[2] O_Z[3] I_HALT

I_RESET_ I_DoDCT I_RamBistE I_CLK I_SCAN_INI_SCAN_EN I_X[0] O_Z[4] I_X[1] O_Z[5] O_Z[6]O_Z[7] O_Z[8] O_Z[9] O_Z[10] O_Z[11]

Check Calibre LVS Log

TEXT OBJECT FOR CONNECTIVITY EXTRACTION

PORTS

Extraction Errors and Warnings for cell CHIP


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Check Calibre LVS LogPORTS

--------------------------------------------------------------------------------

PORTS

--------------------------------------------------------------------------------

O_Z[0] (523.447,31.68) 105 CHIP O_Z[1] (598.068,31.68) 105 CHIP

( ) ( )


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O_Z[2] (821.931,31.68) 105 CHIP O_Z[3] (896.553,31.68) 105 CHIP

O_Z[4] (971.175,31.68) 105 CHIP O_Z[5] (1164.455,372.964) 105 CHIP

Check Calibre LVS Log

Extraction Errors and Warnings for cell CHIP

Extraction Errors and Warnings for cell "CHIP"----------------------------------------------

WARNING: Short circuit - Different names on one net:Net Id: 18

(1) "GND" l i (330 301 216 95) l 102 "M2 TEXT"


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(1) name "GND" at location (330.301,216.95) on layer 102 "M2_TEXT"(2) name "GND" at location (673.2,29.1) on layer 101 "M1_TEXT"(3) name "VDD" at location (748.1,31.5) on layer 101 "M1_TEXT"(4) name "VDD" at location (208.93,274.56) on layer 101 "M1_TEXT"The name "VDD" was assigned to the net.


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What Introduce After Place&Route?

Interconnection wiresparasitic resistance.M1 parasitic resistanceM2

VIA


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M2 parasitic resistance

VIA parasitic resistance

vdd!

gnd!

vdd!

gnd!

M1

Pre-Layout And Post-Layout Design

A pre-layout design (before P&R) and a post-layout design(after P&R)

pre-layout


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post-layout

Why Post-Layout Simulation?

clock skew


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. . . .

clkdata

. . .. . .

critical path delay

data

critical path delay


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Transistor-level Post-layout Simulation

layout

netlist/parasiticextraction Calibre LPE/PRE


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SPICE netlist

Post-layout

simulation

simulation

pattern

simulationresult

Nanosim


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Prepare for Post-Layout Simulation

Apply for a CIC account

http://www.cic.org.tw.

fill in your personal data and your request. Install identdprogram


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this program is used to identify yourself when you log into CICsaccount from remote machine.

Put your DB file to CICs account

Replace Layout / LPE

Qentry

M {LPE}

tech {UMC18 | TSMC18 | TSMC25 | TSMC35}

f GDSII

T Top_cell_names Ram_spce_filename

t {ra1sd | ra1sh | ra2sd | ra2sh | rf2sh |


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{ | | | | |

t18ra1sh | t18ra2sh | t18rf1sh | t18rf2sh | t18rodsh|

18ra1sh_1 | 18ra1sh_2 | 18ra2sh}

c {UMC18 | TSMC18 | TSMC25 | TSMC35}i {UMC18 | TSMC18 | TSMC25 | TSMC35}

o Netlist_file_name

Example:

Qentry M LPE tech UMC18 f CHIP.gds T CHIPs RAM1.spec t 18ra2sh s RAM2.spec t 18ra1sh_1

s RAM3.spec t 18ra1sh_2 c UMC18 i UMC18 o CHIP.netlist

Use Qstat to check the status of your job.

The result is stored in result_# directory.


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Running Nanosim

QentryM {NANOSIM}n {CHIP.io}

nspice CHIP.netlist spice.headernvec CHIP.vec

m Top_cell_name{CHIP f }


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c {CHIP.cfg}z {CHIP.tech.z}

o Output_file_nameout fsdb

t Total_simulation_time

Example:

QentryM NANOSIMnspice CHIP.netlist spice.headernvecCHIP.vec m CHIPc CHIP.cfgz CHIP.tech.zo UMC18t 100

Use Qstat to check the status of your job.The result is stored in result_# directory.

Spice Header File

Spice Header FileModify PVT

.lib 'l18u18v.012' L18U_BJD .lib 'l18u18v.012' L18U18V_TT


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.lib 'l18u33v_g2.011' l18u33v_tt

*epic tech="voltage 3.3

*epic tech="temperature 100"


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Generate Nanosim Simulation Pattern

t ype nsvtsi gnal CLOCK, START, I N[ 7: 0]; cl ock st ar t i n[ 7: 0]

Input simulation pattern --- nsvtformat


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r adi x 1 1 44i o i i i i

per i od 25hi gh 3. 3l ow 0. 0

0 0 xx1 0 xx

0 0 xx. . . . .


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Nanosim Configuration File

bus_not at i on [ : ]pr i nt _node_l ogi c ADRS[ 0]pr i nt _node_l ogi c CLK

pr i nt _node_l ogi c DATA[ 0]. . . . . .r epor t _node_power VDD

t d d DGND

ExampleNanosim_configuration file


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set _node_gnd DGNDset _node_gnd GNDset _node_v DVDD 3. 3set _node_v VDD 1. 8

ADRS[ 0]

ADRS[ 1]. . . . . .CLKDATA[ 0]. . . . . .

nodename file


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Load Simulation Result --- nWave


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Select Signals --- nWave

Signals Get Signals ...


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Check Simulation Result --- nWave


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Power Analysis Result

The power analysis result is stored in Nanosim simulationlog (xxx.log) file

. . . . . .Cur r ent i nf or mat i on cal cul at ed over t he i nt er val s:

0 00000e+00 - 1 00010e+03 ns


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0. 00000e+00 1. 00010e+03 ns

Node: VDDAver age cur r ent : - 3. 53355e+05 uARMS cur r ent : 3. 53388e+05 uA

Cur r ent peak #1 : - 4. 54061e+05 uA at 6. 78400e+02 ns

Cur r ent peak #2 : - 4. 34973e+05 uA at 4. 00000e- 01 nsCur r ent peak #3 : - 3. 88048e+05 uA at 2. 59000e+01 nsCur r ent peak #4 : - 3. 87280e+05 uA at 1. 27500e+02 nsCur r ent peak #5 : - 3. 84302e+05 uA at 5. 77800e+02 ns

. . . . . .

chapter 6 soc encounter

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