Introduction to VLSI Design ECSE 4220

Rensselaer Polytechnic Institute

Cadence Tutorial Usage and Design process

Asif Jahangir Chowdhury 11-10-2014

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Contents

Table of Figures ............................................................................................................................................. 2

Introduction .................................................................................................................................................. 5

Logging into remote server ........................................................................................................................... 5

Changing License Information ...................................................................................................................... 7

Starting Cadence Environment ..................................................................................................................... 8

Creating New Library .................................................................................................................................... 8

Creating the Schematic of the Inverter ....................................................................................................... 10

Creating the Symbol .................................................................................................................................... 18

Testing the inverter ..................................................................................................................................... 19

Drawing the layout ...................................................................................................................................... 23

Creating Layout XL file .................................................................................................................... 23

Placing the Elements ....................................................................................................................... 24

Routing ............................................................................................................................................ 27

DRC .................................................................................................................................................. 30

LVS (Layout Validated to Schematic) .............................................................................................. 32

Network Extraction to Obtain wire Parasitics ............................................................................................. 37

Extracted Simulation with wire Parasitics for Speed comparison .............................................................. 39

2 input NAND .............................................................................................................................................. 43

Schematic of Circuit ........................................................................................................................ 43

Simulation Waveform (No parasitics) ............................................................................................. 44

Layout .............................................................................................................................................. 45

Design Rule Check ........................................................................................................................... 45

Network extraction to obtain Parasitics ......................................................................................... 46

Extracted simulation with wire parasitics ....................................................................................... 47

Ring Oscillator (Inverter) ............................................................................................................................. 48

Ring Oscillator (NAND) ................................................................................................................................ 53

Ring Oscillator (10X Inverters) .................................................................................................................... 55

Ring Oscillator (10X Inverters with multiple fingers) .................................................................................. 58

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Table of Figures Fig. 1 Remote Desktop Connection Dialog Box --------------------------------------------------------------------------- 5

Fig. 2 Remote Desktop Connection Dialog box after inserting the Server Address ------------------------------ 6

Fig. 3 Server Login Window ---------------------------------------------------------------------------------------------------- 6

Fig. 4 Changing the License Information ------------------------------------------------------------------------------------ 7

Fig. 5 CIW Window --------------------------------------------------------------------------------------------------------------- 8

Fig. 6 New Library Box ----------------------------------------------------------------------------------------------------------- 8

Fig. 7 Attach Design Library ---------------------------------------------------------------------------------------------------- 9

Fig. 8 sige5am technology library selected --------------------------------------------------------------------------------- 9

Fig. 9 Add AMS Library Properties -------------------------------------------------------------------------------------------- 9

Fig. 10 Metal M5 Selection ----------------------------------------------------------------------------------------------------- 9

Fig. 11 Library Manager -------------------------------------------------------------------------------------------------------- 10

Fig. 12 Create New File --------------------------------------------------------------------------------------------------------- 10

Fig. 13 Schematic Editor Window ------------------------------------------------------------------------------------------- 11

Fig. 14 Add Instance ------------------------------------------------------------------------------------------------------------ 11

Fig. 15 Add Instance ------------------------------------------------------------------------------------------------------------ 12

Fig. 16 Add instance with NFET info ---------------------------------------------------------------------------------------- 12

Fig. 17Library browser - Add instance for PFET -------------------------------------------------------------------------- 13

Fig. 18 Add Instance for PFET [Important note- ------------------------------------------------------------------------- 13

Fig. 19 Add Instance for the SUBC ------------------------------------------------------------------------------------------- 14

Fig. 20 All the elements placed ---------------------------------------------------------------------------------------------- 14

Fig. 21 Add Pin Dialog Box ----------------------------------------------------------------------------------------------------- 15

Fig. 22 All the Pins and FETs are placed in the editor ------------------------------------------------------------------- 15

Fig. 23 Wires connected ------------------------------------------------------------------------------------------------------- 16

Fig. 24 Add Wire name --------------------------------------------------------------------------------------------------------- 16

Fig. 25 Completed Schematic of the inverter ----------------------------------------------------------------------------- 17

Fig. 26 No Errors in the Schematic ------------------------------------------------------------------------------------------ 17

Fig. 27 Add Pins ------------------------------------------------------------------------------------------------------------------ 18

Fig. 28 Add Symbol -------------------------------------------------------------------------------------------------------------- 18

Fig. 29 Add Selection Box ------------------------------------------------------------------------------------------------------ 18

Fig. 30 Inverter Symbol -------------------------------------------------------------------------------------------------------- 19

Fig. 31 Schematic of the inverter test circuit ----------------------------------------------------------------------------- 20

Fig. 32 Analog Design Environment window------------------------------------------------------------------------------ 20

Fig. 33 Choosing Analyses ----------------------------------------------------------------------------------------------------- 21

Fig. 34 Netlist and Run Successful ------------------------------------------------------------------------------------------- 21

Fig. 35 Plotting the output and inputs-------------------------------------------------------------------------------------- 22

Fig. 36 Output waveform ------------------------------------------------------------------------------------------------------ 22

Fig. 37 Output waveform with separate axes ---------------------------------------------------------------------------- 23

Fig. 38 Menu of Layout Creation--------------------------------------------------------------------------------------------- 23

Fig. 39 Create New Layout ---------------------------------------------------------------------------------------------------- 24

Fig. 40 Startup Option ---------------------------------------------------------------------------------------------------------- 24

Fig. 41 Create Instance --------------------------------------------------------------------------------------------------------- 24

Fig. 42 Adding PFET instance ------------------------------------------------------------------------------------------------- 25

Fig. 43 Specifying the PFET parameters similar to the schematic --------------------------------------------------- 25

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Fig. 44 PFET, NFET and SUB elements placed in the layout editor -------------------------------------------------- 26

Fig. 45 Modifying Display options ------------------------------------------------------------------------------------------- 26

Fig. 46 PFET, NFET and SUB elements in the layout editor after the display options configured properly 27

Fig. 47 Create symbolic pin --------------------------------------------------------------------------------------------------- 28

Fig. 48 Create Shape Pin ------------------------------------------------------------------------------------------------------- 28

Fig. 49 Connecting Input pin with the gates ------------------------------------------------------------------------------ 29

Fig. 50 Complete Layout before DRC --------------------------------------------------------------------------------------- 29

Fig. 51 DRC option --------------------------------------------------------------------------------------------------------------- 30

Fig. 52 Prompt for Line Mode & Orthogonal checking ----------------------------------------------------------------- 30

Fig. 53 DRC options ------------------------------------------------------------------------------------------------------------- 31

Fig. 54 Successful DRC Check ------------------------------------------------------------------------------------------------- 31

Fig. 55 Extractor Option form ------------------------------------------------------------------------------------------------ 32

Fig. 56 Message after Extraction--------------------------------------------------------------------------------------------- 32

Fig. 57 Library manager to check the extracted view------------------------------------------------------------------- 33

Fig. 58 Opening extracted view ---------------------------------------------------------------------------------------------- 33

Fig. 59 Extracted View ---------------------------------------------------------------------------------------------------------- 34

Fig. 60 LVS Artist ----------------------------------------------------------------------------------------------------------------- 34

Fig. 61 Prompt for LVS Artist -------------------------------------------------------------------------------------------------- 35

Fig. 62 Opening Analog Extracted ------------------------------------------------------------------------------------------- 35

Fig. 63 LVS succeeded message ---------------------------------------------------------------------------------------------- 36

Fig. 64 netlist matches with the schematic ------------------------------------------------------------------------------- 36

Fig. 65 Setting the switches before extraction --------------------------------------------------------------------------- 37

Fig. 66 Extractor with switches ----------------------------------------------------------------------------------------------- 37

Fig. 67 Build Analog ------------------------------------------------------------------------------------------------------------- 38

Fig. 68 Analog Extracted ------------------------------------------------------------------------------------------------------- 39

Fig. 69 Analog Environment for Extracted Simulation ------------------------------------------------------------------ 39

Fig. 70 Option to change the environment ------------------------------------------------------------------------------- 40

Fig. 71 Switch View list edited ------------------------------------------------------------------------------------------------ 40

Fig. 72 Setting up the analyses ----------------------------------------------------------------------------------------------- 41

Fig. 73 Waveform with and without Parasitics --------------------------------------------------------------------------- 41

Fig. 74 Waveform with Parasitics -------------------------------------------------------------------------------------------- 42

Fig. 75 Schematic of the NAND with W/L ratio (W/L)p = 27/1 and (W/L)n=20/1 -------------------------------- 43

Fig. 76 Symbol of NAND-------------------------------------------------------------------------------------------------------- 43

Fig. 77 Test Circuit NAND ------------------------------------------------------------------------------------------------------ 44

Fig. 78 Waveform with no parasitics --------------------------------------------------------------------------------------- 44

Fig. 79 NAND Gate Layout ----------------------------------------------------------------------------------------------------- 45

Fig. 80 DRC Check Confirmation --------------------------------------------------------------------------------------------- 45

Fig. 81 Network Extraction ---------------------------------------------------------------------------------------------------- 46

Fig. 82 Build Analog NAND ---------------------------------------------------------------------------------------------------- 46

Fig. 83 Simulation with Extracted Parameters --------------------------------------------------------------------------- 47

Fig. 84 Slight change in the delay due to parasitics --------------------------------------------------------------------- 47

Fig. 85 Schematic of the Ring inverter ------------------------------------------------------------------------------------- 48

Fig. 86 Waveform of the ring oscillator ----------------------------------------------------------------------------------- 48

Fig. 87 layout of the ring oscillator ------------------------------------------------------------------------------------------ 49

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Fig. 88 DRC of ring oscillator -------------------------------------------------------------------------------------------------- 49

Fig. 89 Extraction of the ring oscillator ------------------------------------------------------------------------------------- 50

Fig. 90 Extracted circuit in the library manager -------------------------------------------------------------------------- 50

Fig. 91 LVS successful ----------------------------------------------------------------------------------------------------------- 51

Fig. 92 Netlist match after LVS ----------------------------------------------------------------------------------------------- 51

Fig. 93 with wire parasitics waveform -------------------------------------------------------------------------------------- 52

Fig. 94 Ring oscillator with NAND ------------------------------------------------------------------------------------------- 53

Fig. 95 Layout of ring oscillator with NAND gate ------------------------------------------------------------------------ 53

Fig. 96 Waveform without parasitics --------------------------------------------------------------------------------------- 54

Fig. 97 with parasitics Ring oscillator with nand ------------------------------------------------------------------------- 54

Fig. 98 Schematic of 10X inverters ------------------------------------------------------------------------------------------ 55

Fig. 99 symbol -------------------------------------------------------------------------------------------------------------------- 55

Fig. 100 Schematic of the ring oscillator ----------------------------------------------------------------------------------- 56

Fig. 101 Waveform of the ring oscillator with 10x size ----------------------------------------------------------------- 56

Fig. 102 comparison with Normal ring oscillator top normal ring oscillator, bottom 10x ring oscillator -- 57

Fig. 103 Schematic of the inverter ------------------------------------------------------------------------------------------ 58

Fig. 104 symbol ------------------------------------------------------------------------------------------------------------------ 58

Fig. 105 schematic of the ring oscillator ----------------------------------------------------------------------------------- 59

Fig. 106 waveform without parasitics -------------------------------------------------------------------------------------- 59

Fig. 107 layout of the ring oscillator with fingers ------------------------------------------------------------------------ 59

Fig. 108 waveform with parasitics (First one with no parasitics, second one with parasitics) --------------- 59

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Introduction

This document is a tutorial write up for the course Introduction to VLSI Design. In the tutorial we were

taught how to use Cadence for designing VLSI circuits and create layout of the circuits for fabrication.

Logging into remote server

The process of logging into the remote server is as follows –

1. Pressed Start Button.

2. Wrote Remote Desktop Connection in the Search Programs and Files Text box.

3. The Remote Desktop Connection box appeared [Fig. 1]

4. At the Computer Text box the address of the server was entered. For this tutorial the name of

the server used was “ts1.ecse.rpi.edu”. The condition of the Dialog box after entering the

address is shown in Fig. 2.

Fig. 1 Remote Desktop Connection Dialog Box

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5. Next, the connect Button was pressed. The login window appeared. [Fig. 3]

6. After inserting the username and password provided previously and pressing OK the Desktop of

the Server PC will appear.

Fig. 2 Remote Desktop Connection Dialog box after inserting the Server Address

Fig. 3 Server Login Window

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Changing License Information For the first time use only, we needed to change the license information in the server’s .bashrc file. For

this we needed to follow these steps.

1. Opening the Terminal window from Applications -> Accessories -> Terminal.

2. In the terminal window we typed the following command gedit .bashrc.

3. After that the .bashrc file opened.

4. In that File we had to change the line export CDS_LIC_FILE=5279@licsrvrdg.arc.rpi.edu to

export CDS_LIC_FILE=5279@licsrvrdg2.arc.rpi.edu

5. Then we had to save the .bashrc file by clicking the save button.

6. After that we had to close the .bashrc file and the Terminal window as well. [Fig. 4]

Fig. 4 Changing the License Information

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Starting Cadence Environment

For starting the Cadence interface we had to type icfb& in the terminal window. The ‘&’ sign after the

command ensures that the Cadence process will run in parallel and will not block the terminal. This

enables the user to use the same terminal window to use if needed. The image of the CIW window is

given in Fig.5.

Creating New Library

1. Clicked IBM_PDK – Library – Create. The Following New Library Dialog Box appeared. [Fig 6] In

the Dialog Box the appropriate Library Name is provided. Also the Option Attach to an existing

techfile option is checked. After that OK button is pressed.

Fig. 5 CIW Window

Fig. 6 New Library Box

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2. When OK is pressed the Attach Design Library to Technology File box appears. [Fig. 7]

3. For the Technology Library, Sige5AM is selected. [Fig. 8] After that OK button is pressed.

4. The Add AMS Library Property box appears. [Fig. 9]

5. In the Number of levels of metal M5 is selected. [Fig. 10] Then OK Button is pressed.

Fig. 7 Attach Design Library

Fig. 8 sige5am technology library selected

Fig. 9 Add AMS Library Properties

Fig. 10 Metal M5 Selection

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After that the Library is created. It can be viewed from Tools- Library Manager. [Fig. 11]

Creating the Schematic of the Inverter

1. Create a new Schematic file by clicking File -> New -> cellview. The Create New file box appears.

[Fig 12]

Fig. 11 Library Manager

Fig. 12 Create New File

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2. After inserting the Cell name, view name and selecting Composer-Schematic Tool dropdown list,

the new Schematic window appears. [Fig. 13]

3. Now we need to add all the circuit elements in the editor. At first we need to go to Edit -> Add

Instance (or i) to insert the elements. The Add instance box appears. [Fig. 14]

4. When the Browse button is pressed, the Library Browser – Add Instance Box appears. [Fig. 15]

Like the Fig. 15 we can select sige5am as the Library, FET as the Category, nfet as the cell and

symbol as the view. After that the Add Instance box changes like the [Fig. 16]. Here we need to

change the width of the NFET to 10 uM. [Fig. 16]

Fig. 13 Schematic Editor Window

Fig. 14 Add Instance

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Fig. 15 Add Instance

Fig. 16 Add instance with NFET info

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Fig. 17Library browser - Add instance for PFET

Fig. 18 Add Instance for PFET [Important note- 1. The Add nw contact & dt to pcell should

be checked 2. The width should be 27 uM]

5. After that we can place the NFET in the Schematic editor. The same process is applied for the

PFET and SUBC elements. [Fig. 17, 18, 19, 20]

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Fig. 20 All the elements placed

6. Now we need to add the input and output pins and wire the elements. For adding Pin we need

to click on Add -> Pin and to add wire we need to click on Add -> wire (narrow). [Fig. 21,22,23]

Fig. 19 Add Instance for the SUBC

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Fig. 22 All the Pins and FETs are placed in the editor

Fig. 21 Add Pin Dialog Box

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Fig. 23 Wires connected

Fig. 24 Add Wire name

7. After connecting all the wires we need to name the wires by pressing Add -> Wire name. [Fig.

24, 25]

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Fig. 25 Completed Schematic of the inverter

Fig. 26 No Errors in the Schematic

8. When this is done, we need to press Design -> Check and save to save the schematic. [Fig. 26]

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Fig. 27 Add Pins

Fig. 28 Add Symbol

Fig. 29 Add Selection Box

Creating the Symbol

1. The symbol file could be created from CIW’s File -> New -> Cell View.

2. Clicking the Add –> shape –> line option we need to draw the triangle of the inverter.

3. Then from Add –> shape –> circle option we need to draw the circle in front of the inverter.

4. Next we need to add the input and output pins and connect those using lines. [Fig. 27]

5. After that we can add the label of the instance from Add –> label option. [Fig. 28]

6. We can then add selection box from Add – Selection Box. [Fig. 29]

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Fig. 30 Inverter Symbol

7. When the symbol is finished, it should look like the following figure. [Fig. 30]

Testing the inverter

1. The circuit which was built for the inverter testing is given in the [Fig. 31]

2. To go the simulation environment we need to go to Tools –> Analog Environment. Window in

Fig. 32 appears.

3. After choosing the appropriate set up in the analog environment we press netlist and run icon.

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Fig. 31 Schematic of the inverter test circuit

Fig. 32 Analog Design Environment window

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Fig. 33 Choosing Analyses

Fig. 34 Netlist and Run Successful

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Fig. 35 Plotting the output and inputs

Fig. 36 Output waveform

4. After the net list and run step is successful, we select Output -> Direct Plot -> Transient Signal

from the menu and then select the desired nodes from the schematic and press ESC. Following

that step we can get the waveform of the Inverter circuit.

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Fig. 37 Output waveform with separate axes

Fig. 38 Menu of Layout Creation

Drawing the layout

Creating Layout XL file

1. In the Schematic Editor of the Inverter If we click Tools -> Design Synthesis -> Layout XL, the

following form appears. [Fig. 39]

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Fig. 39 Create New Layout

Fig. 40 Startup Option

Fig. 41 Create Instance

2. When the OK button is clicked in the Create New File box, the Startup option form appears. For

creating a new Layout the Create new check box should be selected. After that OK is pressed. [Fig.

40]

Placing the Elements

1. In the layout editor we need to input instances of PFET, NFET and SUB similar to the Schematic of

the Inverter. The Add instance window is similar to that in the Schematic. [Fig. 41]

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Fig. 42 Adding PFET instance

Fig. 43 Specifying the PFET parameters similar to the schematic

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Fig. 44 PFET, NFET and SUB elements placed in the layout editor

Fig. 45 Modifying Display options

2. To make all the layers visible we need to click options -> Display and press default in the Display

options window and press ok. [Fig. 45]

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Fig. 46 PFET, NFET and SUB elements in the layout editor after the display options configured properly

3. Doing the previous step should make the layout like the following figure [Fig. 46].

Routing

After placing all the elements, we need to set up the pins and wires of the circuit. At first we need to

set up the pins. In the schematic there are four pins. Among them only the input pin is in the

polysilicon (pc) layer and the vdd, gnd and output are in the m1 (metal 1) layer. At first we need to

create the input pin. For that we have to select pc- pin in the LSW window. After that we have to click

Create -> Pin menu. A box will appear [Fig. 47]. In that box we need to select shape pin. After doing

that, another box will appear called the create shape pin [Fig. 48]. In that box we need to specifiy the

terminal names, check display pin name options, I/O type and draw the pin in the layout editor. We

need to follow the process for output, gnd and vdd as well. After all the pins are placed, we need to

connect them with wires. For connecting the input pin with the gates of both the FETs, we again need

to select pc – drw from the LSW window, then select Create -> Path from the menu. Then if we click

on one end of the gate and draw the pointer to the other FET’s gate we will get a path. We need to

use Create -> Rectangle to create the metal wires.

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Fig. 47 Create symbolic pin

Fig. 48 Create Shape Pin

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Fig. 49 Connecting Input pin with the gates

Fig. 50 Complete Layout before DRC

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Fig. 51 DRC option

Fig. 52 Prompt for Line Mode & Orthogonal checking

DRC

1. For checking the DRC (Design Rule Checking) we need to press IBM_PDK -> Checking -> DRC

[Fig. 51]. Sometimes the IBM_PDK options is not present. To recover this options we need to

close the layout editor and reopen it.

2. There is a Do you wish to run line Mode & Orthogonal Checking box, we need to press yes [Fig.

52], then there is DRC window, we also need OK press ok there. [Fig. 53]

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Fig. 53 DRC options

Fig. 54 Successful DRC Check

3. If there is no error in the schematic, we will get the following message in the CIW window. [Fig.

54]

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Fig. 55 Extractor Option form

Fig. 56 Message after Extraction

LVS (Layout Validated to Schematic)

1. Before we can do LVS, we need to extract the schematic from the layout that we have just

designed. For that we need to press IBM_PDK -> Checking -> Extract. We will get the following

window after that. [Fig. 55]

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Fig. 57 Library manager to check the extracted view

Fig. 58 Opening extracted view

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Fig. 59 Extracted View

Fig. 60 LVS Artist

2. After that we can do LVS. For that, we need to press Verify -> LVS. The LVS Artist window

appears. [Fig. 60]

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Fig. 61 Prompt for LVS Artist

Fig. 62 Opening Analog Extracted

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Fig. 63 LVS succeeded message

Fig. 64 netlist matches with the schematic

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Fig. 66 Extractor with switches

Network Extraction to Obtain wire Parasitics

The network Extraction is similar to the previously discussed LVS checking. We just need to select the

Parasitics (Raphael Cap and Rparasitics) from Extractor windows set switches button. [Fig. 64, 65]. Later

in the ARTIST LVS we need to run for successful LVS and then press Build Analog to make the

analog_extracted circuit for wire Parasitics data.

Fig. 65 Setting the switches before extraction

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Fig. 67 Build Analog

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Fig. 68 Analog Extracted

Fig. 69 Analog Environment for Extracted Simulation

Extracted Simulation with wire Parasitics for Speed comparison

This process is similar to the simulation of the Inverter Test circuit. But here we have to press setup ->

Environment [Fig. 69] in the Analog Environment form and need to change switch view list according to

[Fig. 71]

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Fig. 70 Option to change the environment

Fig. 71 Switch View list edited

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Fig. 72 Setting up the analyses

Fig. 73 Waveform with and without Parasitics

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Fig. 74 Waveform with Parasitics

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Fig. 75 Schematic of the NAND with W/L ratio (W/L)p = 27/1 and (W/L)n=20/1

Fig. 76 Symbol of NAND

2 input NAND

Schematic of Circuit

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Fig. 77 Test Circuit NAND

Fig. 78 Waveform with no parasitics

Simulation Waveform (No parasitics)

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Fig. 79 NAND Gate Layout

Fig. 80 DRC Check Confirmation

Layout

Design Rule Check

46

Fig. 81 Network Extraction

Fig. 82 Build Analog NAND

Network extraction to obtain Parasitics

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Fig. 83 Simulation with Extracted Parameters

Fig. 84 Slight change in the delay due to parasitics

Extracted simulation with wire parasitics

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Fig. 85 Schematic of the Ring inverter

Fig. 86 Waveform of the ring oscillator

Ring Oscillator (Inverter)

Schematic

Waveform

49

Fig. 87 layout of the ring oscillator

Fig. 88 DRC of ring oscillator

Layout

DRC

50

Fig. 89 Extraction of the ring oscillator

Fig. 90 Extracted circuit in the library manager

Parasitics Extraction and LVS

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Fig. 91 LVS successful

Fig. 92 Netlist match after LVS

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Fig. 93 with wire parasitics waveform

Extracted Simulation with wire parasitics

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Fig. 94 Ring oscillator with NAND

Fig. 95 Layout of ring oscillator with NAND gate

Ring Oscillator (NAND)

Schematic

Layout

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Fig. 96 Waveform without parasitics

Fig. 97 with parasitics Ring oscillator with nand

Waveform without Parasitics

Waveform with parasitics

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Fig. 98 Schematic of 10X inverters

Fig. 99 symbol

Ring Oscillator (10X Inverters)

Schematic of 10X large inverters

Symbol of the inverter

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Fig. 100 Schematic of the ring oscillator

Fig. 101 Waveform of the ring oscillator with 10x size

Schematic of the ring oscillator

Waveform

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Fig. 102 comparison with Normal ring oscillator top normal ring oscillator, bottom 10x ring oscillator

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Fig. 103 Schematic of the inverter

Fig. 104 symbol

Ring Oscillator (10X Inverters with multiple fingers)

Schematic of 10X large inverters with multiple fingers

Symbol of the inverter

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Fig. 105 schematic of the ring oscillator

Schematic of the ring oscillator

Waveform

Fig. 106 waveform without parasitics

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Fig. 107 layout of the ring oscillator with fingers

Fig. 108 waveform with parasitics (First one with no parasitics, second one with parasitics)

Layout

Waveform with parasitics