Adding value to design and test through education: What are the challenges?

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  • Panel Summaries

    THE 6TH IEEE Latin American Test Workshop(LATW 05), took place from 30 March to 2 April 2005in Salvador, Brazil. The workshop included a panel dis-cussion on the challenges for modern design and testeducation, which attracted much attention from theaudience.

    I organized the panel discussion, and Magdy Abadirof Freescale Semiconductor served as moderator.Participants included Jos Luis Huertas (Centro Nacionalde Microelectrnica, Spain), Yervant Zorian (VirageLogic), Fernando Silveira (Universidad de la Repblica,Uruguay), Cesar Dueas (BSTC-Freescale, Brazil), andPascal Nouet (LIRMMLaboratory of Data Processing,Robotics, and Microelectronics in Montpellier, France).

    Cesar Dueas commented that there is a large gapbetween the research taking place in universities and theactual needs of industry. Both sides are responsible:Industry people tend to require short-term results, and uni-versity peopletrying to be as creative as possibletendto pursue ideas that are not always useful. The solution forthis dilemma would pass through professors because theyare the ones that can actually fill the gap between com-panies and students. One possible strategy is to open upinternship positions in companies. Professors could thenwork at a company for a certain period, and when theyreturn to their university, they would bring with them a fla-vor of the current industry needs.

    Pascal Nouet brought up the challenge that newdevices and designs pose to both professors and stu-dents: Todays designs demand mastery of an increas-ing number of disciplines in addition to the traditionaldisciplines such as fundamental mathematics, physics,and circuits. Moreover, the increasing complexity ofdesigns requires engineers to be knowledgeable inmany different abstraction levels, ranging from basic cir-

    cuit equations to software engineering. Commenting onthe gap between universities and industry, Nouet notedthe successful LIRMM experience in which companiesdonated a state-of-the-art tester to the laboratory; inexchange, LIRMM provided training for all companieswishing to use the tester. This exchange exposed stu-dents to highly complex equipment at reasonable costsand brought companies inside the university.

    Fernando Silveira commented that specifically inLatin America there is a lack of industries wishing toinvest money in research. This causes a cycle in whichfewer students follow engineering careers in the design-and-test field, resulting in less research in the field.

    Jos Luis Huertas mentioned that the widening gapbetween industry and universities in the areas of designand test can only decrease if professors take a bold steptoward developing new technologies. Hence, joint uni-versity-company researcheven with start-up compa-niesis the way to go.

    Yervant Zorian stressed that the way to be successfulin the design-and-test field is to develop expertise in thefield. This idea is certainly not confined to just this field.Education should have a broader sense, and should bestrong in the fundamentals that will be necessary for therest of an electronic engineers life. Another importantaspect is that universities tend to train people to workalone, since that is the evaluation method that universi-ties currently use. In a company, on the other hand,teamwork is what matters; hence, universities shouldinclude collaborative work in their curricula.

    Magdy Abadir proposed the discussion of start-upsas a means to develop new insights and develop a pathto bring technology to developing countries.

    The panel concluded that funding is fundamental

    Adding value to design and test througheducation: What are the challenges?Luigi CarroFederal University of Rio Grande do Sul

    388 0740-7475/05/$20.00 2005 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers

    continued on p. 390

  • 390 IEEE Design & Test of Computers

    Conference Reports

    transient errors in memory arrays.The workshop had 17 paper presentations in six ses-

    sions with ample general discussion time after each ses-sion. It started with an industrial perspectives session,followed by a session on logic-soft-error modeling andanalysis techniques to understand system behaviors inthe presence of soft errors. Next, three design sessionspresented circuit-, logic-, and system-level design tech-niques for soft-error mitigation. Organizers plan the pub-lication of a position paper as an outcome of thisworkshop.

    One key outcome was the observation that logic softerrors will be a major concern in sub-65-nm technolo-gies. Although partially depleted silicon-on-insulator(SOI) processes can provide a five-fold soft-error ratereduction, SOI alone cannot eliminate the risk. Anotheroutcome of the workshop was that participants identi-fied the need for automated tools to better predict sys-tem-level derating of logic soft errors.

    SELSE-1 was sponsored by the Coordinated ScienceLaboratory of the University of Illinois at Urbana-Champaign, the IEEE Computer Societys TestTechnology Technical Council, Advanced MicroDevices Inc., Hewlett-Packard, IBM, Intel, and iRoCTechnologies. Generous sponsorship from the five com-panies allowed a reduced registration fee of $25 for stu-

    dents. The 70 registrants came from a broad range ofindustry and academic institutions, including theCalifornia Institute of Technology; NortheasternUniversity; University of California, Davis; University ofIllinois at Urbana-Champaign; University of Michigan;University of New South Wales, Australia; The Universityof Texas at Austin; Advanced Micro Devices; CypressSemiconductor; Hewlett-Packard; iRoC Technologies;IBM; Intel; Medtronic Inc.; and Texas Instruments.

    SELSE-2 will take place in 2006, and the SELSE com-mittee will begin accepting submissions for SELSE-2 inthe fall of 2005. For more information, access the SELSEWeb site at Pleasedirect questions about SELSE-2 to the SELSE-1 cochairs,Subhasish Mitra ( and PiaSanda (, program chair WendyBartlett (, TTTC contactYervant Zorian (, orlocal-arrangements chair Sanjay Patel ( The SELSE organizing committee thanks the TTTCfor encouraging and sponsoring this workshop.

    CONTRIBUTIONS TO CONFERENCE REPORTS:Send conference reports to Yervant Zorian, VirageLogic, 47100 Bayside Parkway, Fremont, CA 94538;

    because university laboratories must resemble the actu-al environment in which students will work when theybegin their careers. Beside that crucial input, constantdiscussion among professors and company representa-tives in conferences and workshops is a great way tobridge the gap between education and present-daychallenges in design and test.

    The next panel discussion will take place at LATW2006 in Buenos Aires, from 26 to 29 March 2006. Formore information, please see

    CONTRIBUTIONS TO PANEL SUMMARIES: Sendpanel summaries to Yervant Zorian, Virage Logic,47100 Bayside Parkway, Fremont, CA 94538;

    continued from p. 388

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