a three-stage 60ghz cmos lna using dual noise-matching ... · 2008/12/18 ning li, tokyo tech 5...

2008/12/18Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.

A Three-Stage 60GHz CMOS LNA Using Dual Noise-Matching

Technique for 5dB NF

Ning Li1, Kenichi Okada1, Toshihide Suzuki2, Tatsuya Hirose2 and Akira Matsuzawa1

1. Tokyo Institute of Technology, Japan2. Advanced Devices Lab, Fujitsu Laboratories Ltd, Japan

2008/12/18 Ning Li, Tokyo Tech

1

Matsuzawa& Okada Lab.Matsuzawa& Okada Lab.

Outline

Background

60GHz LNA Design Method

Circuit and Simulation Results

Conclusions


2


Background• 7 GHz unlicensed band

at 60 GHz• Gbps data transfer

• Short range• Good isolation

Reference:1. http://windowsil.org/2008/03/13/60-ghz-wireless-communications/ 2. http://www.dailywireless.org/2006/11/13/more-70ghz-radios/

60GHz


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Applications

Ref: http://domino.research.ibm.com/comm/research_projects.nsf/pages/mmwave.apps.html

WPANWireless HDMIPoint to Point links Receiver Architecture


4


Outline

Background



Conclusions


5


Issues…When up to mm-wave CMOS LNA…

Lower gain

MAG is inversely proportional to the logarithm of the operating frequency fc.

Higher noise

NFmin is proportional to the operating frequency fc.

High frequency

100 101 1020

5

10

15

20

25

MA

G [d

B]

Frequency [GHz]100 101 102

2

4

NF

[dB

]

Wf=2.5μm, Nf=32, Vgs=0.8V and Vds=0.8V.

log-log scale

semi-log scale

MSG

/MA

G [d

B]

)(2.11min sgmT

c RRGNF +⎟⎟⎠

⎞⎜⎜⎝

⎛+=

ωω)lg(20

c

MAXMAGG

ωω

≈


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Cascode Topology Noise

M1

M2

Vdd

RFin

M2

M１Cx

IoutZin

Stage 1 Stage 2

CS+CG Small signal equivalent circuit Cascode

⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛+= 2

2

2

2

2

0221, 0

2

04 ωωω

γm

x

gC

gRFFT

dscascodetot

1

1

gs

mT C

g=ω

122 dbsbgsx CCCC ++=( )

⎟⎟⎠

⎞⎜⎜⎝

⎛+=

++= 2

20

01

211

1 14

1T

sds

gsg RgkTR

VRIF

ωωγ

High noise contribution of M2 due to the large inter-stage node capacitance.

Reference:Hirad Samavati, et al., IEEE JSSC, VOL. 35, NO. 5, MAY 2000


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CS-CS Noise

M1 M2

Vdd1 Vdd2

RFin

Proposed schematic Noise CirclesAvailable Gain CirclesSource Stability Circle

Common source topology has a smaller NF.Using source degeneration to adjust the value of the input impedance.

Reference:D.K. Shaeffer, et al., IEEE JSSC, VOL. 32, NO. 5, MAY 1997.


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Outline

Background



Conclusions


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Transistor Model at 60 GHz

Based on BSIM4 model

Large signal

Scalable

Back-gate model

Measurement condition:Wf=2.5μm, Nf=32, Vgs=0.8V and Vds=0.8V.


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Slow-wave Transmission Line

10µm

13µm

Metal 1

Top Metal

0.457dB/mm at 60GHz

Small area!L Constant

LargerC LCωβ ≈Phase Constant:


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Proposed LNA Circuit

Multi-stageHigher gain

Dual noise-matching topologyLower noise

1.080

1.040

1.040

1.040


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Stability

0 20 40 60 80 100100

102

104

Frequency [GHz]

K

Common source is much more sensitive to process variations arising from the bilateral nature of the device.

Input matching

Careful layout

Circuit is unconditionally stable from DC to 100GHz.


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For Comparing…

Vb1 Vb2

CC1

Vdd1

Cout

RFin

RFout

Cin

Vdd2

Pad Pad

Vdd3

Vb3

CC2

1.080

1.040

1.040

1.080

1.040

1.080

115μ

20μ

140μ

50μ0μ

20μ 20μ

20μ 20μ 80μ

90μ

115μ

20μ

140μ

50μ20μ

140μ

50μ

50μ50μ 50μ

0μ 0μ

70μ

The same stage used

Cascode topology


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Simulation Results – S11, S22

S11,

S22

[dB

]

S11,

S22

[dB

]

Proposed Conventional7GHz bandwidth in Japan

59GHz~66GHzS11S22

Proposed Conventional

<-5.7dB<-13.3dB

<-5.1dB<-11.4dB


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Simulation Results – Power Gain

ConventionalProposedGain 15dB 16dB


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Simulation Results -- NF

ConventionalProposedNF 5dB 6.4dB


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Performance Comparison

Simulation MeasurementProposed Conv. [1] [2] [3] [4] [5]

Technology 90nm CMOS

90nm CMOS

90nm CMOSCS154.43.9

90nm CMOS

90nm CMOS

90nm CMOS

65nm CMOS

Topology dual-CS cascode cascode cascode CS cascodeGain [dB] 15 16 14.6 15.5 12.2 22.3 (diff.)NF [dB] 5.0 6.4 5.5 (sim) 6.5 6 (sim) 6.1Power [mW] 22 19 24 86 10.5 35

Reference:[1] Emanuel Cohen, et al., RFIC, pp. 61-64, 2008. [2] Terry Yao, et al., IEEE JSCC, vol. 42, no. 5, pp. 1044-1057, 2007. [3] Stefano Pellerano, et al., ESSCIRC, pp. 352-355, 2007. [4] Babak Heydari, et al., IEEE JSCC, vol. 42, no. 12, pp. 2893-2903, 2007. [5] Christopher Weyers, et al., ISSCC, pp. 192-192, 2008.


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Outline

Background



Conclusions


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Conclusions

A three-stage LNA employing a dual noise-matching topology

Noise matching optimized by using source degeneration

A 5dB NF realized by dual noise matching technique

Comparing with the conventional1.4dB NF improvement

1dB gain decrease

3mW power consumption increase


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Finally…

Thank you !

a three-stage 60ghz cmos lna using dual noise-matching ... · 2008/12/18 ning li, tokyo tech 5...

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