a 0.55 v 7-bit 160 ms/s interpolated pipeline adc …a 0.55 v 7-bit 160 ms/s interpolated pipeline...
TRANSCRIPT
James Lin, Daehwa Paik, Seungjong Lee, Masaya Miyahara, and Akira Matsuzawa
Tokyo Institute of Technology, Japan
A 0.55 V 7-bit 160 MS/s Interpolated Pipeline ADC Using Dynamic Amplifiers
Matsuzawa
& Okada LabMatsuzawa Lab.Tokyo Institute of Technology
2
Outline
• Motivation
• Prior Arts
• Circuit Design
• Measurement Results
• Conclusion
3
Motivation
• Ultra-low-voltage (ULV) operation
– Immediate power saving potential
– Explore new circuit techniques for future technology [1]
[1] ITRS, 2011. 2010 2015 2020 2025
0.5
0.6
0.7
0.8
0.9
1.0
Su
pp
ly v
olt
ag
e (
V)
Year
Key Challenges
• Reduced SNR
• Reduced headroom
• Reduced gain
• Increased mismatch
4
Outline
• Motivation
• Prior Arts
• Circuit Design
• Measurement Results
• Conclusion
Prior Arts
• Successfully demonstrated very good
energy efficiency but all suffer in speed
5 [2] S. Chatterjee et al., JSSC 2005.
[4] A. Shikata et al., JSSC 2012.
Body-Driven [2] Sub-threshold [3] SAR-based [4],[5]
[3] D. C. Daly et al., JSSC 2009.
[5] P. Harpe et al., ISSCC 2013.
Vin
CDAC
SAR LogicVbiasn
Vin
Vin
CLK
6
Outline
• Motivation
• Prior Arts
• Circuit Design
• Measurement Results
• Conclusion
Circuit Techniques Overview
• ADC architecture
• Dynamic amplifier
• Interpolation technique
• Sub-ADC structure
• Self-clocking scheme
7
Dynamic Amplifier
• Minimally stacked amplifier achieves high
speed at low supply voltage [6]
8 [6] J. Lin, et al., ISCAS 2011.
Pd = fCVDD2
Pre-charge
Phase
Amplification
Phase
Time
Vo
lta
ge
Voutp
VoutnCLK
Voc
Vo
ut
Vo
ut
CMD: Common-mode voltage detector
CLK
Vinp Vinn
CMDVoutp Voutn
CLK
ADC Block Diagram
• Ultra-low-voltage interpolated pipeline ADC
9
Vin
Vref
Sample
& CDAC
CMP1
Sample
& CDAC
IntCaps
Correction Logic
7b
D1st
(3b)
D2nd
(2b+1b)
D3rd
(2b)
IntCaps
CMP2
A1a A2a
A2b
CMP3
PS-RDACSTAGE1 STAGE2 STAGE3
A1b
Dynamic Amplifiers
Interpolation Technique
• Interpolation shifts the gain requirement:
absolute relative gain accuracy [7], [8]
10 [7] A. Matsuzawa, et al., ISSCC 1990. [8] C. Mangelsdorf, et al., ISSCC 1993.
Different absolute gain, same decision levels!
Vout
Vin
Voa
Vob
V oa:V
ob =
3:1
V oa:V
ob =
1:1
V oa:V
ob =
1:3
Vout
Vin
Voa
Vob
Interpolated Pipeline
• Same path for both signal and references
11
01 11 01Vrefn
Vrefp
Conventional
Vin
01 11 01Vrefn
Vrefp
Interpolation
Vin4X
4XAny Gain
Fixed references Embedded references
High-Speed Dynamic Amplifier
• Dynamic amplifier with an inverter-based
CMD for high-speed operation
12
Gain = a(VDD-Voc)/Veff , 1<a<2
Vout
Vinp Vinn
CLKCLK
IntCaps IntCaps
Inverter-based
CMDfrom
PS-RDACfrom
PS-RDAC
Vxn Vxp
Pseudo-Static RDAC
• Pseudo-static RDAC is proposed to calibrate
the common-mode voltage during startup
13
VRDAC
VCOM
Voc
VRDAC
CMP +
Counter
IntCaps
IntCaps
Voc=
(Voa+Vob)/2N
ex
t S
tag
ePS-RDAC
A1a
A1bTime
Target
(Vcom)Voa
Vob
AMP
V
Vxa
Vxb
CMP Interpolate
Capacitive Interpolation [9]
• Absolute gain relative gain accuracy
• Interpolation is controlled by the sub-ADC
14 [9] M. Miyahara, et al., VLSI Circuits 2011.
A1a
A1b
A1a
A1b
Sampling Phase Interpolation Phase
to A2a
to A2b
Vxa
Vxb
from PS-RDAC from PS-RDAC
to A2a
to A2b
Via
Vib
Via
Vib
Vxa
Vxb
Sub-ADC
• Gate-weighted interpolation comparators
with a time-based offset calibration
15
[10] Y. Asada, et al., A-SSCC 2009.
[11] M. Miyahara, et al. A-SSCC 2010.
Dynamic Comparator
A1a
A1b
3-bit sub-ADC
Gate-weighted interpolation
Vinpa Vinnb
VDD VDD
CLKP CLKN
VDD VDD
Vinpb Vinna
- +Dout
Wa Wb Wa Wb
Timing
cal.
CLK
Generated CLK2 AMP CMP Hold Reset
AMP1
AMP1's Trigger
CMP2's Trigger
Output of STAGE2
AMP2
CMP2
AMP2's Trigger
Start
CMP2
Start
AMP2
Time Start CMP3
1
2
3
Generated CLK3 Reset
STAGE3
Start
CMP2
Reset
STAGE3
Self-Clocking
• Internal signals trigger the subsequent stages
to maximize speed performance [12], [13]
16 [12] J. Yang, et al., JSSC 2010. [13] R. Kapusta, et al., ISSCC 2013.
17
Outline
• Motivation
• Prior Arts
• Circuit Design
• Measurement Results
• Conclusion
Measured DNL and INL
• Startup calibration: timing cal. + common-mode cal.
18
0 32 64 96 128-4-3-2-101234
DN
L (
LS
B)
0 32 64 96 128-4-3-2-101234
0 32 64 96 128-4-3-2-101234
0 32 64 96 128-4-3-2-101234
INL
(L
SB
)
0 32 64 96 128-4-3-2-101234
0 32 64 96 128-4-3-2-101234
+3.8 / -1 LSB +1.7/ -0.86 LSB +0.77 / -0.47 LSB
+3.4 / -3.1 LSB
+1.5 / -0.91 LSB +0.74 / -0.66 LSB
Digital code
Uncalibrated Timing Cal. Vcm Cal.
Measured SFDR and SNDR
• >38 dB of SNDR is measured up to 160 MS/s with
an ERBW >80 MHz
• Consumes 2.43 mW at 160 MS/s, FoM=240 fJ/c.-s.
19
SFDR & SNDR vs. fs SFDR & SNDR vs. fin
0 50 100 150 200
20
30
40
50
60
SF
DR
an
d S
ND
R (
dB
)
Conversion rate (MS/s)
fin = 1 MHz
SFDR
SNDR
0 20 40 60 80
20
30
40
50
60
SF
DR
an
d S
ND
R (
dB
)
Input frequency (MHz)
fs = 160 MS/s
SFDR
SNDR
Clock-Scalable Power Performance
• Dynamic amplifier enables clock-
scalability in ADC’s power performance
20
0 50 100 150 2000.0
0.5
1.0
1.5
2.0
2.5
3.0
Po
we
r c
on
su
mp
tio
n (
mW
)
Conversion rate (MS/s)
Chip Photo
• Prototype ADC is fabricated in 90 nm CMOS
with the low threshold and deep N-well options
• Occupied area is 0.25 mm2
21
ST
AG
E1
ST
AG
E2
ST
AG
E3
DEC
760 mm
32
0 m
m
Performance Comparison
• Fastest ULV ADC compared to other state-
of-the-art ULV high-speed ADCs
22
[14] [15] [16] [17] This work
Architecture Flash Pipeline Pipeline Pipeline Pipeline
Resolution (bit) 5 8 10 12 7
Supply voltage (V) 0.6 0.5 0.5 0.6 0.55/0.5*
fs (MS/s) 60 10 10 10 160
Power (mW) 1.3 2.4 3.0 0.56 2.43
ENOB (bit) 4.01 7.7 8.5 10.8 6.0
FoM (fJ/c.-s.) 1060 1150 825 30.9 240
Technology (nm) 90 90 130 65 90
Active area (mm2) 0.11 1.44 0.98 0.36 0.25
[14] J. E. Proesel, et al., CICC 2008.
[16] Y. J. Kim, et al., CICC 2007.
[15] J. Shen, et al., JSSC 2008.
[17] S. Lee, et al., JSSC 2012.
*Analog VDD = 0.55 V, Digital VDD = 0.5 V
Summary of ULV Pipeline ADC
• Proposed ADC demonstrates the feasibility
of ULV high-speed analog circuit design
23
20 30 40 50 60 70 800.01
0.1
1
10
100
1000
VDD
=0.6 V
VDD
=0.55 V
VDD
=0.5 V
VDD
=0.4 V
Co
nv
ers
ion
ra
te (
MS
/s)
SNDR (dB)
This work
JSSC 2009 [3]
CICC 2008 [14]
JSSC
2012 [17]
CICC
2007 [16]
JSSC 2008 [15]
JSSC 2012 [4]A-SSCC
2006
ISSCC 2013 [5] JSSC
2007
24
Outline
• Motivation
• Prior Arts
• Circuit Design
• Measurement Results
• Conclusion
Conclusion
• 0.55 V, 7-bit, 160 MS/s, 2.43 mW pipeline
ADC is realized using dynamic amplifiers
and interpolation
• Demonstrates the feasibility of ultra-low-
voltage high-speed analog circuit design
• Proposed techniques are suitable for ULV
and nominal-voltage high-speed circuits
25
Acknowledgement
26
This work was partially supported by NEDO,
Huawei, Berkeley Design Automation for the use
of the Analog FastSPICE (AFS) Platform, and
VDEC in collaboration with Cadence Design
Systems, Inc.
