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64 POINT FFT/ifft Processor for Ieee 802.11(a)

standard

Presented by: SHALY JOSE ECE VJCET 2011-2015

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INTRODUCTION

Discrete Fourier Transform

Fast Fourier Transform: Algorithm to compute DFT using reduced no of calculations.

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Applications of FFT

Used in signal processing applications,such as:

OFDM:Orthogonal Frequency Division Multiplexing;A method encoding digital data on multiple carrier

frequencies.Software defined radio:SDR:Radio communication components implemented by

means of software on a personal computer or embedded system.

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64 pt FFT PROCESSOR—turbo 64 Developed for IEEE 802.11(a) standard. Core area:6.8 sq. mm Average power consumption: 41 mW at 1.8 V @ 20 MHz

frequency

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5Why TURBO64 at 20 MHz?

IEEE 802.11(a) standard

4microsec

Cooley-Turkey Algorithm

192 complex butterfly

operations for a 64 point FFT

1 butterfly operation

• 20.8 ns

48 MHz frequency

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THEORETICAL BACKGROUND

• FFT, A(r)=………………………….1

Where B(k)-complex data sequenceN-length of the sequence------

• Consider:N=MT,r=s+Tt ,k=l+Mm

s,l k,m

Applying these values in above equation:

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A(s+Tt)=[]………….2

• Eqn (2) FFT decomposed into M point and T point FFTAnd combined for final result.

• Considering M=8 and T=8: the 64 point FFT can be expressed as:

A(s+Tt)=[]………3

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Signal Flow graph of a 8 point DFT

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IFFT

Swap real and

imaginary terms

Forward FFT

Again swap the real

and imaginary

terms.

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ARCHITECTURE OF TURBO64

Input unit

1st 8 pt FFT unit

Multiplier unit CB unit 2nd 8 pt

FFT unitOutput

unit

Data 16bit Start input

5 bit binarycounter

Start modecount

16 bit complex output

Data out

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INPUTUNIT

Three additional register

Input register bank

16 bit wordlength

and 57 complex samples

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Block diagram of input unit

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8 point FFT Unit

• Fully parallel 8 Point FFT

• Internal wordlength:16 bit

Signal flow graph of a 8 point FFT

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MULTIPLIER UNITInterdimensional Constants:

•49 non trivial interdimensional constants to be multiplied to result of 1st 8 point FFT.

(,s,l {1,2….7})•Only nine sets are unique

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Contd…

• (1,0), (0.995178, 0.097961), (0.980773, 0.195068),(0.956909, 0.290283), (0.923828, 0.382629), (0.881896,0.471374), (0.831420, 0.555541), (0.773010, 0.634338),

(0.707092, 0.707092)•Each constant decomposed as summation/subtraction

based on powers of 2.

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•Eg:0.991578 (1-

Circuit diagram of proposed multiplier unit-----hard wired representation of the constant

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TABLE IREALIZATION OF DIFFERENT CONSTANTS

IN TERMS OF POWER OF 2

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•Final design of multiplier unit,

Block diagram of complete multiplier unit

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TABLE IIUTILIZATION OF THE DIFFERENT HARD-WIRED CONSTANTS DURING THE

49 COMPLEX MULTIPLICATION OPERATION

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COMPARISON

Synthesized multiplier unit

Cell area:0.6 sqmm

Average power consumption:19m

W

Multiplier unit with 8 complex

multipliers

Cell area:1.1 sqmm

Average power consumption:31m

W

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Multiplier unit also has 2 shuffle network:1.Routes data to appropriate constants2.Maps multiplied data to appropriate index of CB unit.

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ARCHITECTURE OF TURBO64

Input unit

1st 8 pt FFT unit

Multiplier unit CB unit 2nd 8 pt

FFT unitOutput

unit

Data 16bit Start input

5 bit binarycounter

Start modecount

16 bit complex output

Data out

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OUTPUT UNIT

Block diagram of output unit

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MEASUREMENT RESULTS:

• Fabricated using 0.25micrometer 3 metal layer BiCmos process.

• 85 I/O ports• Average power dissipation over 55

fabricated chips:o 4.1mW at 1.8V @ 20MHz frequencyo 84mW at 2.5 V @ same frequencyo Maximum frequency of operation:o At 1.8 V=26 MHzo At 2.5 V=38MHz

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Die photograph of TURBO64 processor

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CONCLUSION

•Requires smaller no. of clock cycles •Better power perfomance, less silicon area• Proposed architecture can be used for any fast and

low power requirement operations.

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REFERENCES

• [1]A 64 point fourier transform chp for high speed wireless LAN application using OFDM-K.Maharatna,E.Grass,U.Jaghold

• [2] A. M. Despain, “Very fast Fourier transform algorithms hardware for implementation,” IEEE Trans. Comput., vol. C-28, no. 5, pp. 333–341,1979.

• [3]C. Chen and L.Wang, “A new efficient systolic architecture for the 2-D discrete Fourier transform,” in Proc. IEEE Int. Symp. Circuits and Systems,vol. 6, ch. 732, 1992, pp. 689–692.

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Thank You