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FRG-100

Technical Supplement

YAESU MUSEN CO., LTD.C.P.0, Box 1500, Tokyo, Japan

YAESU U.S.A.17210 Edwards Rd., Cerritos, California 90701, U.S.A.

YAESU EUROPE B. ViSnipweg 3.1118AA Schipol, The Netherlands

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-l

Chip C’mponent Information . . . -. . . . . . . l . - -. . - -. . . . *. . . . . . . . . . . . . . . . . . . . . . l-3Cse Disasembly & &cuit &ard Access - - l . - - - l - l l l - .. - - - - - l l l - - . - - . l - - - ‘J-1

Main Unit 2- l

Local Unit 2- l

Display Unit 2-3

Pilot Lamp & Lithium Battery Replacement 2-3

Resetting the Microprocessor 2-3&cuit Des&ption ......................... . ... . . . .......m.... ... ..... . . . . 3-lAlignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-l

Aligument Preparations & Precautions 4 - l

Local Uuit 4-2

Reference Oscillator 4-2

2nd Local Oscillator 4-2

v c o 4-2

vco 1&2 4-2

vco 3 4-2

vco 4 4-2

vco 5 4-2

Main Unit 4-2

2nd Local Amplifier 4-2

IF Interstage Transformer 4-2

IFGain 4-2

S-Meter Full Scale 4-3

Noise Blanker 4-3

SSB Squelch Threshold 4-3

Beep Leve 4-3Block & Interconnection J)iagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-l

PCB Diagram & Pa& List . . . . ... . . . . . . . . . . . . . sm.. . . l m. . . l l l a l . . . . . . . . . . . 6-1

Main Unit 6A-1

Local & OSC Unit 6B-1

PLL DDS Unit 6C-1

CAR DDS Unit 6D-1

Display Uni t 6E-1

SQL,VR,ENC & HP Unit 6F-1

FM hit-lOO( Option) 6G-1

TCXO-4( Option) 6H-1Mechanical Details . . . l . - - + -. l . . . . . . . . . . . . l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-l

Introduction

This manual provides technical inf orma-tion necessary for servicing the FRG-100 gen-ral coverage communications receiver. It doesnot include information on specifications, in-stallation, and Operation, which are describedin the FRG-100 Operating Manual, providedwith each receiver, or on FRG-100 accessories,which are described in manuals providedwith each.

Servicing ‘this equipment requires exper-tise in handling surface-mount components.Attempts by non-qualified persons to Servicethis equipment may result in permanent dam-age not covered by the warranty.

While we believe the technical informationin this manual to be correct, Yaesu assumes noliability for darnage that may occur as a resultof typographical or other errors that may bepresent. Your cooperation in pointing out anyinconsistencies in the technical informationwould be appreciated.

Yaesu Musen reserves the right to makechanges in this receiver and the alignmentprocedures, in the interest of technologicalimprovement, without notification of the0 wners.

l-lFRGl 00 Techm*cal Supplement

Chip Component Information

The diagrams below indicate some of thedistinguishing features of common Chip com-ponents.

Ceramic Capacifors

-i_f

Tantalum Capacifors

Negati

(Unit 1 mm)

Type L W T

Resistors

INDICATED LETTERS

1 2 3 4557s90 0

Type RMC l/lOW, 1/16W

Marking* 100,222,473*---

10’s unit 1’s unit Multiplier

0 0 10"1 1 10’

I

2 2 lo’ 13 3 10”4 4 10’5 5 1 OS6 6 10”

Examples 1100 = ion222 = 2.2kn473 = 47k0

1-3FRGl 00 Technicd Supplement

Chip Component InformationReplacing Chip Components

Chip components are installed at the fac-tory by a series of robots. The first one placesa small spot of adhesive resin at the locationwhere each part is to be installed, and laterrobots handle and place Parts using vacuumsuction.

For Single sided boards, solder Paste is ap-plied and the board is then baked to hardenthe resin and flow the solder. For double sidedboards, no solder Paste is applied, but theboard is baked (or exposed to ultra-violetlight) to eure the resin before dip soldering.

In our laboratories and Service shops, smallquantities of chip components are mountedmanually by applying a spot of resin, placingwith tweezers, and then soldering by verysmall dual streams of hot air (without physi-cal contact during soldering). We removeParts by first removing solder using a vacuumsuction iron, which applies a light steady vac-uum at the iron tip, and then breaking theadhesive with tweezers.

T h e special vacuum/desoldering equip-ment is recommended if you expect to do a lotof Chip replacements. Otherwise, it is usuallypossible to remove and replace Chip compo-nents with only a tapered, temperature-con-trolled soldering iron, a set of tweezers andbraided topper solder wick. Soldering irontemperature should be below 280” C (536” F).

Precautions for Chip ReplacementDO not disconnect a Chip forcefully, or the

foil Pattern may peel off the board.

Never re-use a Chip component. Dispose ofall removed chip components immediately toavoid mixing with new Parts.

Limit soldering time to 3 seconds or less toavoid damaging the component and board.

Removing Chip ComponentsCl Remove the solder at each joint, one joint at a

time, using solder wick whetted with non-acidic fluxes as shown below. Avoid applyingpressure, and do not attempt to remove tin-ning from the chip’s electrode.

0 Grasp the chip on both sides with tweezers,and gently twist the tweezers back and forth(to break the adhesive bond) while alter-nately heating each electrode. Be careful toavoid peeling the foil traces from the board.Dispose of the chip when removed.

0 After removing the Chip, use the topper braidand soldering iron to wick away any excesssolder and smooth the land for installation ofthe replacement part.

FREI 00 Techmkd Supplement

Chip Component Information

--

Installing a Replacement ChipAs the value of some Chip components is

not indicated on the body of the Chip, be care-51l to get the right part for replacement.

0 Apply a small amount of solder to the land onone side where the chip is to be installed.Avoid too much solder, which may Causebridging (shorting to other Parts).

.I.

0 Hold the chip with tweezers in the desiredPosition, and apply the soldering iron with amotion line as indicated by the arrow in thediagram below. DO not apply heat for morethan 3 seconds.

0 Remove the tweezers and solder the elec-trode on the other side in the manner justdescribed.

l-5FRGl 00 Techmkd Supplement

Case Disassembly & Circuit Board Access

- Main Unit Local Unit0 Turn off the receiver and disconnect all ca-

bles.

0 Place the set on a stable work surface, andremove the 8 screws affixing the top cover(Figure 1).

Figure 1.

0 Carefully remove the top cover, paying spe-cial attention to the wire connecting the loudspeaker to the main unit. The plug tan beremoved from the socket on the main boardif desired (remember to reconnect before at-tathing the top cover again).This exposes thecomponent side of the Main Unit.

0 To remove the main unit, remove the 8 screwsaffixing the unit and the screws affixing theantenna terminal and EXT DC connector onthe rear Panel (Figure 2).

Figure 2.

0

To access the local unit, remove the 8 screwsaffixing the bottom cover (Figure 3).

Figure 3.

To remove the local unit, remove the 7 screwsaffixing the unit, and the 2 screws used on theCAT connector on the rear Panel. This ex-poses the component side of the Local Unit(Figure 4).

Figure 4.

2-lFRGl 00 Tmlmical Supplement

Case Disassembly & Circuit Board AccessDisplay Unit0 To access the Display Unit (including poten-

tiometer, squelch, rotary encoder and head-phone jack), remove both the top and bottomcovers as previously described, then removethe 2 middle screws from both edges on eachside of the display unit (Figure 1).

Figure 1.

0 Next Zoosen the 2 remaining screws Gentlypull the unit away from the Chassis and foldit down (Figure 2).

Figure 2.

Cl To remove the Display Unit, slightly loosenthe hex nut affixing the main dial (do notuyIscrez.u it!) and pull it Off, then remove the 2screws located underneath (Figure 3).

Cl Gently pull off the VOL, SQL and M E Mknobs, then remove the 4 screws (2-each, top& bottom) attaching the front Panel to thedisplay unit Chassis.

Figure 3.

0

0

0

0

0 Remove the wiring connectors from the SQLand VOL controls on the rear of the DisplayUnit.

0 Gently press in the plastic catch which mateswith the tab on the Display Unit circuit boardto release and lower the front Panel (Figure4).

Figure 4.

Next, using a small flat screwdriver, gentlypry out and remove the wiring connectorfrom the back of the MEM knob, then removethe front Panel.

Gently pull the POWER, AlT (2pcs.), NB,and AGC buttons out from the Panel. Thenremove the spring screw, nylon washer,threaded brass collar and washer affixing therotary encoder shaft to the Chassis.

Remove and the 6 screws aff ixing the DisplayUnit circuit board to the Chassis (Figure 5).

Last, carefully remove the three wiring con-nectors from the bottom edge of the DisplayUnit circuit board to free the unit.

Figure 5.

FRGlOO Tedmicd Supplement

~__~_I_s_ _.-_.l..- . -_.______._._- ..“.----- .._.” --.--.. --. -

Case Disassembly & Circuit Board AccessPilot Lamp ReplacementCl Disconnect all cables and remove the top and

bottom covers as previously described.

0 Remove the 2 middle screws from both edgesof the display unit and loosen the 2 lowerscrews at the edge of each side.

‘Loosen

0 Locate the Pilot light then pull it out from it’sgrommet, trace the two blue wires leadingfrom the bulb to TP1005 & TP1006 on thecorner of the circuit board as shown below.Carefully unsolder these wires to remove thelamp and resolder the replacement lamp as-sembly (polarity of the wires is not impor-tant).

To Change the backup cell, use your fingersto remove the old cell from it’s holder (do notgrab it with metal tweezers or pliers, as thatcould short it out). Replace only with Sonyl i th ium type CR2032 (Yaesu Par t No.Q900564), or equivalent .

Removing Lithium Ce11

Slide cell inward, then pry up to eject

Inserting Replacement Battery

Pilot Lamp TP1005 & TP1006

Battery replacementThe lithium backup battery tan be re-

placed by removing the bottom cover (as pre-viously described). Battery location is shownbelow.

Slide battery downward through slot, theninward and release

Resetting the microprocessorFunctional Problems involving frequency,

mode and memory selection tan sometime beresolved by simply resetting the microproces-sor. There are two ways to reset the CPU in theFRG-100, both of which clear the contents ofall memories, leaving them at the factory de-faults.

Soft Reset

The procedure relies on a ROM routinewhich should normally suffice to correct mostoperating malfunctions.

0 Turn the receiver Off, then hold the MEMCLEAR button while switching the receiverback on. If the Problem still persists, proceedto the hard reset.

FRGlOO Techmixl Supplement2-3

Case Disassembly & Circuit Board AccessHard Reset

D Turn the receiver off, then disconnect the DCpower Source. Turn the BACK UP switch onthe rear Panel to OFF. Reconnect the DCpower Source, then turn the receiver back on.

BACK UP

ON OFF

BACK Ul? SWITCH

2-4FRGl 00 Technical Supplement

Circuit Description

This description, together with the blockdiagram, is intended to provide a general un-derstanding of the electrical functions of thecircuits of the FRG-100. Such an under-standing is necessary for troubleshooting thereceiver. Refer to the schematics diagrams andParts lists for specific component and wiringdetails.

Front-End StagesIncoming RF from the antenna jack is deliv-

ered to the main unit after passing through a9:l impedance transformer Tl004 (if Hl-Z an-tenna is selected using the rear-Panel switch)and surge suppresser D1005, which removeshigh voltage electrostatic pulses which mightotherwise darnage components in the front-end. It is then low-pass filtered and attenu-ated (if enabled). The received Signal is thenimpedance transformed by transformerT1018, then band-pass filtered to suppress in-termodulation by Signals from other bands.The correct bandpass filter is selected by BCDcontrol Signals from the PLL unit, and de-coded by Q1032 (SN74LS145N). The Signal isthen once again impedance transformed byT1005, before entering the 1st mixer Stage.

._.

The Signal then enters the balanced 1stmixer, consisting o f Q1009/Q1013(2SK125X2), along with the 1st local oscillatoroutput from the local unit (47.260 w 77.210MHz) which has been amplified by Q1006(2SC2053), and low-pass filtered by C1014,L1005, C1013, L1004, and C1012. The result-ing 47.21 MHz 1st mixer product Passesthrough monolithic crystal filters XFlOOl andXF1002 ( f 20 kHz BW) where other unwantedmixer products are stripped away to producethe filtered 1st IF Signal.

IF StagesThe filtered 1st IF Signal is then amplified

,^. by Q1011(3SK179), and applied to balanced2nd mixer QlOlO & Q1012 (2SK302x2), whichalso receives the 2nd local Signal generatedfrom 46.775 MHz crystal X2002 and amplifiedby QlOO8 (2SC2620), to produce the 455 kHz

2nd IE When FM Operation is selected, a por-tion of this 455 kHz product of the 2nd mixeris buff er-amplified by QlO38 and delivered tothe optional FM UNIT-1 00 for detection(wheninstalled) For other modes, the 455 kHz Signalis Passes through the noise blanker gate(D1009, DlOlO & D1014) and is then filteredby ceramic filters CF1 001, CF1002, or CF1 003(depending on selected mode) where otherproducts are stripped away

Final IF amplification is provided byQl018, QlO17, and Q1016 (3SK131-V12) be-fore the Signal is applied to buffer amplifierQ1016 (3SK131-V12) and then enters detec-tion circuitry.

For SSB and CW modes, the amplified IFSignal is applied to the product detector con-sisting of D1033, D1038, DlO39, and D1040(lSS198x4). Here, it is mixed with the appro-priate BFO(carrier) Signal for either LSB, CWor USB from the DDS unit, having been buff-ered by Q1028. The detected Signal thenPasses through a LPF consisting of R1129 andCl141 before delivery to analog switch Q1023-4. The Signal enters the active filter Ql026-1,which functions as a low pass filter for audiobefore delivery to analog switch Ql501.

For AM reception, another buffered outputfrom the 2nd IF is detected by D1032, theoutput of which serves as both the detectedAM Signal and AGC. This Signal then Passesthrough the LPF formed by R1208 and Cl130before delivery to analog switch Q1023-3 andon for audio amplification.

Aud io Amp lif iersThe low level detected audio in all modes

pass through mute switch Q1023-l(when notmuted by the squelch control lines), and thenbuffer amplifier Q1026-2. The Signal Passesthrough another mute circuit Q1031 & (21046(DTC144EK) and is mixed with beeper audiofrom the microprocessor having passedthrough the LPF and VR1005. The mixedaudio is amplified by Q1034 (TDA2003H) todrive a 4 w 8 Q loudspeaker or headphone.The output from Q1034 is controlled by VOL

1 .FRGI 00 Techm*cal Supplement

Circuit DescriptionPotentiometer VR3601 located on the VRUnit. A Sample of the pre-amplified audio @600 &2 is also delivered to the REC jack on therear Panel.

Noise Blanker & AGC CircuitIn the AM, SSB and CW modes, when the

noise blanker is on, a Portion of the 455 kHz2nd IF Signal is tapped from the output ofT1011, then Passes through noise blanker am-plifiers 41004 & QlOO5 (3SK131-V12), and de-tected by D1003 & D1004, then fed back to theamplifiers Q1004 &’ QlOO5, controlling theirgain. The response time of this loop is de-signed so that noise pulses detected at D1003&D1004 produce a strong DC pulse for theduration of each RF noise pulse. This DCblanking Signal is returned to the noise blank-ing gate Controller (D1009, DlOlO & D1014),switching them off during the noise pulse andpreventing the 2nd IF Signal from reachingthe narrow IF filters while the noise is present.

Receiver AGC is provided for all modes,with a selectable fast or slow decay. The out-put Signal from buffer amplifier QlOl9 is rec-tified by AGC detector D1026 and D1027(lSS198x2), and then delivered to AGC am-plifier Q1020 (2SC2712). The Signal is proc-essed by QlOl5 (2SJ125), then amplified againby Q1014-1 and delivered to QlOll, QlOl8,and Q1017 to control amplifier gain, S-meterand squelch level.

PLL Frequency SynthesizerThe PLL section on the Local Unit consists

of Main Loop, DDS and the 2nd local oscilla-tor circuitry. The PLL IC Q2030 (CX-7925B)contains a reference oscillator/divider, serial-parallel data latch, programmable divider,and a Phase comparator.

1st Local Signal Generation

The 1st local Signal (47.260 - 77.210 MHz)is generated by PLL Synthesis under control ofCPU on the Local Unit. In the main loop, oneof VCOs Q2015-Q2018 is activated by theCPU and selected via Q2040 (M54564P) ac-cording to the frequency of Operation. Theoutput of the selected VCO is buffered byQ2045 (2SK192) and Q2011 (2SC535) before

delivery to mixer Q2012 (uIIX1037H)This sig-na1 is then mixed with the DDS Signal andlow-pass filtered, buffered by Q2021(2SK192)and amplified by Q2024 (2SC535) before be-ing returned to PLL IC Q2030.

In the main divider/phase comparator sec-tion of PLI, IC, the VCO Signal is divided by128, according to a control Signal (serial di-vider programming data) from the CPU toproduce 83. .92 kHz.

This Signal is then applied to the Phasedetector section for Phase-comparison withthe 10.4875 MHz reference Signal from theOSC UN IT. Any Phase differente between thetwo Signal will produce a 5-V pulsed-DC out-put with pulse duration depending on thePhase differente. This pulse train is convertedto DC by charge pump 42025 (2SK184) andQ2023 (2%3732),and low-pass filtered to pro-duce the varactor control voltage (VCV), andthen is applied to the varactor D2002 - D2005(lSV103x4) in the selected VCO to Cause theVCO oscillating frequency to be Phase-lockedto the 10.4875 MHz reference.

The PLL, local Signal for Loop 1 is the prod-uct of either Loop 1 Local Mixer (Q2012), orthe product of the output of this mixer furthermixed with the 10.4875 crystal reference sig-nal, according to the band of Operation.

2nd Local Signal Generation

A Portion of 2nd local oscillator Signal(46.755 MHz), which is derived fromQ2031(2SK:192)/X2002, is delivered to mixerQ2028 (SN-16913), it also is applied to the 2ndlocal amplifier (on the main unit) after attenu-ation and passing through the LPF formed byL2023, C21.46 & C2147.

The sampled reference Signal (10.48576MHz), which is generated by Q2030, is halvedby frequency divider 42032-2. The outputfrom the divider (5.24288 MHz) is low-passfiltered, then mixed with the DDS output(286.16 - 368.07 kHz) in mixer Q2034(SN1 6913), which is also controlIed by theMPU. The output from Q2034 is band-passfiltered (5.57 MHz) by CF2001 before deliveryto mixer Q2028 (SN16913) along with the 2ndlocal Signal. The mixer product is band-pass

FRGl 00 Techmkd Supplement

Circuit Descriptionfiltered before amplification by Q2019(2SC535), and then applied to the mixer of themain loop Q2012 (uPC1037H) as a sub-loopSignal.

Although the reference frequency of themain loop is 81.92 kHz, a 10 Hz receivingfrequency step is obtained by mixing a sub-loop Signal with the main loop. The VCO isthus Phase-locked to the reference Signal.

Miscellaneous Con trol LogicBand selection for the PLL Loop 1 Local

Signal is provided from the CPU by encoderQ2005 (M14558CP) and switch driver 42040(M54564P). Whenever either VCO Loop be-

Comes unlocked, and unleck line (from pin 8of Q2030) controlled by Q2027 (BAlA4P) sig-nals the CPU, which then mutes receiveraudio and blinks the display until the PLLsresume leck.

The MPU provides band (BPF) selection onthe Main Unit via latch Q1032(SN74LS145N),and mode/filter selection using switchinggates Q1023-2-Q1023-4 and Q1054.

Rotary encoded tuning data from the maindial is processes by dial counter Q2044(FQ7924), and transferred to the MPU via anS-bit data bus. Q2041 contains a real-timeclock with reference oscillator crystal.

“V

FRGI 00 Techmkal Supplement

The FRG-100 is carefully designed to allowthe knowledgeable Operator to make nearlyall adjustments for various Station conditions,modes and Operator preferences simply fromthe controls on the front and rear Panels, with-out having to open the case of the transceiver.The FRG-100 Operation manual describesthese adjustments, plus certain internal set-tings.

..-

The following procedures cover the some-times critical and tedious adjustments that arenot normally required once the transceiverhas left the factory. However, if darnage oc-curs and some Parts subsequently are re-placed, realignment may be required. If asudden Problem occurs during normal opera-tion, it is likely due to component failure; re-alignment should not be done until after thefault component has been replaced.

We recommend that servicing be per-formed by authorized Yaesu Service techni-cians, experienced with the circuitry and fullyequipped for repair and alignment. So, if afault is suspected, you should contact the sell-ing dealer for instructions regarding repair.Authorized Yaesu Service technicians havethe latest modification information, and re-align all circuits and make complete perform-ante Checks to ensure compliance withfactory specifications after replacing faultycomponents.

Those who do undertake any of the follow-ing alignments are cautioned to proceed attheir own risk. Problems caused by unauthor-ized attempts at realignment are not coveredby the warranty policy. Also, Yaesu must re-serve the right to change circuits and align-ment procedures in the interests of improvedPerformance, without notifying owners.

,..

Under no circumstances should any align-ment be attempted unless the normal functionand Operation of the receiver are clearly un-derstood, the Cause of the malfunction hasbeen clearly pinpointed and any faulty com-ponents replaced, and the need for realign-ment determined to be absolutely necessary.

The following test equipment (and thor-ough familiarity with it’s correct use) is neces-sary for complete realignment. Correction ofthe Problems caused by misalignment result-ing from use of improper test equipment isnot covered under the warranty policy. Whilemost Steps do not require all of the equipmentlisted, the interactions of some adjustmentsmay require that more complex adjustmentsbe performed afterwards. DO not attempt toperform only a Single step un less it is clearlyisolated electrically from all other Steps.Rather, have all test equipment ready beforebeginning, and follow all of the Steps in asection in the Order they are presented.0 Digital DC Voltmeter

0 RF Millivoltmeter

Cl AF Millivoltmeter

0 RF Standard Signal Generator/calibratedoutput and dB scale, 0 dBp=0.5 PV

0 Frequency Counter

0 FM Unit-100

0 SINAD Meter

Alignment Preparations G) Precautions0

0

0

.

Except where specified otherwise, the re-ceiver should be tuned to 14.2 MHz, and thefollowing controls set as indicated;

all buttons off

all knobs fully CCW (minimum)

After completing one Step, read the follow-mg step to determine whether the same testequipment will be required. If not, remove thetest equipment before proceeding.

Correct alignment requires that the ambi-ent temperature be the same as that of thereceiver and test equipment, and that thistemperature be held constant between 20 and30” C (68 - 88” F). If the receiver is brought intothe shop from hot or cold air it should beallowed some time for thermal equalizationwith the environment before alignment.

Alignments must only be made with theoscillator shields and circuit boards firmly in

. .FRGl 00 Techmkd Supplement

Alignment

place. Only one extender board (if optional)should be installed at a time for access to theboard being aligned. Also, the test equipmentmust be thoroughly warmed up before begin-ning.

Note: Signal levels in dB referred to inalignment are based on 0 dBp=0.5pV.

Table note: DC voltages should be withinflO% of those listed in the voltage tables.

Local Unit

(1) Ref erence Oscillator

Cl

0

0

Connect the frequency counter to TP2005.

Adjust TC2701 for 10.485760 MHz f 5 Hz.

If the TCXO is installed, tonfirm 10.485760MHz &5 Hz on the counter.

(2) 2nd Local Oscillator

0

0

0

0

Connect a 50-$2 resistor in parallel with thefrequency counter across the socket J2011.

Adjust T2004 for 46.755 MHz &6OOHz on thecounter.

Replace the counter with the RF millivoltme-ter, and tonfirm at least 45 mVrms.

Connect the RF millivoltmeter to TMOOl, andadjust T2001, T2002, and T2003 for maximumindication (at least 60 mVrms) on the meter.

(3) vco

VCOZ and 20 Tune the receiver to 3.999 MHz and select

USB mode.

0 Connect the DC Voltmeter to TP2002 (whileadjusting VCOs, connect the DC Voltmeter toTP2002)

0 Adjust L2003 for 7.0 & 0.1 V.

0 Confirm the voltage as shown below.

Frequency (MHz)0.050

Volts DC0.9 - 1.4

vco30 Tune the receiver to 14.499 MHz in USB

mode.

0 Adjust L2005 for 7.0 V ti.l V.

0 Tune the receiver to 8.00 MHz, and tonfirm1.1 to 1.6 V on the meter.

v c o 4

0

0

0

Tune the receiver to 21.999 MHz in USBmode.

Adjust L2006 for 7.0 V fl.1 V.

Tune the receiver to 14.500 MHz, and tonfirm0.8 to 1.3 Volts on the meter.

v c o 5

0 Tune the receiver to 30.000 MHz in USBmode.

0 Adjust L:2007 for 7.0 V rto.1 V.

0 Tune the receiver to 22.000 MHz, and tonfirm1.4 to 1.9 V on the meter.

Main Unit

(1) 2nd Local Amplifier

0 Connect the RF millivoltmeter to TPl003.

0 Adjust Tl003 on the local unit for maximum(at least ‘500 mV) on the meter.

(2) IF Werstage Transformer

0

0

0

0

0

Install the FM Unit (Option) to the Main Unit,and select FM mode.

Connect the RF Signal generator to the an-tenna jack, and inject an 80 dBp Signal at14.200 MHz.

Adjust Tl006 through Tl009 for Optimum 12-dB SINAD (adjust the injection level as neces-sary).Turn the modulation switch (of the Signalgenerator) Off, and inject an 80 dBp Signal at14.200 MHz.

Adjust Tl011 through Tl017 and Tl019 insuccession several times for peak S-meter in-dication. (adjust the injection level as neces-sary)

(3) IF Gain

0 Inject 6 dBp at 14.200 MHz to the antennajack, and tune for peak on the S-meter.

FRGlOO Technical Supplement

Alignment

-_-

0 Adjust VR1002 for S-l deflection.

(4) S-Meter Full-Scale

0 Inject 100 dBp at 14.200 MHz to the antennajack, and tune for peak on the S-meter.

0 Adjust Tl001 and Tl002 for minimum volt-age on the meter (adjust the injection level asnecessary).

(6) SSB Squelch Threshold

0 Adjust VR1001 for S9 +60 dB on the S-meter.

(5) Noise Blanker

0

Cl

With the receiver tuned to 14.200 MHz, pressthe NB button.

Inject 40 dBp at 14.200 MHz to the antennajack, and connect the DC Voltmeter toTP1003.

0 In the USB mode, with no Signal at the an-tenna jack, set the SQL control to the ll-o’clock Position, and adjust VR1004 so thatthe squelch just closes.

(7) Beep Level

0 Set VR1005 to the lO-o’clock position.

_I

T2004 J2011

'SI T2003i

z;-a, ,A.Fs , T2002 Ll Y -T2001

- T P 2 0 0 1-TP2002

-L2007

-L2006

PL2005

---L2003

- T C 2 7 0 1

- T P 2 0 0 5

I TP1003Tl002Tl001Tl007

1 Tl0171VRiOOl VR1002

Tl003Tl013

Tl014

: Yr Tl006Ort:!8’ VR1004

--------VRl005'I lTl019

-Tl015

4-3FRGl 00 Technical Supplement