web.ece.ucsb.edu...1 transistor and ic design for 50ghz and above mark rodwell, ucsb short course,...
TRANSCRIPT
1
Transistor and IC design
for 50GHz and above
Mark Rodwell, UCSB
Short Course, July 26, 2017, Qualcomm San Diego
mm-wave systenms:Prof. U. Madhow & group: UCSB
mm-wave ICsS-K Kim, R. Maurer, A. Ahmed, H. Yu, H-C. Park, T. Reed, UCSBProf. J. Buckwalter & group, UCSBJ. Hacker, Z. Griffith: Teledyne Scientific and ImagingM. Seo: Sungkyunkwan University
mm-Wave Transistors :J. Rode, P. Choudhary, B. Markman, Y. Fang, J. Wu, A.C. Gossard, B. Thibeault, W. Mitchell: UCSB M. Urteaga, B. Brar: Teledyne Scientific and Imaging
2
Why mm-wave wireless ?
3
Overview
4
mm-Waves: high-capacity mobile communications
Needs→ research:RF front end: phased array ICs, high-power transmitters, low-noise receiversIF/baseband: ICs for multi-beam beamforming, for ISI/multipath suppression, ...
5
mm-Waves: benefits & challenges
Massive # parallel channels
Need mesh networksNeed phased arrays (overcome high attenuation)
5
Large available spectrum
line-of-sight MIMO
spatial
multiplexing
(note high attenuation in foul weather)
6
mm-Wave Wireless Needs Phased Arrays
R
dtransmitte
received eRP
P
2
2
isotropic antenna → weak signal →short range
highly directional antenna → strong signal, but must be aimed
no good for mobile
beam steering arrays → strong signal, steerable
32-element array → 30 (45?) dB increased SNR
must be precisely aimed →too expensive for telecom operators
R
rt
dtransmitte
received eR
DDP
P
2
2
R
transmitreceive
transmit
received eR
NNP
P 2
2
7
Millimeter-wave imaging
235 GHz video-rate synthetic aperture radar
10,000-pixel, 94GHz imaging array→ 10,000 elements
Go
lcuk: Tran
s MT
T, Au
g 20
14
1 transmitter, 1 receiver100,000 pixels20 Hz refresh rate5 cm resolution @ 1km50 Watt transmitter
(tube, solid-state driver)
Demonstrated:SiGe (UCSD/Rebeiz)
~1.3kW: 10,000 elementsLower-power designs:
InP, CMOS, SiGe(UCSB, UCSD, Virginia Poly.)
8
mm-wave imaging radar: TV-like resolution
What you see in fog What 10GHz radar shows What you want to see
goal: ~0.2o resolution, 103-106 pixels
Large NxN phased array Frequency-scanned 1xN array
mm-waves → high resolution from small apertures
ultimate: ~400 GHz; intermediate: ~140 GHz
9
mm-wavesystems
10
Target Systems
10
11
arrays
12
Antenna & array basics
heightelement steering vertical
(radians) dthelement wi
steering horizontal
.range ngbeamsteeri maximum setselement Individual
2
areaarray 4ty)(directiviGain
heightarray beamwidth vertical
(radians) harray widt
beamwidth horizontal
gain and beamwidth setsarray Overall
13
Electronic Beamsteering, a.k.a. phased array
./2 elementsadjacent between shift phase electrical Required
sin differencelength Path
. angle physicalat phase intoback signals bring shifters-Phase
l
Dl v
14
Reminder: Multipath Propagation
npropagatiopath -multi:paths signalMany
pattern. beam antennain objectsMany
antennas)y directivit-(lowbeamwidth angular largeGiven
reflection ofStrenght
antennas ofy Directivit
strenght signaldifferent haspath Each
shift. phase possible :conditionboundary surface Reflecting
delay.different length,different haspath Each
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Fading vs Intersymbol interference
periods symbollonger :ODFM useor
receiverin equalizer adapitive need
another with interfers periodbit One
ceinterferen lIntersymboperiod) Symbol spread(Delay
separation eappropriatat antennas receiving two:fix
signalery weak possibly vceinterferenphase ofout are Carriers
aligned~ periods symbol with arrive signals NLOS and LOS
Fadingperiod) Symbol spread(Delay
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Beamforming can suppress ISI
0
0.5
1
1.5
2
0 1 2 3 4 5 6
1Gbaud
10 Gbaud
(dela
y s
pre
ad
)/ (
sym
bo
l p
eri
od
)
scatterer lateral offset, degrees , meters at 100 meters range
fad
ing
ISI
1050
typical beamwidth: 10o or less FWHM
Dc
H
2spreadDelay
2
1 Gbaud with 10o array beamwidth :multipath mostly causes fadingnot much ISI
10 Gbaud with 10o array beamwidth :significant fading and significant ISI
Solution 1: larger arraysnarrower beamwidth
Solution 2: multiple arraysmultiple receivers to handle fading ?can sum these to form narrow nulls! also handles fading and ISI
17
Optimum array size for low system power
10-2
10-1
100
101
102
103
10 100 1000
To
tal S
yste
m P
ow
er,
Wa
tts
# of transmitter array elements, # of receiver array elements
PA saturated
ouput power/element
PA total DC
power consumption
Phase shifter
+distribution+LNA
DC power consumption
total DC power
0.2W phase shifters, 0.1 W LNA
22
22 1
NP
RN
P
Ptransmit
transmit
receive
?power save arrays large Do
.shifters.. phase LNA, ofpower efficiency
power system Total NPtransmit
At optimum-size array,target PA output poweris typically 10-200 mW
18
How big should be the array ?
Large arrays:more directive→ less PA power neededmore channels→ cost, DC power
10 100 1000
Po
we
r, W
att
s
# of transmitter array elements, # of receiver array elements
PA saturated
ouput power/element
PA total DC
power consumption
Phase shifter
+distribution+LNA
DC power consumption
total DC power
0.2W phase shifters, 0.1 W LNA
140GHz
4 dB noise figure,
20% PAE
Rodwell,
2013 APMC, Seoul
example only;#s need updating
Large arrays:more directive→less SNR loss with NLOS nullingeases multipath equalization
19
Data delay equalization in large arrays
lesbetween ti
retimed modulationwith
*ngarray tili*by compensate
:arrays largeVery
sinbandwidth
2/~ below bemust ;sin
skew timing
modulation not thebut carrier theretime arrays Simple
D
c
Tc
Dsymbol
20
systems
21
mm-Wave LOS MIMO: multi-channel for high capacity
Torklinson : 2006 Allerton ConferenceSheldon : 2010 IEEE APS-URSI Torklinson : 2011 IEEE Trans Wireless Comm.
22
Spatial Multiplexing: massive capacity RF networks
multiple independent beamseach carrying different dataeach independently aimed# beams = # array elements
Hardware: multi-beam phased array ICs
23
100-1000 GHz Wireless Needs Mesh Networks
Object having area~R
will block beam.
Blockage is avoided using beamsteeringand mesh networks.
...high-frequency signals are easily blocked.
...this is easier at high frequencies.
24
mm-wavepropagation
25
Fair-Weather Propagation
Wiltse, 1997 IEEE Int. APS Symposium, JulyFair weather
2-5 dB/km
75-110 GHz
200-300 GHz
125-165 GHz
9km elevation
4km elevation
sea level
26
Foul Weather Propagation
0.1
1
10
100
109
1010
1011
1012
Rain
Atte
nu
atio
n,
dB
/km
Frequency, Hz
100 mm/Hr
50 mm/Hr
30 dB/km5
0 G
Hz
Extreme Fog (1g/m3)
~(25 dB/km)x(frequency/500 GHz)
4
Rain:10-3: 25mm/hr, 11dB/km10-4: 50-85mm/hr, 19dB/km10-5: 100+mm/hr: 30dB/km
Olsen, Rogers, Hodge, IEEE Trans Antennas & Propagation Mar 1978 Liebe, Manabe, Hufford, IEEE Trans Antennas and Propagation, Dec. 1989 Liebe, IEEE Trans Ant and Pro, Vol 31, No. 1, Jan 1983Karasawa, Maekawa, IEEE Proc, Vol 85 , #6 , June 1997
35oC, 95% Humidity loss (dB/km)~(frequency/60GHz)2
11 dB/km@200 GHz, 5.5dB/km@140GHz
Rosker; Wallace, 2007 IEEE IMS
27
Atmospheric Attenuation: Implications
0.01
0.1
1
10
100
0 50 100 150 200 250 300 350
Rain
Atte
nu
atio
n,
dB
/km
Frequency, GHz
Rain: 25, 50, 100 mm/hr
~10-3
, 10-4
, 10-5
95% humidity, 35C
Fog, 1G/m3
Worst-case attenuation roughly constant over 50-250 GHz.10-5 outage rate: equal losses over 50-300 GHz10-3 outage rate: equal losses over 50-200 GHz
target should be 50-250 GHz links. Exclusive use of VLSI Si processes forces use of 50-180GHz
28
detailed link analysis
29
Example Link budgets (60 GHz)
o
FHWM
o
FWHM
radians
FHWM
radians
FWHM
effAD
000,414/4 2
22 )/)(16/(/ RDDPP rttransreceived
SNR where2
)4( QkTFBQP QPSKreceivedNote various margins allocated.Rain losses calculated from rain rate.
array:16 elements (2x8)4.5 x 1.0 inches11.5 x 2.54 cm
30
Example Link budgets (140 GHz)
o
FHWM
o
FWHM
radians
FHWM
radians
FWHM
effAD
000,414/4 2
22 )/)(16/(/ RDDPP rttransreceived
SNR where2
)4( QkTFBQP QPSKreceivedNote various margins allocated.Rain losses calculated from rain rate.
array:16 elements (2x8)1.9 x 0.43 inches4.9 x 0.11 cm
31
hardware: rough numbers
32
140 GHz, 10 Gb/s Adaptive Picocell Backhaul
33
140 GHz, 10 Gb/s Adaptive Picocell Backhaul
350 meters range in 50mm/hr rain
PAs: 24 dBm Psat (per element)
LNAs: 4 dB noise figure
Realistic packaging loss, operating & design margins
34
340 GHz, 160 Gb/s MIMO Backhaul Link
→ 1o beamwidth; 8o beamsteering
35
340 GHz, 160 Gb/s MIMO Backhaul Link
600 meters range in five-9's rain
1o beamwidth; 8o beamsteering
PAs: 21 dBm Psat (per element)LNAs: 7 dB noise figure
Realistic packaging loss, operating & design margins
36
60 GHz, 1 Tb/s Spatially-Multiplexed Base Station
2x64 array on each of four faces.
Each face supports 128 users, 128 beams: 512 total users.
Each beam: 2Gb/s.
200 meters range in 50 mm/hr rain
PAs: 20 dBm Pout , 26 dBm Psat (per element)LNAs: 3 dB noise figure
Realistic packaging loss, operating & design margins
37
mm-Wave Wireless Transceiver Architecture
custom PAs, LNAs → power, efficiency, noiseSi CMOS beamformer→ integration scale
...similar to today's cell phones.
38
400 GHz frequency-scanned imaging radar
What you see with X-band radarWhat your eyes see-- in fog
What you would like to see
38
39
400 GHz frequency-scanned imaging car radar
39
40
400 GHz frequency-scanned imaging car radar
Image refresh rate: 60 Hz
Resolution 64×512=32,800 pixels
Angular resolution: 0.10 degrees
Aperture: 12" by 12"
Angular field of view: 9 by 97 degrees
Component requirements: 10 mW peak power/element, 3% pulse duty factor6.5 dB noise figure, 5 dB package losses5 dB manufacturing/aging margin
Range: see a basketball at 300 meters (10 seconds warning) in heavy fog(10 dB SNR, 28 dB/km, 1 foot diameter target, 65 MPH)
40
41
Transistorsand IC technologies
42
Production Semiconductor Processes for mm-Wave
Silicon Germanium BiCMOS Processes
foundry process nominal fmax useful range
IBM (GF !) 9HP 320 GHz ~170 GHz
TowerJazz SBC13H3 270 GHz ~140 GHz
TowerJazz SBC18H4 (near release) 350 GHz ~180 GHz
ST Microelectronics S9MW 270 GHz ~140 GHz
ST Microelectronics SB55 (development) 340 GHz ~180 GHz
"Useful (frequency) range" means those frequencies at which acceptable-performance IC blocks can be realized, not the highest frequency of a published research result.
43
Production Semiconductor Processes for mm-Wave
VLSI CMOS Processes
foundry process nominal fmax useful range
various (IBM, GF, TSMC) 65nm bulk CMOS ~~250GHz ~130GHz
IBM (GF !) 45nm PD-SOI (high leakage power) ~~300 GHz ~150 GHz
IBM (GF !) 32 nm UTB-SOI ~~300 GHz ~150 GHz
ST Microelectronics 28 nm UTB-SOI similar to above
various 22nm, ~14nm UTB-SOI poorer than above
Intel, IBM/GF 22nm, ~14nm finFET likely poorer than above,
Generations beyond 28/32nm: progressively poorer performance in 100+ GHz ICsprogressively lower transmitter power at all frequencies
44
Semiconductor Processes for mm-Wave
Production III-V foundries
foundry process nominal fmax useful range
Northrop-Grumman(low-volume)
600nm InP HBT: 4V: higher-power transmitters
>300GHz ~150 GHz
Northrop-Grumman(low-volume)
100nm InP HEMT (FET)for very low noise receivers
>350GHz ~200 GHz
Qorvo (Tri-Quint) TQP13 HEMTpower amps, low-noise -amps
~~150GHz 100 GHz
These processes are best for single-stage add-on power amps, low-noise amps;both to increase system range.
45
Research Semiconductor Processes
Research institutions with some "foundry-like" access
foundry process nominal fmax useful range
Teledyne 250nm InP HBT 700GHz ~250 GHz
Teledyne 130nm InP HBT 1100 GHz ~450 GHz
IHP 130nm SiGe BiCMOS 500GHz ~250 GHz
microwave GaN HEMT is a production technologymm-wave GaN HEMT may become a production technologymm-wave InP HBT may become a production technology
46
mm-wave CMOS (examples)
260 GHz amplifier: 65nm bulk CMOS, Over-neutralized to reach Gmax, 9.2 dB, 4 stagesMomeni ISSCC, March 2013
150 GHz amplifier: 65 nm bulk CMOS, 8.2 dB, 3 stages (250GHz fmax)Seo et al. (UCSB), JSSC, December 2009
300 GHz fmax
47
mm-Wave CMOS won't scale much further
Gate dielectric can't be thinned → on-current, gm can't increase
Tungsten via resistances reduce the gainInac et al, CSICS 2011
0
0.1
0.2
0.3
0.01 0.1 1
no
rma
lize
d
tra
nsco
nd
ucta
nce
(electron effective mass)/mo
one band minimum
EOT + body thickness term = 1nm
0.6 nm
0.4 nm
0.3 nm
Shorter gates give no less capacitance dominated by ends; ~1fF/mm total
Maximum gm, minimum C→ upper limit on ft.about 350-400 GHz.
Present finFETs have yet larger end capacitances
48
III-V high-power transmitters, low-noise receivers
Cell phones & WiFi:GaAs PAs, LNAs
mm-wave links needhigh transmit power, low receiver noise
0.47 W @86GHz
0.18 W @220GHz
1.9mW @585GHzM Seo, TSC, IMS 2013
T Reed, UCSB, CSICS 2013
H Park, UCSB, IMS 2014
49
InP Bipolar Transistors
50
Why InP Bipolar Transistors ?
InP better electron transport than Si collectorshigher electron velocity 3.5 vs 1.0 × 107 cm/s plus wider bandgap→ higher breakdown field
InGaAs base, base-emitter heterojunction: very low base sheet resistances
Implications: ~3:1 higher (ft, fmax) at a given scaling nodehigher breakdown* at a given (ft, fmax) but...InP HBT not a production technology
*Breakdown is too complicated to summarize with BVCEO.BVCBO vs. BVCEO vs. safe operating area ?Bottom line: look at Vce used in published IC data for a given IC technology.
51
Transistor scaling laws: ( V,I,R,C,t ) vs. geometry
AR contact /
Bulk and Contact Resistances
Depletion Layers
T
AC
v
T
2t
2
max)(4
T
Vv
A
I applsat
Thermal Resistance
Fringing Capacitances
~/ LC finging~/ LC finging
dominate rmscontact te
escapacitanc fringing FET )1
escapacitancct interconne IC )2
W
L
LK
PT
th
ln~transistor
LK
PT
th
ICIC
Available quantum states to carry current
→ capacitance, transconductancecontact resistance
L
52
Bipolar Transistor: Structure & Models
nkTqIg Em /
)( cbmjebe gCC tt
mbe gR /
""
2
2/
/2/
satcc
thermalbnbb
vT
vTDT
t
t
collex
E
bc
E
jecollectorbase RRqI
nkTC
qI
nkTC
ftt
t2
1
53
Base-Collector Distributed RC Parasitics
emitteremittercontactex AR /,
Eesspread LWR 12/ ELlength emitter
Egapsgap LWR 4/
Ebcscontactspread LWR 6/,
contactsbasebasecontactcontact AR _, /
cemitterecb TAC /,
cgapgapcb TAC /,
ccontactsbasecontactcb TAC /_,
54
RbbCcb Time Constant, Fmax , Simple Hybrid- model
where8max cbibbCRff t
)(
)2/(
,,
,,
,
spreadgapcontactspreadcontactecb
gapcontactspreadcontactgapcb
contactcontactcbcbibbcb
RRRRC
RRRC
RCCR
t
above from fit set to ratio :
total true
resistance base totaltrue
maxfCC
CCC
R
cbxcbi
cbcbxcbi
bb
Vaidyanathan & PulfreyIEEE Trans. Elect. Dev.Feb. 1999
55
BJT Space-Charge-Limited Current (Kirk effect)
. increased with increases holdKirk thres
.high at increased, ), ( Decreased max
ce
cb
V
JCfft
0
2
4
6
8
10
12
14
16
0 0.5 1 1.5 2 2.50
5
10
15
20
25
30
35
40
Je (
mA
/mm
2)
Vce
(V)
Ajbe
= 0.6 x 4.3 mm2
Ib step
= 180 uA
Vcb
= 0 V
Ic (mA
)Peak f
t, f
max
2
min,max /)2(2 ccbcbEeff TVVAvI
2
3
4
5
6
7
8
0 2.5 5 7.5 10 12.5
Ccb/A
e (
fF/m
m2)
Je (mA/mm
2)
-0.2 V
0.0 V
0.2 V
Vcb
= 0.6 V
100
200
300
400
500
0 2 4 6 8 10 12
f t (G
Hz)
Je (mA/um
2)
ft, -0.3 V
cb
0.0 Vcb
-0.2 Vcb
0.2 Vcb
0.6 Vcb
/)/(// 22 vJqNx D
56
InP: Electron velocity modulation
More collector voltage→ less distance before scattering→ more transit time
more collector voltageless collector voltage
light G valley
heavy L valleyheavy X valley
(ft, fmax) decrease with increased Vce. Ccb is modulated by Ic.
2
3
4
5
6
7
8
0 2.5 5 7.5 10 12.5
Ccb/A
e (
fF/m
m2)
Je (mA/mm
2)
-0.2 V
0.0 V
0.2 V
Vcb
= 0.6 V
57
10-3
10-2
10-1
100
101
102
-0.3 -0.2 -0.1 0 0.1 0.2
J(m
A/m
m2)
Vbe
-
Fermi-Dirac
Highly degenerate
(Vbe
->>kT/q
Boltzmann
(-Vbe
)>>kT/q
Reduced gm at extreme current densities
Boltzmann
2
32
3
)(8
*
beV
mq
)/exp( kTqVbe
Fermi-Dirac
Highly Degenerate
Problem in InP, not silicon: silicon has larger electron effective mass, more valleys
High currents→ transconductance less than qI/kT → bandwidth decreases
130nm InP HBT
58
Bipolar Transistor Design eW
bcWcTbT
nbb DT 22t
satcc vT 2t
ELlength emitter
eex AR /contact
2
through-punchce,operatingce,max cesatc TVVAvI /)(,
contacts
contactsheet
612 AL
W
L
WR
e
bc
e
ebb
e
e
E W
L
L
PT ln1
cccb /TAC
58
59
Bipolar Transistor Design: Scaling eW
bcWcTbT
nbb DT 22t
satcc vT 2t
ELlength emitter cccb /TAC
eex AR /contact
2
through-punchce,operatingce,max cesatc TVVAvI /)(,
contacts
contactsheet
612 AL
W
L
WR
e
bc
e
ebb
e
e
E W
L
L
PT ln1
59
60
Energy-limited vs. field-limited breakdown
band-band tunneling: base bandgapimpact ionization: collector bandgap
60
61
Making faster bipolar transistors
to double the bandwidth: change
emitter & collector junction widths decrease 4:1
current density (mA/mm2) increase 4:1
current density (mA/mm) constant
collector depletion thickness decrease 2:1
base thickness decrease 1.4:1
emitter & base contact resistivities decrease 4:1
Narrow junctions.
Thin layers
High current density
Ultra low resistivity contacts
Teledyne: M. Urteaga et al: 2011 DRC
62
Refractory Contacts to In(Ga)As
Refractory: robust under high-current operation / Low penetration depth: ~ 1 nm / Performance sufficient for 32 nm /2.8 THz node.
10-10
10-9
10-8
10-7
10-6
10-5
1018
1019
1020
1021
N-InGaAs
B=0.6 eV
0.4 eV0.2 eV
0 eV
Electron Concentration, cm-3
Co
nta
ct
Re
sis
tiv
ity
,
cm
2
step-barrierLandauer
1018
1019
1020
1021
N-InAs
Electron Concentration, cm-3
0.2 eV
B=0.3 eV
step-barrier
B=0 eV
0.1 eV
Landauer
1018
1019
1020
1021
P-InGaAs
Hole Concentration, cm-3
B=0.8 eV
0.6 eV0.4 eV0.2 eV
step-barrierLandauer
32 nm (2.8THz) node requirements
Baraskar et al, Journal of Applied Physics, 2013
Why no ~2THz HBTs today ?Problem: reproducing these base contacts in full HBT process flow
62
63
THz HBTs: The key challenges
Obtaining good base contactsin HBT vs. in contact test structure(emitter contacts are fine)
1018
1019
1020
1021
P-InGaAs
10-10
10-9
10-8
10-7
10-6
10-5
Hole Concentration, cm-3
B=0.8 eV
0.6 eV0.4 eV0.2 eV
step-barrierLandauer
Co
nta
ct
Re
sis
tivit
y,
cm
2
3THz target
Baraskar et al, Journal of Applied Physics, 2013
RC parasitics along finger lengthmetal resistance, excess junction areas
64
THz HBTs: double base metal process
Blanket surface clean (UV O3 / HCl)strips organics, process residues, surface oxides
Blanket base metalno photoresist; no organic residuesRu refractory diffusion barrier2 nm Pt : penetrates residual oxides
Thick Ti/Au base pad metal liftoffthick metal→ low resistivity
Ro
de
et
al.,
IEEE
TED
, Au
g. 2
01
5
65
Reducing Emitter Length Effects
small base post undercut
large base post
bef
ore
afte
r
large base post undercut
small base post
65
Ro
de
et
al.,
IEEE
TED
, Au
g. 2
01
5large emitterend undercut
small emitterend undercut
66
Reducing Emitter Length Effects
before after
thicker Aubase metal
narrowercollectorjunction
66Rode et al., IEEE TED, Aug. 2015
67
InP HBTs: 1.07 THz @200nm, ?? @ 130nm
?
Rode et al., IEEE TED, Aug. 2015
68
130nm /1.1 THz InP HBT: ICs to 670 GHz614 GHz fundamentalVCO
340 GHz dynamic frequency divider
Vout
VEE VBB
Vtune
Vout
VEE VBB
Vtune
620 GHz, 20 dB gain amplifierM Seo, TSCIMS 2013
also: 670GHz amplifierJ. Hacker , TSCIMS 2013 (not shown)
M. Seo, TSC / UCSB
M. Seo, UCSB/TSCIMS 2010
204 GHz static frequency divider(ECL master-slave latch)
Z. Griffith, TSCCSIC 2010
300 GHz fundamentalPLLM. Seo, TSCIMS 2011
220 GHz 180 mWpower amplifier T. Reed, UCSBCSICS 2013
600 GHz IntegratedTransmitterPLL + MixerM. Seo TSC
Integrated 300/350GHz Receivers:LNA/Mixer/VCO
M. Seo TSC
81 GHz 470 mWpower amplifier H-C Park UCSBIMS 2014
69
Towards a 3 THz InP Bipolar Transistor
Extreme base doping→ low-resistivity contacts→ high fmax
Extreme base doping→ fast Auger (NP2) recombination→ low .
Solution: very strong base compositional grading→ high
1018
1019
1020
1021
P-InGaAs
10-10
10-9
10-8
10-7
10-6
10-5
Hole Concentration, cm-3
B=0.8 eV
0.6 eV0.4 eV0.2 eV
step-barrierLandauer
Co
nta
ct
Re
sis
tiv
ity
,
cm
2
70
1/2-THz SiGe HBTs
500 GHz fmax SiGe HBTs Heinemann et al. (IHP), 2010 IEDM
16-element multiplier array @ 500GHz (1 mW total output)U. Pfeiffer et. al. (Wuppertal / IHP) , 2014 ISSCC
71
Towards a 2 THz SiGe Bipolar Transistor
InP SiGe
emitter
junction width 64 18 nm
access resistivity 2 0.6 mm2
base
contact width 64 18 nm
contact resistivity 2.5 0.7 mm2
collector
thickness 53 15 nm
current density 36 125 mA/mm2
breakdown 2.75 1.3? V
ft 1000 1000 GHz
fmax 2000 2000 GHz
Similar scalingInP: 3:1 higher collector velocitySiGe: good contacts, buried oxides
Key distinction: Breakdown InP has:
thicker collector at same ft, wider collector bandgap
Key requirements:low resistivity Ohmic contacts note the high current densities
Assumes collector junction 3:1 wider than emitter.Assumes SiGe contacts no wider than junctions
72
InP Field-Effect Transistors
73
State of the art in InP HEMTs
Xiaobing Mei, et al, IEEE EDL, April 2015 (Northrop-Grumman)
First Demonstration of Amplification at 1 THz Using 25-nm InP High Electron Mobility Transistor Process
74
HEMTs: Key Device for Low Noise Figure
1
)(2
)(21
2
min
G
G
G
t
t
f
fRRRg
f
fRRRgF
igsm
igsm
Hand-derived modified Fukui Expression, fits CAD simulation extremely well.
0
2
4
6
8
10
1010
1011
1012
ft=300GHzft=600GHz
ft=1200GHzft=2400GHz
Nois
e f
igu
re,
dB
frequency, Hz
2:1 to 4:1 increase in ft → greatly improved noise @ 200-670 GHz.
Better range in sub-mm-wave systems; or use smaller power amps.
or enable yet higher-frequency systems
75
FET Design
g
DSWL
RRS/D
contact
gW width gate
gfgsgd WCC ,
)/( gchgm LvCg
)/( vWLR ggDS
)density state /well(2// 2
wellwell qTT
WLC
oxox
gg
chg
masstransport
1
capacitors threeabove the
between ratiodivision voltage2/1
v
76
FET Design: Scaling
g
DSWL
RRS/D
contact
gW width gate
gfgsgd WCC ,
)/( gchgm LvCg
)/( vWLR ggDS
)density state /well(2// 2
wellwell qTT
WLC
oxox
gg
chg
masstransport
1
capacitors threeabove the
between ratiodivision voltage2/1
v
77
FET Design: Scaling
g
DSWL
RRS/D
contact
gW width gate
gfgsgd WCC ,
)/( gchgm LvCg
)/( vWLR ggDS
)density state /well(2// 2
wellwell qTT
WLC
oxox
gg
chg
masstransport
1
capacitors threeabove the
between ratiodivision voltage2/1
v
2:1 2:1
constant 2:12:1
2:1 2:1
2:1 2:1 2:1
2:1
constant
constant
2:1 2:1
constant
2:1 2:1
4:1
constant
constant
78
FET Scaling Laws (these now broken)
fringing capacitance does not scale → linewidths scale as (1 / bandwidth )
78
FET parameter change
gate length decrease 2:1
current density (mA/mm) increase 2:1
transport mass constant
2DEG electron density increase 2:1
gate-channel capacitance density increase 2:1
dielectric equivalent thickness decrease 2:1
channel thickness decrease 2:1
channel state density increase 2:1
contact resistivities decrease 4:1
79
FET Scaling Laws (these now broken)
Gate dielectric can't be much further scaled.Not in CMOS VLSI, not in mm-wave HEMTs
gm/Wg (mS/mm) hard to increase→ Cend / gm prevents ft scaling.
Shorter gate lengths degrade electrostatics→ reduced gm /Gds → reduced fmax/ ft
FET parameter change
gate length decrease 2:1
current density (mA/mm) increase 2:1
transport mass constant
2DEG electron density increase 2:1
gate-channel capacitance density increase 2:1
dielectric equivalent thickness decrease 2:1
channel thickness decrease 2:1
channel state density increase 2:1
contact resistivities decrease 4:1
80
Why THz HEMTs no longer scale
HEMTs: gate barrier also lies under S/D contacts → high S/D access resistance
As gate length is scaled, gate barrier must be thinned for high gm, low Gds
HEMTs: High gate leakage when gate barrier is thinned→ cannot thin barrier
81
FET scaling laws; 2:1 higher bandwidth change
gate length decrease 2:1
current density (mA/mm), gm (mS/mm) increase 2:1
transport mass constant
gate-channel capacitance density increase 2:1
contact resistivities decrease 4:1
Towards at 2.5 THz HEMT
Xiaobing Mei, et al, IEEE EDL, April 2015 (Northrop-Grumman)
First Demonstration of Amplification at 1 THz Using 25-nm InP High Electron Mobility Transistor Process
Need thinner dielectrics, better contacts
82
Record III-V MOS
S. Lee et al., VLSI 2014
10 100
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
S. Lee, VLSI 2014
J. Lin, IEDM 2013
T. Kim, IEDM 2013
Intel, IEDM 2009
J. Gu, IEDM 2012
D. Kim, IEDM 2012
I on (
mA
/mm
)
Gate Length (nm)
VDS
= 0.5 V
Ioff
=100 nA/mm
-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.510
-7
10-6
10-5
10-4
10-3
10-2
10-1
100
101
gm (
mS
/mm
)
Cu
rren
t D
en
sit
y (
mA
/mm
)
Gate Bias (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0L
g = 25 nm
SS~ 72 mV/dec.
SS~ 77 mV/dec.
Ion= 500 mA/mm at Ioff
=100 nA/mm
and VD=0.5V
Vertical Spacer
N+ S/D
Lg~25 nm
recordfor III-V
= best UTB SOI silicon
83
Excellent III-V gate dielectrics
-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.710
-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
|Gate
Leakag
e|
(A/c
m2)
Cu
rren
t D
en
sit
y (
mA
/mm
)
Gate Bias (V)
10-5
10-4
10-3
10-2
10-1
100
101
SSmin
~ 61 mV/dec.
(at VDS
= 0.1 V)
SSmin
~ 63 mV/dec.
(at VDS
= 0.5 V)
Dot : Reverse Sweep
Solid: Forward Sweep
Lg = 1 mm
61 mV/dec Subthreshold swing at VDS=0.1 V
Negligible hysteresis
2.5nm ZrO2
1nm Al2O3
2.5nm InAs
V. Chobpattanna, S. StemmerFET data: S Lee, 2014 VLSI Symp.
84
III-V MOS @ Lg = ???
Image courtesy of S. Kraemer (UCSB)
Huang et al., 2015 DRC
85
Towards at 2.5 THz HEMT
-0.2 0.0 0.2 0.4 0.6 0.810
-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
100
101
SS ~ 107.5 mV
at VDS
=0.5 V
SS ~ 98.6 mV
at VDS
=0.1 V
VDS
= 0.1 to 0.7 V
0.2 V increment
I D,
|IG| (m
A/m
m)
VGS
(V)
C. Y. Huang et al., DRC 2015VLSI III-V MOS
THz III-V MOS
86
mm-wave measurements
87
• Agilent, Rhode/Schwarz network
analyzer,
• Oleson Microwave Lab or
Virginia Diodes
frequency extenders
• micro-coax wafer probes with
waveguide connections
GGB Industries,
Cascade Microtech
University of Virgina.
• Internal bias Tee’s in probes
• Mostly on-wafer calibration standards.
On-Wafer Network Analysis: 750+ GHz
88
On-Wafer Through-Reflect-Line (TRL) Calibration
Through
Reflect
Line
DeviceUnder Test
225um
reference plane
ΔL ΔL= 90 deg @center frequency./8<ΔL<3/8
DUT
open shortEither open or short needed.Standards need not be accurate."Open" must have G closer to that of open than that of short. Ports 1 & 2 must be symmetric.
Through line should be long for large probe separation.Minimizes probe-probe coupling.Measurements normalized to the line characteristic impedance.
225um
225um 225um
225um
225umPlease see also:http://www.ece.ucsb.edu/Faculty/rodwell/publications_and_presentations/publications/204vg.ppt
89
On-Wafer Line Reflect Linie Calibration
Extended Reference planes
transistors placed at center of long on-wafer line
LRL standards placed on wafer
large probe separation → probe coupling reduced
still should use the best-shielded probes available
Problem: substrate mode coupling
method will FAIL if lines couple to substrate modes
→ method works very poorly with CPW lines
need on wafer thin-film microstrip lines
CPW
90
Difficulties with >100 GHz On-Wafer Calibration
Data on two layouts of 65 nm MOSFET
2E
11
3E
11
4E
11
5E
11
6E
11
7E
11
8E
11
9E
11
1E
11
1E
12
1
2
3
4
5
6
7
8
9
0
10
freq, Hz
MS
GM
AG
_d
B_
ibm
MS
GM
AG
_d
B_
pfg
MA
G/M
SG
, d
B
2E
11
3E
11
4E
11
5E
11
6E
11
7E
11
8E
11
9E
11
1E
11
1E
12
2
4
6
8
10
12
14
16
18
0
20
freq, Hz
Um
_ib
m_
dB
Um
_p
fg_
dB
150 160 170 180 190140 200
-15
-10
-5
0
5
10
15
-20
20
freq, GHz
Um
_ib
mU
m_
pfg
U < 0 (!)
10*log10|U| (?)
"Un
ilate
ral g
ain
", d
B
"Un
ilate
ral g
ain
", lin
ea
r
Measured Y-parameters correlatereasonably with expected device model.
Small errors in measured 2-port parameters result in large changes in Unilateral gain and Rollet's stability factor; neither measurement is credible.
Y12 appears to be the key problem.
IC Sij measurements are fine.Transistor fmax measurements are hard.
12212211
2
1221
4 GGGG
YYU
( K<1 )
91
Packaging and
antennas
92
The Antenna Feed Loss Problem
array elements are many longoverall array can be very big→ high feed line losses
One solution:waveguide-fed arrays of slots
Use distributionamplifiers ?
Use to feed array tile:overall array needs steering
93
Using lenses to reduce feed loss
Lenses on individual array elements.
...or on the overall array.
Here the challenge is maintaining constant beamwidthover wide steering angles.
94
mm-wave interfaces: packaging
Wire-bonds:With care, >60GHz can be coupled over wire-bonds.Coupling of multiple lines remains problematic .
Flip-chip bondsStandard C4 bonds very capacitive; tuning OK @ 60GHz. Possibly higher.Option: more highly scaled bonds. Must contact vendors.Heat removal problematic in flip-chip ICs
Flexible polyimide interconnect substrateUsed in Cascade micotech multi-signal probes, in some 60GHz products.Ground integrity, low inductance mm-wave connections.Must identify vendor.
https://www.cmicro.com/products/probe-cards/the-technology/thin-film-technology/cascade-microtech-s-thin-film-technology
95
mm-wave interfaces: packaging
Through-silicon vias for RF grounding (TowerJazz, also IBM/GF)very low ground inductancelow losses, low crosstalk in mm-wave IC-package connections
96
mm-waveIC Design
97
Reactively-Tuned IC Design: Concepts
98
What's the most gain we can get ? Do we care ?
12212211
2
1221
12
4
match then ,0 untilfeedback lossless :gain Unilateral
GGGG
YYU
S
1
Match. feedback. No r. transistostablenally unconditio :gain available Maximum
2
12
21 KKS
SGma
factor).stability (Rollet 2
1 where
2112
2
21122211
2
22
2
11
SS
SSSSSSK
12
21
Match. Stabilize. feedback. No r. transistounstabley potentiall :gain stable Maximum
S
SGms
0
5
10
15
20
25
30
35
10 100 1000
Gain
s, d
B
Frequency, GHz
Gma
Common emitter
U
Gma
common base
Gma
common collector
Gmax,S
stability nalunconditiogiven gain feasibleHighest
)1(2)12(
match feedback, reactive lossless eappropriat
:gain snta'Singhakowi
2/12/1
max, UUUG S
A. Singhakowinta & A. R. Boothroyd, International Journal of Electronics, Volume 21, Issue 6, 1966, pages 549-560, DOI:10.1080/00207216608937931O. Momeni and E. Afshari, 2011 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, 2011, pp. 1-4, doi: 10.1109/CICC.2011.6055322
99
What's the most gain we can get ? Do we care ?
Low-noise amplifiers designed for low noise figure, fairly high IP3
Power amplifiersdesigned for high Psat, PAE, sufficiently low IM3
IF amplifiersdesigned for low noise figure, high IP3.
Practical amplifiers are rarely designed for highest gain.
Real-world relevance of Gma, Gms, Gmax,S is not clear.
Practical designs would benefit from new theoryQuantities similar to Gma, Gms, Gmax,S aboveBut under constraints of high-power or low-noise tuning.I know of no such published work.
100
RF-IC Design: Simple & Well-Known Procedures
1: (over)stabilize at the design frequency
guided by stability circles
3: Tune remaining port for maximum gain
2: Tune input for Fmin (LNAs) or output for Psat (PAs)
4: Add out-of-band stabilization.
There are many ways to tune port impedances: microstrip lines, MIM capacitors, transformers
Choice guided by tuning losses. No particular preferences.
0
5
10
15
20
25
30
10 100 1000
MS
G/M
AG
, dB
Frequency, GHz
Common base
Common Collector
Common emitter
UFor BJT's, MAG/MSG usually highest for common-base.
Common-base gain is however reduced by:
base (layout) inductance
emitter-collector layout capacitance.
100
101
Low-Noise Amplifier Design
Inductive emitter/source degenerationsimultaneous S11 and noise matchreduces gain, improves IP3
Additional in-band stabilization (output port) as neededInput tuning for FminOutput matchOut-of-band stabilization
Input
Output
3/0.133/0.13
1 mA 1 mA
Vb
VCC
102
parasitic C's and R's represented
by external elements...
Power Amplifier Design (Cripps method)
0
20
40
60
80
100
0 1 2 3 4 5 6 7 8
Curr
en
t, m
A
Vce
or Vds
(V)
breakdown
100 mW
200 mW
maxminmaxmax 81 IVVP For maximum saturated output power,
& maximum efficiency
device intrinsic output must see
optimum loadline set by:
breakdown, maximum current, maximum power density.
ammeter monitors intrinsic
junction current
without including
capacitive currents
...(Vcollector-Vemitter )
measures voltage
internal to series parasitic
resistances...
103
PAs with corporate combining
W-band InP HBT power amplifier - UCSB
34 GH InP HBT power amplifier - J. Hacker Teledyne
34 GH InP HBT power amplifier - J. Hacker Teledyne
104
Power amplifier design: combiners
Even-mode equivalent circuit
adjustedusly simultaneo , variablessharedby defined linessimilar all
:approach CAD
input.match toand reach toadjusted are parameters Line
added. be alsocan )capacitors ,(inductors elementsShunt
er. transformline-ansmissionsection tr-multi a :circuit equivalent The
,optlZ
105
mm-wave IC Interconnects
106
Transmission Lines
A pair of wires with regular spacing, dielectric loading along the length.
These have inductance per unit length and capacitance per unit length.
Forward and reverse waves propagate.
Reflections will occur if lines are not terminated in Zo
107
Transmission Lines for On-Wafer Wiring
H
W microstrip line
coplanar waveguide
0V 0V
0V
+V
0V
+V
geometry voltages currents
I
I
H
W
W+2S
I
0
I/2I/2
108
Skin loss
H
W
~W +2H
GHz 10 @ nm 640
100GHz, @ nm 200 :Gold
:/2depth Skin
m
HWWLRseries
2
1111/
:lengthunit per resistance Series
fZ
LRseries 2
/
distanceunit per n Attenuatio
0
)/2exp()exp()(
decay signal lExponentia
go zjzVzV
109
Lateral Modes (1)
2222
2222222
0
/
,...2 ,1 ,0for / and 0
:line-ssionon transmi *laterally* propagatecan Waves
2
form of waves:dielectricIn
Wnck
nWnkk
ckkkk
eeeeE
rz
xy
drzyx
zjkyjkxjktj zyx
110
Lateral Modes (2)
222
222
2222
/
: /2 if n propagatio Evanescent 2)
/
/2. ifn propagatio mode-Multi )1
/
cWn
We
Wnc
W
Wnck
rz
d
z
rz
d
rz
z
111
Lateral Modes (3)→ Junction Parasitics
parasiticsjunction modelmust
.wavelength-half ahan narrower tmuch bemust lines
:Lessons
.simulation neticelectromagor models,junction library ADS
parasiticsjunction modes evanescentin power Reactive
: /2 if n propagatio Evanescent
d
zWe z
112
Substrate Modes
.sfrequencielow at confined weakly ; 4 as confinedstrongly
mode;- tranversemetal topno withSubstrate
...23 , ,2 withmodes
surfaces metal bottom top, withSubstrate
T
E
h
d
ddd
113
Substrate Mode Coupling: Microstrip
4 when coupling mode strongVery
s.frequencie allat loss )radiation"(" coupling mode Nonzero
.in and in propagecan modes slab dielectric These
dh
zx
114
Substrate Mode Coupling: CPW
kz
loss" radiation"
frequencydimensions e transversline dB/mmloss, coupling mode
: substrate, thick Given
henstrongly w couple Modes
22
mode substrate,CPW,
d
yy
H
kk
115
Transmission lines: the problem
problems.major be will
radiation substrate and modes lateral then
substrates thick and lines wideuse weIf
large. be willlosseseffect -skin then
substrates thin and lines narrow use weIf
116
kz
III-V MIMIC Interconnects -- Classic Substrate Microstrip
Strong coupling when substrate approaches ~d / 4 thickness
H
W
Thick Substrate
→ low skin loss
Hr
skin 2/1
1
Zero ground
inductance
in package
a
Brass carrier andassembly ground
interconnectsubstrate
IC with backsideground plane & vias
near-zeroground-groundinductance
IC viaseliminateon-wafergroundloops
High via
inductance
12 pH for 100 mm substrate -- 7.5 @ 100 GHz
TM substrate
mode coupling
Line spacings must be
~3*(substrate thickness)
lines must be
widely spaced
ground vias must be
widely spaced
all factors require very thin substrates for >100 GHz ICs
→ lapping to ~50 mm substrate thickness typical for 100+ GHz
No ground plane
breaks in IC
117
kz
Parasitic slot mode
-V 0V +V
0V
Coplanar WaveguideNo ground vias
No need (???) to
thin substrate
Parasitic microstrip mode
+V +V +V
0V
Hard to ground IC
to package
substrate mode coupling
or substrate losses
ground plane breaks → loss of ground integrity
Repairing ground plane with ground straps is effective only in simple ICs
In more complex CPW ICs, ground plane rapidly vanishes
→ common-lead inductance → strong circuit-circuit coupling
40 Gb/s differential TWA modulator driver
note CPW lines, fragmented ground plane
35 GHz master-slave latch in CPW
note fragmented ground plane
175 GHz tuned amplifier in CPW
note fragmented ground plane
poor ground integrity
loss of impedance control
ground bounce
coupling, EMI, oscillation
III-V:
semi-insulating
substrate→ substrate
mode coupling
Silicon
conducting substrate
→ substrate
conductivity losses
118
If It Has Breaks, It Is Not A Ground Plane !
signal line
signal line
ground plane
line 1
“ground”
line 2
“ground”
common-lead inductance
coupling / EMI due to poor ground system integrity is common in high-frequency systems
whether on PC boards
...or on ICs.
119
No clean ground return ? → interconnects hard to model
35 GHz static divider
interconnects have no clear local ground return
interconnect inductance is non-local
interconnect inductance has no compact model
InP 8 GHz clock rate delta-sigma ADC
8 GHz clock-rate delta-sigma ADC
thin-film microstrip wiring
every interconnect can be modeled as microstrip
some interconnects are terminated in their Zo
some interconnects are not terminated
...but ALL are precisely modeled
120
fewer breaks in ground plane than CPW
III-V MIMIC Interconnects -- Thin-Film Microstrip
narrow line spacing → IC density
... but ground breaks at device placements
still have problem with package grounding
thin dielectrics → narrow lines
→ high line losses
→ low current capability
→ no high-Zo lines
H
W
HW
HZ
r
oo 2/1
~
...need to flip-chip bond
no substrate radiation, no substrate losses
InP 34 GHz PA
(Jon Hacker , Teledyne)
121
No breaks in ground plane
III-V MIMIC Interconnects -- Inverted Thin-Film Microstrip
narrow line spacing → IC density
... no ground breaks at device placements
still have problem with package grounding
thin dielectrics → narrow lines
→ high line losses
→ low current capability
→ no high-Zo lines
...need to flip-chip bond
Some substrate radiation / substrate losses
InP 150 GHz master-slave latch
InP 8 GHz clock rate delta-sigma ADC
122
VLSI mm-wave interconnects with ground integrity
negligible breaks in ground plane
narrow line spacing → IC density
negligible ground breaks @ device placements
still have problem with package grounding
thin dielectrics → narrow lines
→ high line losses
→ low current capability
→ no high-Zo lines
...need to flip-chip bond
no substrate radiation, no substrate losses
Also:
Ground plane at *intermediate level* permits
critical signal paths to cross supply lines, or other
interconnects without coupling.
(critical signal line is placed above ground,
other lines and supplies are placed below ground)
123
Modeling Interconnects, Passives in Tuned IC's
Interconnects are tuning elements
Narrow bandwidths→ precision is critical
Initial IC simulation uses CAD-systems' library of passive element models.
Second design cycle: 2.5-Dimensional electromagnetic simulation of:lines, junctions, stubs, capacitors, resistors, pads.
Third design cycle: 2.5-D simulation of entire IC wiring (if possible); otherwise, of large blocks (gain stages)
150-200 GHz HBT amplifier, Urteaga et al, IEEE JSSCC , Sept. 2003
185GHz HBT amplifier, Urteaga et al, IEEE IMS, May. 2001
1-180GHz HBT amplifier, Agarwal et al, IEEE Trans MTT , Dec.. 1998
124
ICs in Thin-Film (Not Inverted) Microstrip
Note breaks in ground plane at transistors, resistors, capacitors
125
ICs in Thin-Film (Not Inverted) Microstrip
Note breaks in ground plane at transistors, resistors, capacitors
126
ICs in Thin-Film Inverted Microstrip
100 GHz differential TASTIS Amp. 512nm InP HBT
127
Power supply problems
local resonances between bypass cap and supply interconnectsglobal LC standing-wave resonances on supply bus
Detuning of individual stagesCoupling, feedback via supply→ oscillation, loss of path isolation
128
Power supply problems
The supply impedance willdetune individual stages.
129
Power supply problems
Here, the supply is terminated by 50 Ohms through a bias T.This avoids resonances.
More generally, we must simulate systemfor wide range of external supply impedance.
Model the supply in all simulations."If it is on the IC, PCB, probe station, put it in the simulation."
130
Transmission-lines in 500+ GHz ICs
Inverted microstrip: the problem is ground via inductance
131
Transmission-lines in 500+ GHz ICs
Grounded CPW: lower ground inductance, metal 3 ground plane suppresses ground bounce
J. Hacker , Teledyne IMS 2013
132
Differential mm-wave stages
Common-emitterM. Seo, Teledyne
Common-baseM. Seo, 2013 IMS
Virtual ground→ avoids ground via inductance Avoids power-supply coupling Potential problems with common mode
133
mm-wave common-mode instability
In all amplifiers, stability must be ensured from DC-fmax.Differential & common-mode stability must be ensured from DC-fmax
Simple LNA inductive tuning is, for example, problematic
134
Pseudo-Differential Stages
No common-mode instability problem.Power-supply is virtual ground.No supply detuning of output networkImproved power-supply isolation (oscillation, unwanted signal coupling)
135
20+ GHz digital &
mixed-signal design
136
Modeling Interconnects: Digital & Mixed-Signal IC's
longer interconnects: lines terminated in Zo → no reflections.
Shorter interconnects: lines NOT terminated in Zo .But they are *still* transmission-lines.Ignore their effect at your peril !
vl
ZC
ZL
/
,/
,
0
0
t
t
t
If length << wavelength, or line delay<<risetime, short interconnects behave as lumped L and C.
Modeling: 2.5D, library Tline, or L-C
137
Design Flow: Digital & Mixed-Signal IC's
All interconnects: thin-film microstrip environment.Continuous ground on one plane.
2.5-D simulations run on representative lines.various widths, various planessame reference (ground) plane.
Simulation data manually fit to CAD line modeleffective substrate r , effective line-ground spacing.
Width, length, substrate of each line entered on CAD schematic.
rapid data entry, rapid simulation.
Resistors and capacitors:2.5-D simulation→ RLC fitRLC model used in simulation.
138
High Speed ECL Design
Followers associated with inputs, not outputsEmitters never drive long wires.(instability with capacitive load)
Double termination for least ringing, send or receive termination for moderate-length lines, high-Z loading saves power but kills speed.
Current mirror biasing is more compact.Mirror capacitance→ ringing, instability.Resistors provide follower damping.
139
High Speed ECL Design
Layout: short signal paths at gate centers, bias sources surround core.Inverted thin film microstrip wiring.
Example: 8:1 205 GHz static dividerin 256 nm InP HBT.
Key: transistors in on-stateoperate at Kirk limited-current.→ minimizes Ccb/Ic delay.
205 GHz divider, Griffith et al, IEEE CSIC, Oct. 2010
Key: transistors designed for minimumECL gate delay*, not peak (ft , fmax).*hand expression, charge-control analysis
140
Differential stages: schematic vs. floorplan
141
Example: 40 GS/s S/H clock buffer
Itail=6 mA
Itail=12 mA
142
Example: 40 GS/s S/H clock buffer
143
Example: 40 GS/s S/H clock buffer
144
20GHz Op-Amps for Linear 2 GHz Amplification
0
10
20
30
40
50
108
109
1010
1011
Fe
ed
ba
ck F
acto
r, d
B
Frequency, Hz
bandwidth loop
increasing
Even for 2 GHz operation,
loop bandwidths must 20-40 GHz.
need very fast transistors
physically small feedback loop;
bias components surround active core.
Griffith et al, IEEE IMS, June. 2011
input power, dBm
ou
tpu
t p
ow
er, d
Bm
linear response
2-tone intermodulation
increasing feedback
Reduce distortion withstrong negative feedback
R. Eden
145
86 GHz Power Amplifier
146
combiner-power
collectordrain/
Gain
11PAE
mm-Wave Power Amplifier: Challenges
needed: High power / High efficiency / Small die area ( low cost)
Extensive power combining Compact power-combining
Efficient power-combining Class E/D/F are poor @ mm-waveinsufficient fmax , high losses in harmonic terminations
Goal: efficient, compact mm-wave power-combiners
147
Parallel Power-Combining
Output power: POUT = N x V x I Parallel connection increases POUT
Load Impedance: ZOPT = V / (N x I) Parallel connection decreases Zopt
High POUT→ Low Zopt
Needs impedance transformation:lumped lines, Wilkinson, ...
High insertion loss Small bandwidthLarge die area
148
Series Power-Combining & Stacks
Parallel connections: Iout=N x I Series connections: Vout=N x V
Local voltage feedback:drives gates, sets voltage distribution
Design challenge:need uniform RF voltage distributionneed ~unity RF current gain per element
...needed for simultaneous compression of all FETs.
Output power: Pout=N2 x V x ILoad impedance: Zopt=V/ISmall or zero power-combining lossesSmall die areaHow do we drive the gates ?
Shifrin et al., 1992 IEEE-IMS; Rodwell et al., U.S. Patent 5,945,879, 1999; Pornpromlikit et al., 2011 CSICS
149
Ideal Tri-axial Line
Two separate transmission lines (m3-m2, m2-m1)
E, H fields between m3 and m1 perfectly shielded
150
Sub-λ/4 Baluns for Series Combining
Sub-/4 balun : stub→ inductivetunes transistor Cout !short lines→ low lossesshort lines → small die
Standard /4 balun : long lines→ high losses → large die
Balun combiner:2:1 series connectioneach source sees 25 → 4:1 increased Pout
Park et al., 2013 CSICS, 2014 IEEE-IMS
151
M1
HBTs
86 μm
186 μm
M1 thickness: 1 μm
Baluns in Real ICs
1) M1 as a GND 2) Slot-type transmission lines (M1-M2), AC short (2 pF MIM)
3) Microstrip line (M2-M3), E-field shielding NOT negligible
4) Sidewalls between M3-M1 (Faraday cages), /16 length
M1-M2 Capacitors M1-M2 Line
M2 91 μm42 μm
52 μm
124 μm
M1-M2 gap: 1 μm
M2 thickness: 1 μm
M2-M3 Line
12 μm
M2-M3 gap: 5 μm
M3 thickness: 3 μm
M2-M3 Sidewalls
10 μm
1) 2)
3) 4)
152
Two-Stage PA IC Test Results (86GHz)
Gain: 17.5 dBPSAT: >200 mW @ 3.0 VPAE: >30 %
14 16 18 20 22 240
5
10
15
20
25
30
35
PA
E, G
ain
(%
, d
B)
Pout (dBm)
PAE, Measured
Gain, Measured
Gain, Simulated
PAE, Simulated
Power density (power/die area)= 307 mW/mm2 (including RF pads)= 927 mW/mm2 (core area)
Large signal measurements
IC size: 825 x 820 um2
[H. Park et al, CSICS 2013]30% PAE W-Band InP Power Amplifiers Using Sub-Quarter-Wavelength Baluns for Series-Connected Power-Combining
153
4:1 series-connected 81GHz power amplifier
17 dB Gain470 mW Psat23% PAETeledyne 250 nm InP HBT2 stages, 1.0 mm2(incl pads)
Park et al., 2014 IEEE-IMS
154
IC example: 220 GHz
power amplifier
155
Millimeter-wave imaging
235 GHz video-rate synthetic aperture radar
10,000-pixel, 94GHz imaging array→ 10,000 elements
Go
lcuk: Tran
s MT
T, Au
g 20
14
1 transmitter, 1 receiver100,000 pixels20 Hz refresh rate5 cm resolution @ 1km50 Watt transmitter
(tube, solid-state driver)
Demonstrated:SiGe (UCSD/Rebeiz)
~1.3kW: 10,000 elementsLower-power designs:
InP, CMOS, SiGe(UCSB, UCSD, Virginia Poly.)
156
90 mW, 220 GHz Power Amplifier
Reed (UCSB) and Griffith (Teledyne): CSIC 2012Teledyne 250 nm InP HBT
-20
-10
0
10
20
210 220 230 240 250 260
Am
plif
ier
ga
ins (
dB
)
frequency (GHz)
3dB bandwidth = 240GHz
S21,mid-band
= 15.4dB
S11
S22
8-cell, 2-stage PA
PDC
= 4.46W
0
20
40
60
80
100
0 2 4 6 8 10 12 14
Po
ut , m
W
Pin
, mW8-cell, 2-stage PA PDC
= 4.46W
88mW Pout
84mW
80mW
72mW
62mW
42mW
90mW
220GHz operation
active area, 1.02 x 0.85 mmdie: 2.42 x 1.22 mm
156
157
214 GHz InP HBT Power Amplifier UCSB/Teledyne
Gain: 25dB S21 Gain at 220GHz
Saturated output power: 164mW at 214GHz
Output Power Density:0.43 W/mm
PAE: 2.4%
Technology: 250 nm InP HBT
(no die photo) 2.5mm x 2.1 mm
Reed et al, 2014 CSICS http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6659187&tag=1
158
214 GHz 180mW Power Amplifier (330 mW design)
2.3 mm x 2.5 mm
Reed, Griffith CSICS2013Teledyne 250 nm InP HBT
158Reed et al, 2014 CSICS http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6659187&tag=1
159
220 GHz power amplifiers; 256nm InP HBT
160
ICs in Thin-Film (Not Inverted) Microstrip
Note breaks in ground plane at transistors, resistors, capacitors
161
220 GHz measurement
162
Power combined modules
Slide from Z. Griffith IMS 2016 Presentation
163
mm-Wave power
164
Teledyne: 1.9 mW, 585 GHz Power Amplifier
Output Power
•12-Stage Common-base
•2.8 dBm Psat
•>20 dB gain up to 620 GHz
What limits output power in sub-mm-wave amplifiers ?
S-parameters
M. Seo et al., Teledyne Scientific: IMS2013
165
Sub-mm-wave PAs: need more current !
common-base HBT
base
emitter
collector
groundplane
HBTs with microstrip combiner
0
1
2
3
0 1 2 3 4 5
Je (
mA
/mm
)
Vce
(V)
3 mm max emitter length (> 1 THz fmax)2 mA/mm max current densityImax= 6 mA
Maximum 3 Volt p-p output
Load: 3V/6mA= 500
Combiner cannot provide 500 loading
166
Multi-finger HBTs: more current, lower fmax
More current→ lower cell load resistance
one-finger common-base HBT
two-finger power cell
four-finger power cell: parasitics
base
emitter
collector
groundplane
base
emitter
collector
base
emitter
collector
unequal emitter inductances
emitter-collector capacitance
Reduced fmax, reduced RF gain:common-lead inductance→ Z12
feedback capacitance→ Y12
phase imbalance between fingers.
Worse at higher frequencies:less tolerant of cell parasiticsless current per cellhigher required load resistanceCan optimum load be reached ?
167
Sub-mm-wave transistors: need more current
0
1
2
3
0 1 2 3 4 5
Je (
mA
/mm
)
Vce
(V)
InP HBTs:thinner collector→ more currenthotter→ improve heat-sinkingor: longer emitters→ thicker base metal
GaN HEMTs: much higher voltage100+ GHz: large multi-finger FETs not feasibleNeed high current to exploit high voltage.
Need more mA/mm or longer fingers
Example: 2mA/mm, 100 mm max gate width, 50 Volts200mA maximum current50 Volts/200mA= 250 load→ unrealizable.
168
50-500GHz Wireless
169
IC example: 150 GHz
CMOS amplifier
170
3-stage 150-GHz Amplifier; IBM 65 nm CMOS
-20
-15
-10
-5
0
5
10
140 150 160 170 180 190 200
Frequency (GHz)
S21(meas)
S21(sim)
S21 (measured using power sensor)
S11 (meas)
S11 (sim)
S22 (meas)
S22 (sim)
Frequency (GHz)
S21
S22
S11 (meas)
S11 (sim)
-20
-15
-10
-5
0
5
10
140 150 160 170 180 190 200
Frequency (GHz)
S21(meas)
S21(sim)
S21 (measured using power sensor)
S11 (meas)
S11 (sim)
S22 (meas)
S22 (sim)
140 160 180Frequency (GHz)
K-factor
0
1
2
3
140 160 180Frequency (GHz)
Stability
factor (K)
140 160 180Frequency (GHz)
K-factor
0
1
2
3
140 160 180Frequency (GHz)
Stability
factor (K)
S-p
ara
mete
r (d
B)
-15
-10
-5
0
5
10
-20 -15 -10 -5 0 5
Input power (dBm)
Ou
tpu
t p
ow
er
(dB
m)
0
5
10
15
20
25
Po
wer
Ad
ded
Eff
icie
ncy (
%)
153 GHz
153 GHz
158.4 GHz
158.4 GHz
153 GHz
158.4 GHz
Outp
ut po
we
r (d
Bm
), G
ain
(d
B)
Input power (dBm)
Po
we
r A
dde
d E
ffic
iency (
%)
PAE
Pout
Gain
-15
-10
-5
0
5
10
-20 -15 -10 -5 0 5
Input power (dBm)
Ou
tpu
t p
ow
er (
dB
m)
0
5
10
15
20
25P
ow
er A
dd
ed E
ffic
ien
cy (
%)
153 GHz
153 GHz
158.4 GHz
158.4 GHz
153 GHz
158.4 GHz
153.0GHz
158.4GHz
-15
-10
-5
0
5
10
-20 -15 -10 -5 0 5
Input power (dBm)
Ou
tpu
t p
ow
er (
dB
m)
0
5
10
15
20
25P
ow
er A
dd
ed E
ffic
ien
cy (
%)
153 GHz
153 GHz
158.4 GHz
158.4 GHz
153 GHz
158.4 GHz
153.0GHz
158.4GHz
Acknowledgement:IBM
M. Seo, B. Jagannathan, J. Pekarik, M. Rodwell, IEEE JSSCC, Dec. 2009
Dummy-prefilled microstrip lines
171
IC example: 140 GHz
spatial multiplexing
172
Massive Spatial Multiplexing
Two applications:
Spatially multiplexed networksmultiple independent beamscarrying independent data→ spectral re-use for massive capacity
mm-wave line-of-sight MIMOspatial multiplexingfor increased capacity
These use similar signal processing hardware
173
Arrays for single-beam links
Single-beam arrays: steerable, high gain, for mm-wave links.
Simple hardware: one RF port for IC, one phase-shifter for each element
174
Multi-beam links: hardware design
multiple independent beamseach carrying different dataeach independently aimed# beams = # array elements
Hardware: multi-beam phased array ICs
175
Multi-Beam Links: Analog Beamformer Matrix
I/Q matrix at baseband
varying coefficients→ track/aim beams
Designs: March tapeout GF (ex IBM) 45nm SOI16 beams: 32 x 32 matrix1024 matrix elementsarea: 2.25 mm2
power: 2.25W bandwidth: ~5 GHz ?aggregate ~160 Gb/s.
Also for tapeout140 GHz front-ends for these
176
Multi-Beam Links: Analog Beamformer Matrix
177
Multi-Beam Links: Analog Beamformer Matrix
I/Q matrix at baseband
varying coefficients→ track/aim beams
Designs: March tapeout GF (ex IBM) 45nm SOI16 beams: 32 x 32 matrix1024 matrix elementsarea: 2.25 mm2
power: 2.25 W bandwidth: ~5 GHz ?aggregate ~160 Gb/s.
Also for tapeout140 GHz front-ends for theselater: RF for 38GHz, 60 GHz
array
cell
switched gm block
178
0
90°
0
90°
0
90°
0
90°
RF Ch.1
RF Ch.2
RF Ch.3
RF Ch.4
LO
140 GHz MIMO receiver front-end
LO
RF
RF
RF
RF
Ch.1
Ch.2
Ch.3
Ch.4
Size: 1075 x 1760 um2
RF
IF_Q IF_Q
IF_I IF_I
90° hybrid
Power div.
Single-channel layout
179
Single-ended vs differential
Single-ended Differential
Gain - -
Power consumption Low High
Design complexity LowHigh
(Balun is required)
Isolation (S12) & Stability LowHigh
(Cgd cancellation)
Power supply (VDD & VSS)
immunityPoor Good
Power supply immunity is critical differential structure
180
Low noise amplifier
LNA design:
3-stage differential CS amplifier
Cgd cancellation
Transformers for matching networks and sing.-to-diff.
24 x 1um
181
SGF vs PGF
0.0 0.1 0.2 0.3 0.4 0.50
1
2
3
4
5
6
7
8
PGF
SGF
Current Density (uA/um)
MA
G (
dB
)
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
No
ise
Fig
ure
(d
B)
Total width = 1um x 20 fingers
0.0 0.1 0.2 0.3 0.4 0.50
1
2
3
4
5
6
7
8
PGF
SGF
Current Density (uA/um)
MA
G (
dB
)
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
Total width = 1um x 30 fingers
No
ise F
igu
re (
dB
)
Simulation results includes BSIM model and PEX results
(PEX capacitance and resistance due to PC, CA and M1)
*PC: poly, CA: connection between poly and metal 1, M1: metal 1
182
FET footprint
Series gate feeding Parallel gate feeding
Gate
Gate
(M1)
Gate
(M2)
Drain
(M2)
Source
(M1)
Drain
(M2)
Source
(M2)
183
FET footprint - PGF
PGF
- PGF and SGF have similar performances (MSG, NF)
- SGF is hard to extract the inductance of the gate
feeding line
- Source can directly connect to ground
(M1 is the ground plane)
SGF
Gate
Gate
184
FET modeling
Parallel Gate Feeding
Gate
(M2)
Drain
(M2)
Source
(M1)
PEX
CA, PC, M1 parasitic
(capacitance, resistance)
EM Simulation
M2 – LB interconnection parasitic
(capacitance, resistance, inductance)
BSIM
Transistor core
LB
M1
BEOL: M1-M2-M3-C1-C2-B1-B2-B3-UA-UB-LB
Transistor modeling:
BSIM + PEX + EM simulation
(BSIM & PEX from the foundry)
185
FET differential pair layout
Cgd cancellation
: MOM Cap
M1 ground plane
Cgd cancellation – better isolation & gain
Gate+(LB)
Gate-(LB)
Drain+(LB)
Drain-(LB)
BEOL: M1-M2-M3-C1-C2-B1-B2-B3-UA-UB-LB
186
Matching networks
VDD: M2-M3-C1-C2
Gate bias: M2
UB-LB
M1 ground plane
For matching:
Optimize transistor size & transformer diameter
Center-tapped transformer for DC biasing (VDD, VGS)
BEOL: M1-M2-M3-C1-C2-B1-B2-B3-UA-UB-LB
187
LNA layout
Size: 315 x 170 um2
188
Gain & NF
100 120 140 160 180-20
-10
0
10
20
30
Frequency (GHz)
Gain
& N
ois
e F
igu
re (
dB
)
-20
-10
0
10
20
30
Input
Output
GainNF
5.2 dB @ 140 GHz
In/o
utp
ut
Retu
rn L
oss (
dB
)
19.2 dB @ 140 GHz
Gain 19.2 dB (peak gain 20 dB @ 145 GHz)
NF: 5.2 dB
189
Linearity
IIP3: -5.84 dBm, Input P1dB: -13.87 dBm
-40 -30 -20 -10 0-20
-10
0
10
20
30
Gain
Output Power
Gain = 19.07 dB
Ou
tpu
t P
ow
er
(dB
m),
Ga
in (
dB
)
Input Power (dBm)
Input P1dB = -13.87 dBm
-40 -30 -20 -10 0-80
-60
-40
-20
0
20
Ou
tpu
t P
ow
er
(dB
m)
Input Power (dBm)
IIP3 = -5.84 dBm
140 GHz with 10 MHz spacing
190
Summary - LNA
Gain 19.2 dB (Peak 20 dB @ 145 GHz)
NF 5.2 dB
IIP3 -5.8 dBm
Input P1dB -13.87 dBm
Power consumption 41 mA @ 1 V
Size 315 x 170 um2
191
RF
RF
LO_I
LO_Q
IF_I
IF_Q
Down-conversion mixer
Mixer design:
Single-balanced active I/Q mixerCS buffer for testing (buffer gain ≈ 1)
Size: 140 x 230 um2
LO_I
LO_Q
I/Q mixer
192
Mixer core layout
RF input
(LB)
LO +(LB)
LO –
(LB)
IF output (C1)
M1 ground plane
FET
BEOL: M1-M2-M3-C1-C2-B1-B2-B3-UA-UB-LB
193
0
90°
0
90°
0
90°
0
90°
RF Ch.1
RF Ch.2
RF Ch.3
RF Ch.4
LO
LO distribution network:
Wilkinson power divider
Quadrature hybrid (I/Q generation)
Four-channel receiver
(12 dBm)
194
Layout
LO
RF
RF
RF
RF
Ch.1
Ch.2
Ch.3
Ch.4
Size: 1075 x 1760 um2
RF
IF_Q IF_Q
IF_I IF_I
90° hybrid
Power div.
Single-channel layout
Wilkinson power divider
195
Conversion gain & NF (single-channel)
100000 1000000 1E7 1E8 1E94
6
8
10
12
14
16
18
20
22
24
NF
dsb
(d
B)
Frequency (GHz)
NF dsb = 5.8 dB
1 2 3 4 5 6 7 8 9 1010
11
12
13
14
15
16
17
18
Co
nv
ers
ion
Ga
in (
dB
)
IF Frequency (GHz)
LO @ 139 GHz
Gain 17 dB (single-channel IF_I output)
NF : 5.8 dB (dsb)
196
Linearity (single-channel)
-40 -30 -20 -10 0-30
-20
-10
0
10
20
30
Ou
tpu
t P
ow
er
(dB
m),
Ga
in (
dB
)
Input Power (dBm)
Gain = 17.05 dB
Gain
Output Power
Input P1dB = -18.74 dBm
-50 -40 -30 -20 -10 0-120
-100
-80
-60
-40
-20
0
20RF @ 140 GHz with 10 MHz spacing
LO @ 139 GHz
Ou
tpu
t P
ow
er
(dB
m)
Input Power (dBm)
IIP3= -10.7 dBm
IIP3: -10.7 dBm, Input P1dB: -18.74 dBm
197
Summary - receiver
Gain 17 dB (Single-channel IF_I output)
NF 5.8 dB
IIP3 -10. 7 dBm
Input P1dB -18.7 dBm
Power consumption
41 mA (LNA) + 2 mA (I/Q mixer)
+ 14 mA (IF-I/Q buffers)
@ 1 V (Single-channel)
Size 1075 x 1760 um2
198
IC example: 94 GHz
low-power-array
199
Millimeter-wave imaging
10,000-pixel, 94GHz imaging array→ 10,000 elements
Go
lcuk: Tran
s MT
T, Au
g 20
14
Demonstrated:SiGe (UCSD/Rebeiz)
~1.3kW: 10,000 elementsLower-power designs:
InP, CMOS, SiGe(UCSB, UCSD, Virginia Poly.)
System concept: Bruce Wallace DARPA. 1st ICs (SiGe) Rebeiz, UCSD.
200
Millimeter-wave imaging
10,000-pixel, 94GHz imaging array→ 10,000 elements
Go
lcuk: Tran
s MT
T, Au
g 20
14
Demonstrated:SiGe (UCSD/Rebeiz)
~1.3kW: 10,000 elementsLower-power designs:
InP, CMOS, SiGe(UCSB, UCSD, Virginia Poly.)
100 pixel × 100 pixel image→ 10,000 array elements.~130 mW DC power per element → 1.3 kW system power requirement.Problem: required size and weight of heat sink.
201
94 GHz low-power IC design: transistors
At 1mW dissipation, ~17 dB gain is feasible→ low power ICs.
Teledyne: 130nm InP HBT: high-fmax bias
Teledyne: M. Urteaga et al: 2011 DRC
0
5
10
15
20
25
30
1010
1011
1012
Gain
s (
dB
)
Frequency (Hz)
MAG/MSG; common emitter MAG/MSG;
common base
Mason's unilateral gain Ic=1 mA
Vce
=1.0 V
94 GHz
10.4dB
16.8 dB
Teledyne: 130nm InP HBT: low-power bias
130nm × 3 mm emitter
202
94 GHz low-power IC design: transistors
Ccbi
Ccbx
Rbe
RbbB C
E
Rex
Rc
Vbe
CjeCbe,diff =gmt f
gmVbee-jtc
CgdRg
Ri
Cgs Vg’s’
gmVg’s’ Gds
Rs
G
D
S
Csb
Cdb
BJTs FETs
ions)considerat IP3 , (ignores
BJTs use should ICs wave-mmpower -low
mV. 300/~ :FETs
.mV 26/ :BJTs
/1)/1)(/()/()( :BJTs& FETs
possible matching-impedance make tosized bemust or transist:RF
1
//
sat
Sm
Em
mmmbegsBBgin
P
Ig
Ig
ggjffgCjRZ
t
203
Phased array
IC can transmit on vertical (V) or horizontal (H) polarizations (one at a time)IC can receive on vertical (V) and horizontal (H) polarizations (simultaneously)Each mode has phase-shifter, VGA. Signal distribution on backplane.InP IC: requires low-speed CMOS digital control IC
1770 um x 1550 um
Phase Shifter
VGA
PA_V
PA_H
LNA Phase Shifter
VGA
V_Antenna
H_Antenna
Rx_V Output/ Tx Inpout
Rx_H Output
V/H Switch
InputT/Rx Switch
OutputT/Rx Switch
(Virtual)
204
Low-power, low-voltage mm-wave design
Extensive use of current mirrors, translinear techniques
RFin
Block3
Block2
RFin1
RFout1, in2
RFout2
RFout
Block1
on/off
on/off
Input
Output
RFin
RFout1 RFout2
on/off Off/on
Gain & switching Low-power T/R switching
VGA / switch Multiplier→ mixer, modulator,phase-shifter
205
Low-power, low-voltage mm-wave design
Antenna switch LNA
backplane T/R switch PA & V/H switch
RxTx
Antenna
Cbypass
CDC
VCC
~ λ/4 Lload
Rx on/off
Rleak1Rleak2
Tx on/off
Input
Output
3/0.13
3/0.131 mA 1 mA
VCCRx on/off
~ 1 mA
SPDT SW bias
Rx VGA 1st bias
3/0.13
Rx bias circuit
Rx output/Tx input
Rx
Tx
50
Ω @
Rx o
ff
VGA 2nd stage
Tx VGA
OutputT/Rx Switch
Rx VGA
Tx on/off
ICtrlICtrlb
50 Ω @ Tx off
Input
VGA 1st stage
6/0.13
VOnHOnHOutput
Input
12/0.13
VOutput
3/0.133/0.13
VCC
206
Phase-shifter and control circuits
balun
λ/4
de
lay
Input Output
Ib
I
I
Qb
Q Q
2WW 4W
Q
ExternalCurrent DAC
I
6/0.13
2/0.13IC
trl
QC
trl
VCC
Sub-quarter wavelength balun
λ/4
de
lay
Input Output
IbCtrlICtrl ICtrl
QbCtrlQCtrl QCtrl
Mat
chin
g
Ibias+Qbias
= 3.2 mA
760 um x 640 um
207
Phase-shifter measurement results (1 V)
Power consumption: 4.2 mA @ 1 V
-300
-200
-100
0
100
200
90 92 94 96 98 100
Ph
as
e (
De
gre
e)
Frequency (GHz)
1 V
-20
-15
-10
-5
0
-40
-30
-20
-10
0
10
20
75 80 85 90 95 100 105 110
S(2,1), 1.5 VS(2,1), 1 VS(1,1), 1.5 V
S(2,2), 1.5 VS(1,1), 1 V
S(2,2), 1 V
S(2
,1)
(dB
)
S(1
,1), S
(2,2
) (dB
)
Frequency (GHz)
-10
-9
-8
-7
-6
-5
-4
-3
-2
90 92 94 96 98 100
Gain
(d
B)
Frequency (GHz)
1 V
-20
-15
-10
-5
0
-40
-30
-20
-10
0
10
20
75 80 85 90 95 100 105 110
S(2,1), MeasS(2,1), SimS(1,1), Meas
S(2,2), MeasS(1,1), Sim
S(2,2), Sim
S(2
,1)
(dB
)
S(1
,1), S
(2,2
) (dB
)
Frequency (GHz)
1 V
ICtrl
= 0 mA, QCtrl
= 0 mA
208
Low-noise amplifier
- Noise matching for input- Conjugate matching for inter-stage- Gain matching for output- Power consumption: 2 mA @ 1.5 V
660 um x 510 um
Input
Output
3/0.133/0.13
1 mA 1 mA
Vb
VCC
209
LNA Measurement results (1 V)
Power consumption: 2.0 mA @ 1 VGain: 16.3 dB @ 94 GHz (peak gain)
8
10
12
14
16
18
-25
-20
-15
-10
-5
0
-40 -35 -30 -25 -20 -15 -10
Gain, MeasGain, SimPout, MeasPout, Sim
Gain
(d
B)
Ou
tpu
t Po
we
r (dB
m)
Input Power (dBm)
1 V
-20
-15
-10
-5
0
5
10
15
20
-30
-20
-10
0
10
20
75 80 85 90 95 100 105 110
S(2,1), MeasS(2,1), SimS(1,1), Meas
S(2,2), MeasS(1,1), Sim
S(2,2), Sim
S(2
,1)
(dB
)
S(1
,1), S
(2,2
) (dB
)
Frequency (GHz)
1 V
-20
-15
-10
-5
0
5
10
15
20
-40
-30
-20
-10
0
10
20
75 80 85 90 95 100 105 110
S(2,1), 1.5 VS(2,1), 1 VS(1,1), 1.5 V
S(2,2), 1.5 VS(1,1), 1 V
S(2,2), 1 V
S(2
,1)
(dB
)
S(1
,1), S
(2,2
) (dB
)
Frequency (GHz)
2
3
4
5
6
7
8
9
10
8
10
12
14
16
18
90 91 92 93 94 95 96 97 98
NF, MeasNF, Sim
S(2,1), PNAS(2,1), NFAN
ois
e F
igu
re (
dB
)
S(2
,1), (d
B)
Frequency (GHz)
1 V
210
Noise measurement setup
Calibration
Measurement
-1 dB
-1 dB
Loss before the DUT: compensated using the NFA’s internal functiontherefore, measured gain should be subtracted by -1 dB
Noise source
Mixer(LO @ 94 GHz)
W-bandAmp.
Noise Source(NSI-9095W)
Mixer(LO @ 94 GHz)
NFA(N8972A)
W-bandAmplifier
Noise Source(NSI-9095W)
Mixer(LO @ 94 GHz)
NFA(N8972A)DUT
W-bandAmplifier
211
Transceiver measurement results
-30
-20
-10
0
10
20
30
-30
-20
-10
0
10
20
30
75 80 85 90 95 100 105 110
S(2,1), VS(2,1), HS(1,1), V
S(2,2), VS(1,1), H
S(2,2), H
S(2
,1)
(dB
)
S(1
,1), S
(2,2
) (dB
)
Frequency (GHz)
Rx, 1 V
10
15
20
25
-15
-10
-5
0
-40 -35 -30 -25 -20 -15
Gain, VGain, H
Pout, VPout, H
Ga
in (
dB
)
Ou
tpu
t Po
wer (d
Bm
)
Input Power (dBm)
Rx, 1 V
-30
-20
-10
0
10
20
30
-30
-20
-10
0
10
20
30
75 80 85 90 95 100 105 110
S(2,1), VS(2,1), HS(1,1), V
S(2,2), VS(1,1), H
S(2,2), H
S(2
,1)
(dB
)
S(1
,1), S
(2,2
) (dB
)
Frequency (GHz)
Tx, 1.5 V
14
16
18
20
22
24
-15
-10
-5
0
5
-40 -35 -30 -25 -20 -15 -10
Gain, VGain, HPout, VPout, H
Gain
(d
B)
Ou
tpu
t Po
wer (d
Bm
)
Input Power (dBm)
Tx, 1.5 V
212
Receiver noise
6
7
8
9
10
11
12
16
17
18
19
20
21
22
23
24
93 93.5 94 94.5 95 95.5 96
NF, MeasNF, Sim
S(2,1), PNAS(2,1), NFAN
ois
e F
igu
re (
dB
)S
(2,1
), (dB
)
Frequency (GHz)
1 V
213
94 GHz transceiver: performance summary
@Vcc=1.5V @Vcc=1.0V
Power Amplifier
+V/H SW
Output Power P3dB dBm 6.9 3.5
Power Gain @P3dB dB 14 14
PAE % 17 12.7
Pdiss @ P3dB mW 27.2 16.9
Pdiss (small-signal) mW 22.5 16.4
Pdiss (core exclude bias ckt) mW 17.55 11.45
Size (exclude Pads) µm 475*475 475*475
VGA
Power Gain (Rx/Tx) dB 12.5/10.9 13.4/11.5
NF (max gain) dB 4.8/7.8 4.6/7.7
NF (max gain - 6dB) dB 7.1/9.4 6.6/9.3
Input P1dB dBm -12.4/-9.6 -15.9/-15
OIP3 dBm 6.7/7.6 -1.8/-3
Pdiss mW 9 6.4
Pdiss (core exclude bias ckt) mW 6.9 4.6
Size (exclude Pads) µm 530*900 530*900
LNA
Power Gain dB 15.1 16.3
NF dBm 5 5
Input P1dB dBm -21.9 -24.5
OIP3 dBm -1.7 -3
Pdiss mW 4.95 3.95
Pdiss (core exclude bias ckt) mW 3.5 2
Size (exclude Pads) µm 480*280 480*280
Phase Shifter
Power Gain (Rx/Tx) dB -5±1.5 -5±1.5
NF dB 14.9 14.6
Input P1dB dBm 9 6
OIP3 dB 10.9 2
Pdiss mW 6.5 4.2
Pdiss (core exclude bias ckt) mW 6.5 4.2
Size (exclude Pads) µm 660*340 660*340
SPDTAntennaT/Rx SW
Loss dB 2 1.8
Isolation dB 19.5 18.5
P1dB dBm 14 14
Pdiss mW 6.8 4.8
Pdiss (core exclude bias ckt) mW 4.8 2.8
Size (exclude Pads) µm 200*680 200*680
Rx Channel
Power Gain dB 21 22.7
NF dB 8.5 8
Fractional BW % 7.6 7.5
Input P1dB dBm -22.9 -27.9
IIP3 dBm -16.3 -24.3
Pdiss mW 19.2 12.9
Pdiss (core exclude bias ckt) mW 17.25 11
Tx Channel
Power Gain dB 22.2 22.4
Pout (P3dB) dBm 3.8 0.1
Fractional BW % 6.7 6.7
Output P1dB dBm 0.8 -3.4
OIP3 dBm 10 3.8
Pdiss mW 39.7 28.7
Pdiss (core exclude bias ckt) mW 31.5 20.5Simulation
Phase Shifter
VGA
PA_V
PA_H
LNA Phase Shifter
VGA
V_Antenna
H_Antenna
Rx_V Output/ Tx Inpout
Rx_H Output
V/H Switch
InputT/Rx Switch
OutputT/Rx Switch
(Virtual)
214
IC example: 1-25 GHz
dual-conversionreceiver
215
Dual Conversion: Wide Tuning
Low (2GHz) IF→ image & LO responses close to RF carrier
High (100GHz) IF→ image & LO responses far from RF carrier
Dual conversion: a standard approach in RF receivers.
Modern THz IC processes→ 100 GHz IF easily feasible → Image-response-free 1-50 GHz receiver
216
W-band Waveguide Filters
1 GHz filter bandwidth is easy; 100 MHz should be just feasible.
our effort: design the ICs, purchase the filter.
217
Choice of Frequency Plan
Distribution Statement
LO below IF:triplers have residual output @ 2fin
→ maximum 1.5:1 tuning ratio→ maximum 67-100 GHz LO tuning~1-33 GHz RF tuningNeed 67-100GHz LO driver PApresent designs (lower-risk)
217
LO above IF:maximum 100-150 GHz LO tuning~1-50 GHz RF tuningNeed 100-150GHz LO driver PAAt ~200-300mW output powerhigher-risk.
218
Full receiver configuration: 2 chips to ease testing
219
Receiver: down-conversion block
LO Driver(> 20 dBm)
Ground Plane: MET3
VEE: -3.3 V
Ground Plane: MET1
VDD: 2.0 V
100 GHz
11.1 GHz
Microstrip line filter
x3
x3Multiplier(ECL_Gate)
LC filter
Down-mixer
Buffer
Multiplier(ECL_Gate)
IFA
Matching& Balun
Mu
ltiplie
r Ch
ain
Gro
un
d P
lan
eM
ET3
M
ET1
5240 um x 1160 um
220
Receiver: up-conversion block
LNA
LO Driver(> 20 dBm)
Gro
un
d P
lan
eM
ET3
M
ET1
Ground Plane: MET3
VEE: -3.3 V
Ground Plane: MET1
VDD: 2.0 VM
ult
iplie
r C
ha
in
70-100 GHz
7.88-11.1 GHz
0.1 GHz-20 GHz
Microstrip line filter
x3
x3Multiplier(ECL_Gate)
LC filter
Up-mixer
Buffer
Multiplier(ECL_Gate)
Matching& Balun
4300 um x 1160 um
1 GHz
-25 GHz
221
Mixer
IF
RF
LO
D1
D2
D3
D4
CA
B D
MET3 MET2 MET1
B1
B2 B3
B4
Diode mixer:High dynamic range.base-collector diodes: no saturationseries-connected→ high IP3requires high LO drive power
Baluns:tri-plane designsome are sub-quarter-wavelength
222
9:1 LO Multiplier
ECL_gate1
x3 x3
ECL_gate3Filter1
Ground Plane: MET3VEE: -3.3 V
Ground Plane: MET1VDD: 2.0 V
Filter2ECL_gate2 Amp.
2500 um x 1160 um
simulation
measured6
7
8
9
10
11
12
75 80 85 90 95 100 105 110
Ou
tpu
t P
ow
er
(GH
z)
Multiplier Output Frequency (GHz)
223
Differential LO Driver Amplifier: 67-100GHz
Ultra-broadband LO driverlimited by 67GHz substrate mode ?data shows otherwise.
High Powerrequired by high-IP3 mixer>100mW over full bandwidth> 250mW at most frequencies.
Topology4:1 series connected by balunscompact, efficient, ultra-broadband2 cascaded stages
224
Differential LO Driver Amplifier: 67-100GHz
5
10
15
20
25
20 40 60 80 100 120
S2
1,
dB
Frequency, GHz
Measured
Simulated
10
12
14
16
18
20
22
24
5
10
15
20
25
30
40 50 60 70 80 90 100 110
P3
dB,
dB
m
Pe
ak P
AE
, %
Frequency, GHz
-30
-25
-20
-15
-10
-5
0
20 40 60 80 100 120
ma
gn
itu
de
, d
B
Frequency, GHz
S11
, S22
225
High dynamic range IF amplifier
low noise figurehigh third-order interceptlow/moderate gain
Common-emitterPseudo-differential Strong inductive degeneration
high IP3. partly converges noise & S11 tuning
226
First IF Amplifier
Distribution Statement 226
5.5-6 dB gain6.5 dB noise figure95-105GHz
WITH
OU
T PA
DS: 5
51
um
X 5
75
um
,1
00
mW
DC
po
wer
20.7dBm IIP3(26.7dBm OIP3)
baluns for probe testing only
Simulations
227
IF Amplifier measurement results
75 80 85 90 95 100 105 1100
1
2
3
4
5
Frequency (GHz)
S2
1 (
dB
)
-20
-15
-10
-5
0
5
S1
1,
S2
2, S
12
(d
B)
S11
S21
S22
S12
Power consumption: 94 mA @ 2 VPeak gain: 4.3 dB @ 95 GHz, 4.0 dB @ 100 GHz
Low-gain (high-IIP3) design
Power consumption: 97 mA @ 2 VPeak gain: 5.9 dB @ 95 GHz, 5.7 dB @ 100 GHz
Low-gain (high-IIP3) design
75 80 85 90 95 100 105 1100
1
2
3
4
5
6
7
Frequency (GHz)
S21 (
dB
)
-20
-15
-10
-5
0
5
10
S12
S22
S11
S11, S
22, S
12 (
dB
)
S21
228
IF Amplifier measurement results
5
6
7
8
9
10
11
12
93 93.5 94 94.5 95 95.5 96
Simulated Noise FigureMeasured Noise FigureDe-embedded Noise Figure
No
ise
Fig
ure
(d
B)
Frequency (GHz)
20
25
30
35
92 94 96 98 100 102
Breakout OIP3, Vcc = 2VBreakout OIP3, Vcc = 1.5VSimulated OIP3, Vcc = 2VSimulated OIP3, Vcc = 1.5VDe-embedded OIP3, Vcc = 2VDe-embedded OIP3, Vcc = 1.5V
OIP
3 (
dB
m)
Frequency (GHz)
229
Performance: upconversion block
-5
0
5
10
15
20
25
30
-25
-20
-15
-10
-5
0
5
10
75 80 85 90 95 100 105 110
IIP3, w/o Mul (dBm)IIP3, Sim (dBm)IIP3 w/ Mul. (dBm)Conversion Gain, w/o Mul. (dB)Conversion Gain, Sim (dB)Conversion Gain, w/ Mul. (dB)Conversion Gain, Power meter (dB)
IIP
3 (
dB
m)
Co
nv
ers
ion
Ga
in (d
B)
IF Frequency (GHz)
Fixed RF input @ 200 MHz
-5
0
5
10
15
20
25
30
-25
-20
-15
-10
-5
0
5
10
0 2 4 6 8 10 12 14 16 18 20 22
IIP3 w/o Mul. (dBm)IIP3, Sim (dBm)IIP3 w/ Mul. (dBm)Conversion Gain w/o Mul. (dB)Conversion Gain, Sim (dB)Conversion Gain w/ Mul. (dB)Conversion Gain, Power meter (dB)
IIP
3 (
dB
m)
Co
nv
ers
ion
Ga
in (d
B)
RF Frequency (GHz)
Fixed IF frequency @100GHz
230
Upconversion measurement: Gain, IM3
Coupler Power sensor
1
Harmonic mixer
Spectrumanalyzer
Power meter
Signal generator (Multiplier, LO)
Signal generator (RF)
Frequency measurement: Harmonic mixerPower measurement: power meter
Harmonic mixerLO = (RF+IF)/n
In our test:n=10 and IF = 1 GHz
*Harmonic mixer LO frequency was adjusted to measure LO feedthrough(Harmonic mixer IF =1 GHz)
231
Downconversion measurement: IP3
232
mm-Wave Wireless
233
mm-Wave Wireless Electronics
Mobile communication @ 2Gb/s per user, 1 Tb/s per base station
Requires: large arrays, complex signal processing, high Pout , low Fmin
VLSI beamformersVLSI equalizersIII-V LNAs & PAs (?)
234
(backup slides follow)