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E-CAD LAB

BHARAT INSTITUTE OF ENGINEERING AND TECHNOLOGY

(Approved By AICTE and Affiliated to JNTU, Hyderabad)

(NBA ACCREDITED)

Mangalpally (V), Ibrahimpatnam (M)

ELECTRONICS COMPUTER AIDED DESINING

LAB MANUAL

ELECTRONICS AND COMMUNICATIONS DEPARTMENT

ELECTRONICS COMPUTER AIDED DESIGNING LAB Table of Contents

S.No.Experiment NamePage No.

1.LOGIC GATES

3-16

2.A POSITIVE EDGETRIGGERED D FLIP FLOP

17-19

3.D FLIP FLOP

20-22

4.T-FLIP FLOP

23-26

5.DECADE COUNTER

27-29

6.JK FLIP FLOP

30-31

7.4 -BIT BINARY COUNTER

32-34

8.SHIFT REGISTER

37-41

9.UNIVERSAL SHIFT REGISTER

42-44

10.3X8 DECODER

45-47

11.4-BIT COMPARATOR &

1-BIT COMPARATOR48-49

50-53

12.8X1 MULTIPLEXER

4X1 MULTIPLEXER54-56

57-61

13.16X1 MULTIPLEXER

62-65

14.READ AND WRITE OPERATIONS OF RAM

66-68

15.2X4 DECODER

69-74

16.FULL ADDER

78-80

1. LOGIC GATES

AIM: Write a VHDL code for all the logic gates.

APPARATUS: Xilinx ISE 7.1

#1-Title: AND gate

Logic gate symbol:

Truth Table:

xy z

00 0

01

0

1 0 0

1 1 1

VHDL Code:--Dataflow model

architecture behav1 of AND2 is

begin

Z