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Experiment - 1

AIM : To design and implement half adder.

DESIGN : VHDL code for Half-Adder was written and simulation waveform wasgenerated. The truth table is as follows:

Ao Bo So Co0 0 0 00 1 1 01 0 1 01 1 0 1

BLOCK DIAGRAM :

LOGIC DIAGRAM :

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VHDL Code:

library ieee;use ieee. std_logic_1164.all;

entity half_adder isport(a0,b0:in std_logic; c0,s0:out std_logic);end half_adder;architecture and_2 of half_adder isbegins0

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Experiment 2

AIM : To design and implement full adder.

DESIGN : VHDL code for Full-Adder was written and simulation waveform wasgenerated. The truth table is as follows:

Ak Bk Ck-1 Sk Ck 0 0 0 0 00 1 0 1 01 0 0 1 01 1 0 0 10 0 1 1 00 1 1 0 1

1 0 1 0 11 1 1 1 1

BLOCK DIAGRAM :

LOGIC DIAGRAM

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VHDL Code:

library ieee;use ieee.std_logic_1164.all;

entity fulladder isport (ak,bk,ck-1:in std_logic; sk,ck: out std_logic);end fulladder;architecture fulladder of fulladder isbeginsk

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Experiment 3

AIM: - To design and implement 8:1 Multiplexer.

DESIGN: - VHDL code for 8:1 Multiplexer was written and simulation waveform wasgenerated. The truth table is as follows:

O/P = I0 + I1 + I2 + I3 + I4 + I5 + I6 + I7

BLOCK DIAGRAM :

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VHDL Code:

library ieee;use ieee.std_logic_1164.all;entity mux8 is

port(x0,x1,x2,x3,x4,x5,x6,x7,s0,s1,s2:in bit;y:out bit);end mux8;architecture mux of mux8 isbeginprocess(x0,x1,x2,x3,x4,x5,x6,x7,s0,s1,s2)beginif(s2='0'and s1='0'and s0='0')theny

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Experiment 4

AIM: - To design and implement 3:8 Decoder.

DESIGN: - VHDL code for 3x8 Decoder was written and simulation waveform wasgenerated. The truth table is as follows:

LOGIC DIAGRAM

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VHDL Code:

library ieee;use ieee.std_logic_1164.all;

entity decoder3X8 isport (A,B,C:in bit; I:out bit_vector(0 to 7));end decoder 3X8;architecture dec_dataflow of decoder 3X8 is -- Architecture DeclarationbeginI(0)

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Experiment 5AIM: To design and, implement 4-bit comparator.

DESIGN: VHDL code for 4-bit comparator was written and simulation waveform wasgenerated. The truth table is as follows:

BLOCK DIAGRAM :

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VHDL Code:

library ieee;use ieee.std_logic_1164.all;entity comparator is

port(A,B: in std_logic_vector(3 downto 0);less :out std_logic;equal : out std_logic;greater : out std_logic);end comparator;architecture comp of comparator isbeginprocess(A,B)beginif (A

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Experiment 6

AIM: - To design and, implement a BCD to seven-segment decoder.

DESIGN: - VHDL code for a BCD to seven-segment decoder was written and simulationwaveform was generated. The truth table is as follows:

BLOCK DIAGRAM:

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VHDL Code:

library ieee;use ieee.std_logic_1164.all;entity seven_seg is

port(bcd:in bit_vector(0 to 3);led:out bit_vector(0 to 6));end seven_seg;architecture seg of seven_seg isbeginled

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Experiment 7AIM: To design and implement a 1:8 demultiplexer.

DESIGN: - VHDL code for a 1:8 demultiplexer was written and simulationwaveform was generated. The truth table is as follows:

S2 S1 S0 X7 X6 X5 X4 X3 X2 X1 X0

0 0 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 1 0 0 0 0 0 0 1 0 00 1 1 0 0 0 0 1 0 0 01 0 0 0 0 0 1 0 0 0 0

1 0 1 0 0 1 0 0 0 0 01 1 0 0 1 0 0 0 0 0 01 1 1 1 0 0 0 0 0 0 0

BLOCK DIAGRAM :

D0

D1

D2

INPUT D 3

DATA D4

D5

D6

D7

S0 S1 S2

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VHDL Code:

library ieee;use ieee.std_logic_1164.all;

entity demux8 isport(data,s0,s1,s2:in bit;x0,x1,x2,x3,x4,x5,x6,x7:out bit);end demux8;architecture demux of demux8 isbeginprocess(data,s0,s1,s2)beginif(data='1')thenif(s2='0'and s1='0'and s0='0')thenx0

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VHDL Code:

library ieee;use ieee.std_logic_1164.all;entity sipo1 is

port(d,pr,cr,clk: in bit;q0,q1,q2,q3: buffer bit);end sipo1;architecture sipo of sipo1 isbeginprocess(pr,cr,clk)beginif(pr='1' and cr='1' and clk='1') thenq0

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VHDL Code:

library ieee;use ieee.std_logic_1164.all;entity siso is

port(d,pr,cr,clk:in bit;z:out bit);end siso;architecture siso of siso issignal q0,q1,q2:bit;beginprocess(d,pr,cr,clk)beginif(pr='1' and cr='1' and clk='1')thenq0

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