thin film soi emerges

Thin-film SO1 emerges

Demand is building for thin-film silicon-on-insulator ICs, which get high speed out of less than 1 -V drive voltage and do away with complicated isolation schemes

veryone in a position to judge recognizes the advantages of silicon-on-insulator tech- E nology-higher circuit speed, lower power

consumption, greater immunity to radiation- induced errors, and compatibility with existing IC fabrication processes. In the past few years, these advantages have become critical for some commercial applications, particularly in the portable electronics arena, where the pressure for lower power and higher performance is unrelenting.

As companies, universities, government agen- cies, and consortia throughout the world address silicon-on-insulator (Sol) technology, the supply of less expensive yet high-quality SO1 materials is growing, and the grasp of the fabrication process strengthening-both encouraging signs. And as applications for the technology increase, the focus

L. ALLES ibis Techno’ogy

today is shifting from issues of feasibility to issues of circuit design and yield.

Why the excitement? An SO1 wafer is a layered structure consisting of

a relatively thin layer of single-crystal silicon either atop an insulating substrate, such as quartz or sapphire, or separated from a bulk silicon substrate by an electrically insulating layer-typically, silicon dioxide. The circuitry is constructed in the top silicon layer, above the insulator. Several methods are used to obtain the layered structure [see “A tale of SO1 materials,” p. 421.

SO1 technologies can be grouped into thick- and thin-film types. Over the past decade, many applications have been demonstrated for both types. Thick-film wafer technologies typically yield

IEEE SPECTRUM JUNE 1997 0018-9235/97/$10 0 0 0 1 9 9 7 IEEE 37

silicon layers 1 pm or more thick, thin-film layers seldom reach 0.5 pm. Thick-film varieties-well-adapted to high-power, analog, sensor, and smart-power applications using bipolar or bipolar-CMOS technologies-require less advanced lithographic processes and smaller wafers. But thin-film SO1 technology, suited to low-power, high-speed applications, will be targeted here.

CMOS, bipolar, and biCMOS circuits, including phase-locked loops, microcontrollers, arithmetic-and-logic (ALU) units, asyn- chronous-transfer-mode (ATM) switches, gate arrays, and dynamic and static RAMS (DRAMS and SRAMs), have been built to show the capabilities of thin-film SOI. Analog, mixed-mode, microwave, sensor, optoelectronic, and flat-panel display circuits have been built, as well. To date, though, commercially available thin-film SO1 ICs are limited primarily to radiation-hardened circuits (mainly SRAMs) and to high-temperature circuits.

The SOI. structure produces devices with smaller junction areas, simpler isolation structures, and steeper subthreshold-voltage slopes than bulk devices. Performance clearly profits from the con- sequent reduction in parasitic capacitances and leakage currents, as well as from the ability to use lower supply and threshold voltages without loss of speed. Speed improvements of 20-300 percent and power reduction of up to 90 percent relative to bulk silicon counterparts, as well as operation to below 1 V, are well established.

The isolation built in by the insulating layer in SO1 also elimi- nates latch-up (in which parasitic bipolar devices are activated) and

simplifies the process of isolating devices from one another. What's more, with SOI, wells and buried doped layers are not needed, so circuit sizes can be smaller than in bulk silicon counterparts [Fig. 11.

In the ideal IC, as feature sizes shrink and the number of devices per circuit goes up, device spacing should also be reduced. But techniques for electrically isolating transistors from one another are becoming more and more challenging. Local oxidation of silicon (Locos), because of the relationship between the width of the oxide and its thickness, can require devices to lie farther apart than otherwise would be necessary. An alternative is to use deep, narrow trenches for isolation, but the trenches are hard to refill.

In bulk CMOS device fabrication, wells and other isolating structures introduce parasitic effects that are harmful to IC performance and place constraints on how tightly devices can be packed. Either epitaxial silicon growth or ion implantation can be used to obtain highly doped layers and to control latch-up, but each adds to the cost and complexity of circuit processing. Conversely, for advanced thin-film SO1 CMOS processes, both Locos and trench isolation are simplified, since the isolation need be no deeper than the thickness of the top silicon layer-typically less than 0.25 pm. Also, the number of process steps has been reduced by up to 30 percent, and overall circuit area by up to 60 percent .

Structurally, too, thin-film SO1 has its rewards in such applications as high-voltage smart-power integrated sensors, three- dimensional devices, optoelectronic circuits, and radiation-tolerant

38 IEEE SPECTRUM JUNE 1997

circuits. The isolation layer permits high- and low-voltage devices to be integrated in close proximity, as is needed in some flat- panel displays. The layer in addition serves as an etch stop in the patterning of silicon waveguides and the fabrication of sensor membranes or 3-D structures. Leakage currents induced thermally or by exposure to radiation are reduced by substrate isolation, suiting SO1 to sensors as well as to automo- tive and space electronics.

Radiation tolerance is of growing impor- tance to advanced commercial devices. In DRAMS made with bulk-silicon technologies, for example, the minimum capacitance of the storage node is determined by the need for immunity to changes in data caused by radiation-a minimum that thin- film SO1 can relax.

Thin-film SO1 applications

power ICs has intensified. By 1998, low- power electronics may account for about 40 percent of the IC market. Lowering supply voltages will be one of the mutes to reducing the power consumed by ICs-and to protecting the thinner gate oxides that are part and parcel of devices of smaller critical dimensions. But as the supply voltage shrinks, drive currents dwindle and the capacitance associated with the junctions’ depletion region swells, slowing circuit operation. One way to maintain speed is to lower device threshold voltage. In bulk CMOS devices this move is unprofitable, because it also increases subthreshold leakage and standby power-but neither outcome affects SO1 wafers, with an oxide layer less than 0.5 pm thick under a silicon layer less than 0.25 pm thick. The steep subthreshold slopes of thin-film SO1 CMOS transistors allow threshold voltages to fall, so that circuit speeds can be maintained without affecting leakage current and standby power [Fig. 21. And because of the smaller junctions of thin-film SO1 devices, their superiority in performance to bulk circuits rises as supply voltages fall [Fig. 31. In addition, the insulating oxide sets bounds to the junctions, so that depletion capacitance almost vanishes. In short, thin-film SO1 is well suited to low-voltage submi- crometer digital CMOS applications.

Portable low-power electronics systems will, of course, require an array of circuitry, including processing, logic, memory, and communications--all capable of low-voltage operation. Each benefits from the ability to obtaiin reasonable performance at low voltage levels and with low power consumption. In fact, most of the work on thin-film SO1 applications in the past few years has described circuits for operation at or below 2.5 V, and more recently 1 V [Table 11.

At the first Symposium on Low Power Electronics, held in October 1994 in Phoenix, Ariz., Motorola Inc. presented electrical results for subcircuits of two reduced-instruction-set computer (RISC) microprocessors. Researchers from the h4esa, Ariz., group compared a thin-film SO1 version with a 0.5-pm bulk CMOS

Recently, interest in high-speed, low-

unit. At a supply voltage (V,,,,) of 2.5 V, the thin-film-SO1 version had an energy-delay product about one fifth of the level of the bulk version, and was much less sensitive to supply voltages down to below 1 V In the case of a 1Kb-by-8 SRAM test circuit, the SO1 CMOS part needed a supply voltage of only 1.5 V to achieve an access time of 15 ns---on a par with that of the bulk version operating at 2.5 V At the 1995 International Electron Devices Meeting, Motorola reported a 1 -V microcontroller that operated at twice the speed of the bulk part operating at 1 V

Nippon Telegraph and Telephone Corp., Kanagawa, Japan, has vigorously pursued thin-film SO1 applications. One demonstration was of a phase-locked loop containing a multigigahertz prescaler

ALLES -THIN-FILM SO1 EMERGES 39

in a O 25-pm thin-film SO1 CMOS technology Operating at 2 2 CHz and a supply voltage of 1 5 V, the circuit consumes less than 5 mW of power Over the past two years, NTT has also reported a low-power O M H z , 8000-gate, 16-bit ALU, a 48-bit multiplier running 28 percent faster and using 22 percent less power than a bulk counterpart, and a 1 2-V, 300 000-gate array that consumes only 30 mW In the plenary talk at the 1997 International Solid-

State Circuits Conference (ISSCC), Hiroshi Yasuda, vice presi- dent and director of N I T Information and Commmunications Systems Laboratones, descnbed Japan's multimedia network and a crucial element in connectivity to it, namely, the company's thm- film SO1 high-speed ATM switch The switch has the required data transfer rate of 40 Gb/s and consumes 8 4 W of power Mitsubishi Electric Corp , Hyogo, Japan, has also actively reported on thin-film SO1 developments, including a 220 000-gate array

[31 SO1 devices have clear speed advantages over devices having bulk silicon substrates, as is plain from this comparison of access times for 1Kb-by-8 static RAM test circuits built by Motorola Inc. on bulk silicon and Simox substrates (Simox stands for separation by implantation of oxygen). A 0.5-vm CMOS process was used in both cases. The measurements were reported by S. Wilson at the 1994 Electrochemical Society Symposium on SO1 Technology and Devices, Reno, Nev.

is determined mainly by soft-error considerations Charge generated by alpha or other ionizing particles can alter the data stored In DM cells, whose must therefore tolerate the

This charge is determined by the particle's ionization charactenstics in the silicon, together with the volume and length of its track, from which charge may be collected at key junctions in a circuit

The SO1 insulating layer limits the volume of this charge-collection region, since only charge generated in the thin top silicon layer can affect devices [Fig 41 The reduction of this charge in thin-film SO1 cuts the required DRAM cell capacitance, which is instead determined by data retention considerations (which also matter in bulk-silicon DRAMS, but are secondary there to soft errors) Data retention lasts as long as allowed by junction leakage currents, which charge or discharge memory cell capacitors when the devices are in a standby state Since insulators surround most SO1 junctions, the leakage current is smaller than in bulk devices In static mode (when the circuit is not being read or wntten), data is retained for longer than in bulk DRAM cells with the same capacitance Sol's advantages cut the cell capacitance requirement by about an order of magnitude But in the active mode (when the device is being read or wntten), issues related to transient charactenstics of thin-film SO1 devices may shorten the data-retention time

Both Samsung Electronics CO, Seoul, Korea, and Mitsubishi Electric have built 16Mb DRAMS in 0 5-pm thin-film SO1 technology The Samsung part, reported at the 1995 VLSI Technol- ogy Symposium, Kyoto, Japan, showed an access time of 50 ns at 3 V-20 percent faster than the bulk counterpart The Mitsu- bishi Part Operated to time Of 46 ns The bit-line capacitance and required storage capacitance were half those of the bulk DRAM

DRAMS based on thin-film so1 are essentially immune to soft errors induced by alpha particles NEC Corp , Kanagawa, Japan, bullt and tested such cells for 1 c b DRAMs Fabricated In a 0 4.pm CMOS process on th,n-film sol, the cells data for 550 seconds at 25 "C, five to six times as long as their bulk counter-

charge collectable from the track of an

141 So-called soft errors in memories are typically caused by an alpha particle-the nucleus of a helium atom-that penetrates the silicon and creates excess charge by ionizing the atoms in i t s path. Some of this charge may be collected by the storage node, and if enough is collected, the value of the stored data could change. In an SOI-based dynamic RAM cell, the buried insulating layer truncates the collection region so that the storage node cannot accumulate enough charge to change the cell's logic state.

with an

[51 Lateral bipolar transistors on 501, developed by Philips Research Laboratories, offer Small emitter dimensions, low power consumption, and high-frequency operation in the gigahertz region.

Instruments Inc., large in area with a radiation-resistant so1 process. Despite the relative complexity of the radiation-hardened fabrication and design pro-

has fabricated a lMb


cess, no adverse yield issues were attributable to the SO1 material or the associated process. Thin-film SO1 256Kb radiation-hardened SRAMs have been produced by several manufacmrerr, including TI, Hams Corp., Palm Bay, Fla., and Honeywell Inc., Plymouth, Minn.

More recently, thin-film SO1 has also become commercially attractive for SRAMs. Low-voltage operation aind reduced power consumption are again the driving factors. IBM Corp., Yorktown Heights, N.Y., has reported an SOI-based 512Kb SRAM that has a 3.5-ns access time at 1 -V operation, consuming only a tenth of the power of a bulk silicon equivalent. Such parts are attractive for portable computer cache memory. Work continues on radiation-hardened and commercial thin-film SO1 SRAMs, with 1Mb and 4Mb versions under development,

For portable communication devices, low-cmt radio frequency (RF) circuits are in demand. While gallium arsenide serves much of the need for high-frequency communications, silicon-based technologies are nonetheless attractive, since they could more easily be integrated with other silicon devices and are potlmtially less costly. Yet such approaches as silicon bipolar consumt: more power, for there is no isolation from the supporting substrate. Silicon-germanium is one approach being investigated [see “The SiCe bipolar transistor,” IEEE Spectrum, March, 1995, pp. 49-35]. Researchers at IBM in Yorktown Heights are examining the combination of silicon-germanium on thin-film SO1 substrates as a way to achieve circuits with even higher frequency and lower power.

Such devices as pagers and cellular phones require circuits that operate at frequencies from several hundred megahertz to several gigahertz and use little power. Operation at frequencies greater than I GHz and at supply voltages below 2 V are attributes of several thin-film SO1 circuits aimed at such RF applications.

For instance, as early as 1989, scientists at AT&T Bell Labs, Murray Hill, N.J., built a 6.2-GHz dual-modulus prescalar on thin-film SO1 that was 50 percent faster than the bulk variety and consumed 210 mW operating at 3.5 V Since that time, several companies have demonstrated basic building blocks of communications devices, including prescalars, phase-locked loops (PLLs), and frequency dividers, that operate below 2 V. Most recently, Fujitsu Ltd., Kawasaki, Japan, has described a 1-V 340-MHz PLL that is suited to pager applications. It is 1.9 timles faster than the bulk version and consumes 25 percent less power at the same speed. In 1991, Westinghouse Electric Corp., Pittsburgh, reported an all-silicon microwave IC technology based on high-resistiv- ity thin-film SOL More recently, a standard thin-film SO1 CMOS process has been used to demonstrate microwave transistors that operate down to 0.9 V. RF amplifiers have been demonstrated by the Fraunhofer Institute, Duisburg, Germany, the Universitk Catholique de Louvain, Belgium, and MIT Lincoln Laboratory, Lexington, Mass. T h e 0.25-pm technology of the latest one was developed as part of the Defense Advanced Research Projects Agency‘s Low Power Electronics program. It in- cluded a data-thinning circuit that attained 1.14 GHz at 2 V. AlliedSignal Inc., Morristown, N.J., and Hitachi Ltd., Tokyo, have also told of applying thin-film SO1 CMOS to RF circuits.

In addition to CMOS, lateral bipolar devices for high-frequency, low-power (low current) circuits have been reported, including BiCMOS processes with complementary lateral bipolars by the University of California, Berkeley, and with lateral npn devices by Motorola. Philips Corporate Research, Eindhoven,

ALLES -THIN-FILM SO1 EMERGES

the Netherlands, has announced the development of an ultralow- power lateral bipolar technology on 501. Excellent performers, the devices have emitter areas as small as 0.15 pm2 and unity power gain values as high as 15 GHz. The process requires only seven masks, one layer of metal, and one critical step: an anisotropic poly etch with a high selectivity to oxide [Fig. 51.

Through thick and thin Sensors, high-temperature electronics, and smart power cir-

cuits have been implemented with both thick- and thin-film SO1 materials. Materials requirements for these applications, more especially the sensors, may differ somewhat from those of thin- film SO1 CMOS or thick-film SO1 bipolar circuits. In some cases, the underlying oxide may serve as an etch stop in the cre. ation of structural features, such as membranes, or to limit thermal leakage in circuits. In this instance, the silicon layer might have to be thick, whereas the buried oxide could be relatively thin. When high voltages must be supported across the buried oxide, the layer has to be thick.

A good deal of SO1 sensor work has been undertaken in Europe. In Germany, the Fraunhofer Institute, Duisburg, has developed a high-temperature pressure sensor, a microwave power sensor, a sensor for invasive blood-flow characterization, and a mag- netic field sensor. Fabrication employs the buried oxide layer as an etch stop to isolate the sensing elements in the top thin silicon membrane [Fig. 61. Circuitry, which can be integrated with the sensors, is fabricated in the adjacent regions where the underlying substrate is intact.

In the United States, Honeywell manufactures high-temperature sensors on SO1 for oil-drilling equipment.

SO1 thin-film transistors (TFTs) are also of use in flat-panel displays. At the 1994 IEEE Silicon on Insulator Conference, the David Sarnoff Research Center, Princeton, NJ., along with several companies collaborating on a project funded by the Ad- vanced Research Projects Agency, presented a process that used SO1 to fabricate liquid-crystal displays (LCDs) and electroluminescent displays. The unique aspect of the SO1 technology is the transfer of the thin silicon layer onto a glass substrate. LCD pixel sizes as small as 12 pm2 were made. The electroluminescent display uses an SO1 process suitable for 200-V high-density, active- matrix, fully scanned electroluminescent displays. Pixels as small as 24 pm2 were obtained, and fully functional 128-by- 128 arrays

were fabricated with brightness levels

[6] Sillicon-on-insulator structures are an excellent meanis of manufacturing silicon-based sensors because thin silicon membranes can be created by using1 the buried insulating layer as an etch stop. The associated electronics can then be fabricated in the aldjacent regions.

of 800 fL (2400 cd/ml)-and contrast ratios greater than 1000: 1 . Planar Systems Inc., Beaverton, Ore., has also reported the use of insulating SO1 materials for flat-panel displays, and SuperTex Inc., Sunnyvale, Calif., had been applying SO1 in flat-panel displays under a Darpa program.

Analog parts have not been over- looked, either. Thomson-CSF SA, based in Paris, France, has reported CMOS 8-bit, 20-MHz analog-to-dig- ita1 converters on thin-SO1 substrates, as well as digital and analog application-specific ICs. At the 1995 ISSCC, Fraunhofer researchers discussed a current-mode amplifier using a 0.6-pm SO1 CMOS process. The amplifier has a 10-dB current gain at 1 G H z and dissipates 40 mW of power operating at 3 V. AlliedSignal has told of a solenoid-driver, and the Universite Catholique de Louvain, Belgium has reported low-power, high-gain, and high-frequency operational amplifiers

41

for operation at up to 300 "c Furthermore, studies by both Motorola

and National Semiconductor Corp , Santa Clara, Calif, found that SO1 substrates have more desirable cross talk characteristics than their bulk-silicon counterparts

do-an appealing feature for mixed-mode applications

Choice of process technologies SO1 provides a foundation for many

technology options-CMOS, bipolar, and

biCMOS, among others For low-power electronics, the primary candidate is CMOS Here, thin-film SO1 tantalizingly offers the possibility of Mly depleted operation In such a case, the maximum width of the depletion reaon beneath the trams-

4 2 IEEE SPECTRUM JUNE 1997

tor gate is greater than the silicon layer's thickness, and the entire body of the transistor is depleted except for an accumulated or inverted channel region. If the junctions extend to the buried oxide, that layer bounds the source and drain depletion

regions on the bottom. Such devices are attractive for mainstream CMOS IC evolu- tion for several reasons. They have an ideal subthreshold slope of 60 mV per decade, they are resistant to short-channel effects, arid they altogether eliminate the floating-

body effects that afflict partially depleted thin-film SO1 devices.

Floating body effects are unique to partially depleted devices. Because t h e threshold voltage is modulated by the charging in the isolated transistor body,


the effects produce a "kink in the dc out- put of SO1 transistors They cut the transistors' breakdown voltage and cause hys teresis in the switching characteristics, and their prevention complicates the circuit design The floating-body effect can be addressed in the process integration in several ways, including the use of lightly doped drain and source structures, body ties, the reduction of minority carrier life time through germanium implantation, band-gap engineering, the application of substrate bias, or field-shield isolation

The effects are not pronounced in fully depleted devices, where the gate voltage controls the body potential But manufac turing issues present difficulties for fully depleted devices They tend to be more sensitive to material parameters because they use thinner silicon films, while con- tact formation and threshold voltage control are more challenging Several methods of overcoming the sensitivity while maintaining the benefits of fully depleted operation have been shown, such as a near fully depleted mode of operation, threshold doping based on constant doses rather than constant concentration, and raised source and drain regions There is a tradeoff for CMOS applications existing designs are more easily transferable to fully depleted devices, the process technologies to partially depleted ones At pre sent, it is unclear which type of device will

be used first in thin-film SO1 CMOS products. U.S. firms and some Japanese manufacturers are leaning toward partially depleted technology, while other Japanese companies are having great success with fully depleted devices.

Bipolar processes fashioned on SO1 include thick-film vertical and thin-film lateral devices. Scientists at Philips Re- search Laboratories, Motorola, and the University of California at Berkeley have observed very good performance in lateral bipolar devices on SOI. To date, however, thick-film SO1 vertical bipolar devices have been more popular.

BiCMOS devices, too, have been constructed on SOI. Motorola has reported a thin-film SOI-based biCMOS process for low-power applications. Other technology variations, including silicon-germanium on SOI and hybrid-mode devices ( MOS and bipolar integrated in a single SO1 transistor), have been investigated, as well. Integrating SO1 with bulk technology is of interest for such applications as smart power, where CMOS SO1 control circuitry can be meshed with bulk power devices. The University of California at Berkeley has reported a bulk-SO1 hybrid technology in which bulk MOSFETs were built in the substrate after the patterned removal of the top silicon and buried oxide layers. The bulk transistors can be used as protec- tion against electrostatic discharge.

SO1 technologies must overcome two ob- stacles: electrostatic discharge and thermal dissipation. When devices are insulated from the substrate, the dissipation of abundant transient energy requires special considera- tion in the design of electrostatic-discharge devices. Also, since each device is surround- ed by silicon dioxide, which is two orders of magnitude worse at conducting heat than is silicon, heating effects can degrade performance. Modeling and experimentation have shown that this is primarily a steady-state concern: devices that switch quickly, such as those in a microprocessor, do not have the time to heat up significantly.

The heating is determined by average power and is not always reflected by measurements taken using DC bias condi- tions. Further, the metal contacts and wires help to dissipate it away from in- dividual devices. Heating also becomes of less account as supply voltages fall and as buried oxide layers get thinner. Nonethe- less, heating remains an issue for model parameter extraction, which is usually performed with dc measurements. The use of ac or pulsed measurements can deal with this problem effectively.

The future Thin-film SO1 continues to chase the

low-voltage issue, and the biggest competi- tor of thin-film SO1 technology continues to be bulk technologies. Texas Instruments


has told of utilizing 0.18-pm bulk CMOS technology for digital signal-processing chips operating at 1 V: The physics, however, sug- gests that if anything can be done on bulk, it can be done even more effectively on Sol.

Take a 1-V thin-film SO1 CMOS technology developed by the Massachusetts Institute of Technology's Lincoln Labor- atory, in Lexington, Mass. Researchers there used both 248- and 193-nm lithography to achieve 1/36 the power consumption of a 0.5-pm bulk CMOS process. Again, at the 1996 ISSCC, Toshiba Corp., Tokyo, described a 0.5-V, 16-bit multiplier with 18-11s multiplication. It consumed only 4 mW At this year's conference, the company described a 0.5-V, 200-MH2, 32-bit ALU that consumed just 2 mW and had a power-delay product amounting to only 5 percent of its bulk equivalent. NIT has also told of using thin-film SO1 CMOS to develop al6-bit ALU at 0.5 V:

A clever idea n intriguing opportunity for very ow-voltage operation is a novel

tion reported by the Hewlett-Packard Co., the University of California at Berkeley, and IBM. The device exploits what is called the body effect, in which a MOS transistor's threshold voltage depends on the substrate (body) potential beneath the gate [Fig. 71. The gate and body of the MOS transistor are electrically connected, so when the transistor is turned on, the threshold voltage decreases, making for more efficient switching; when the device is off, the threshold voltage increases, making for low leakage currents. Although this type of device is feasible in bulk silicon, it is less efficient, due to the parasitic capacitance caused by the device being in con- tact with the substrate. In the SO1 configu- ration, the device operates with extremely low power, on supply voltages below 0.7 V, and demonstrates an ideal subthreshold slope of 60 millivolts per decade.

Transistors, inverters, and ring oscillators have been built that used this device config- uration running at a 0.7-V supply voltage. At higher voltages, the body- source junction becomes forward-biased, activating the inherent bipolar structure. Exploiting the drive current of both the bipolar transistor and the MOS device can produce excellent performance with ideal subthreshold slopes and bipolar current gains greater than 500 at low power levels. This bipolar mode of operation uses rather more power, though, and better suits high-speed operation.

On another front, the continued scaling of device dimensions is becoming an extravagance. Currently, 0.25-pm CMOS technologies are entering production. New fabrication facilities with state-of-the-art lithography cost US $1 billion to $2 billion now and are projected to cost about

k thin-film SO1 transistor configura-

$10 billion by 2005. The economics could give thin-film SO1 an opening in large- scale mainstream circuit applications. Process simplification and performance benefits of thin-film SO1 could help offset increasing costs and extend the usefulness of existing tools and facilities.

One of the greatest virtues of thin-film SO1 is the fact that it is a silicon technology, fully compatible with existing process steps and equipment. Studies by Sematech Inc., Austin, Texas, presented at the 1994 EIlectrochemical Society Symposium on SO1 Technology and Devices, Reno, Nev., showed that a 64Mb SRAM built in a thin-film-SO1 CMOS process uses three f'ewer mask levels than a comparable bulk CMOS process and can reduce the number of fabrication steps by 13-20 percent. An analysis of manufacturing costs presented at the 1994 Low Voltage, Low Power Technology Workshop, Tempe, Ariz., indicated that the cost per die of circuits on 200-mm-diameter SO1 wafers is comparable to that of counterpart circuits o n 300-mm bulk silicon wafers.

The hurdles ahead Challenges remain. Substrate quality,

cost, and availability have improved noticeably in the past three years, but the consistency and cost of materials and their availability in large volumes remain problems. Probably, the availability of large quantities of wafers-particularly wafers of the same material from multiple sources-will have to be addressed, too. Circuit design is another bottleneck: clesign tools for large circuits are not widely available for thin-film SO1 devices.

The unique floating-body effect makes clesign difficult without accurate models, but the models are more complex and do riot lend themselves to large circuit designs. Even with good design tools, large circuit designs can require tremendous resources. Ways of dealing with the floating-body effect demand added process steps or circuit area, thus reducing thin-film SOI's benefits. None of these problems looks like being a permanent obstacle for thin-film Sol, but the money and time needed to overcome them leave the momentum at present to bulk-silicon technologies.

For several years, thin-film SO1 was a technology of the future. But the past two years' developments indicate that the future is in sight. Much of the research on thin- fiilm SO1 at universities and research insti- hJtes has been transferred to industry. In the United States, the Semiconductor Research Corp., Research Triangle Park, N.C., has played a major role in this process, funding slubstantial efforts and centers of excellence for SO1 technologies at major universities throughout the country. SRC conducts periodic technology-transfer courses, and Sematech sponsors industry-university-gov-

ernment joint projects to disseminate SO1 technology. The Advanced Research Pro- jects Agency's Low Power Electronics Pro- gram and Sematech's continuing thin- film-SO1 programs have lent the technology greater visibility.

Moreover, SO1 is a key technology on the Semiconductor Industry Association's road map of the 21st century, For thin-film Sol, it seems a question, not of if, but of when-and of who will be first to market. Several major semiconductor manufacturers are proceeding in this direction, and their success will be critical in determining whether thin-film SO1 will be a standard technology for the IC industry. +

To probe further Two books-Silicon-On-Insula tor Technology:

Materials to VLSI, by J. P. Colinge (Kluwer Academic, 1991) and Electrical Character- ization of Silicon-On-Insulator Materials a n d Devices, by Sorin Cristoloveanu (Kluwer Academic, 1995)-give an excellent overview of Sol, ranging from materials t o applications.

Informative articles by A.J. Auberton-Heme and co-authors on SO1 applications include "SO1 Substrates for Low-Power Electronics," in Solid State Technology, May 1995, pp. 87-90; "Sol Materials for ULSl Applications," in Semiconductor International, October 1995, pp. 97-100; and '501-Based Devices: Status Overview," in Solid State Technology, July 1994, pp. 89-96.

Information on specific applications can be found in the proceedings of annual technical conferences: the International Electron Devices Meeting's technical digests (especially those of 1991-96), the Symposium on VLSI Technology's technical digests (1993-96). and the Proceedings of IEEE international SO1 conferences (1991-96). Specific applications are also described in such publica- tions as IEEE Electron Device Letters, IEEE Transactions on Electron Devices, and the /€€E Journal of Solid State Circuits. In the United States, the Semiconductor Research Corp., Research Triangle Park, N.C., and Sematech member companies have access to much information on SO1 technologies through the results of sponsored research.

About the author Michael L. Alles, director of applications engi-

neering at ibis Technology Corp., Danvers, Mass., has a background in silicon-on-insulator (Sol) device physics and experience as a design engineer on an industrial 256Kb SO1 static RAM. He is now responsible for identifying application opportunities, for Simox (separation by implantation of oxygen), for serving as a technical liaison between Simox users and Ibis, and for SOI- based device and process integration issues. He can be reached at mike-alles9ibis.com.

Spectrum editor: Linda Geppert


http://mike-alles9ibis.com

thin film soi emerges

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