Coulomb Blockade in Thin SOI Nanodevices.

D. Fraboulet, X. Jehl*, D. Mariolle, C. Le Royer, G. Le Carval, P. Scheiblin, P. Rivallin, D. Deleruyelle, L. Mollard, M. E. Nier, A.Toffoli, G. Molas, B. De Salvo, S. Deleonibus

and M. Sanquer* CEA-LETI and * CEA-DSM-DRFMC-SPSMS

CEA-Grenoble, 17 rue des Martyrs 38054 Grenoble Cedex 9, France fraboulet@cea.fr, xjehl@cea.fr

Abstract

Deca-nanometer size SOI devices have been fabricated with a conventional SOI-MOSFET process adapted in order to favor Coulomb blockade in a silicon channel locally constricted. The device is designed in a thin highly doped SOI layer. At low temperature, the field effect induced by the gate is modulated by periodic Coulomb blockade oscillations attributed to the accumulation islands formed below the gate. The Coulomb oscillations are remarkably periodic, insensitive to disorder and their period is given by the planar capacitance between the gate and the SOI film.

1. Introduction

Very thin SOI is prerequisite for scaling down the MOSFET and the problem of access resistance to the thin fully depleted SOI channel is pendent. Highly doped SOI wires exhibit unintentional Coulomb blockade oscillations (CBO) [1] showing the role of structural roughness and segregation effects in the formation of disconnected electron islands. Disorder in thin SOI source and drain in a small SOI-FET will give high access resistances. The small number of carriers and the disorder can make single electron phenomena play an important role in emerging CMOS devices. Some authors use these phenomena to design highly integrated and low power memory cells [2]. Numerous publications show CBO in silicon and the relative control of the Coulomb energy [3-6]. Either the geometry is well controlled, with multiple gate techniques [7-9] and the Coulomb energy is small, or the Coulomb energy is large but the confinement region is not controlled [3,10]. In MOSFET wires [3,10] the size of the quantum dot scales with the width of the wire. Multiple dots in series are likely to form in such geometry. In standard MOSFET [11] the size of the quantum dot scales with the length of the channel. A single local constriction MOSFET has been shown to define an ultimate single dot [6].

We fabricated such constriction SOI-MOSFETs with small volume (thin film, narrow channel, short gate length). We observe Coulomb blockade in this structure with highly resistive source and drain. Due to

these large access resistances we can observe periodic CBO superimposed to aperiodic and sample-dependent oscillations due to the disordered constriction.

2. Device Fabrication

Device fabrication is adapted from SOI technology. An SOI wafer is thinned down locally to Tsi ˜ 10nm in active areas. These areas have been highly doped (above 1e19 cm-3), paying attention to keep a good cristallinity of the silicon. In order to ensure a low resistivity for the contact on silicon, the SOI under the contacts is thicker (70nm) and heavily doped (As 30keV, 2e15cm-2) (fig. 2). The resulting resistivity in these “thick” SOI areas is below 100 O/? . The active areas are protected during this operation in order to avoid amorphisation of the thin SOI layer. Wires are then defined by an hybrid DUV/E-Beam lithography using Sumitomo negative tone resist and E-Beam LEICA VB6R (fig. 1).

Figure 1. Left: SEM image after gate etching of a “nano-wire” device Lf= 200nm, W=30nm, Lg=40nm. Right: “Point Contact” device before gate processing: W=20nm. Lf=20nm.

Various sizes of “deca-nano-wires” have been implemented. Moderate resist trimming (-8nm) is performed before RIE etching of the thin Silicon layer. A gate oxide of thickness 10nm is deposited. The gate consists in 100nm doped poly-Si, its lithography is then performed with E-Beam without resist trimming. Gate etching is performed by RIE (Breakthrough C2F6, Main etch: HBr, Chlorine, O2). The following fabrication steps are fairly conventional: W/TiN/TiSi2 contact plugs, USG-PSG(0.8µm) intermetal dielectric,

100nm

S D

G

G

Lg

400nm W

Lf

S D

AlCu (440nm) metal 1 level, metal passivation and pad opening. It was verified that the access resistances are dominated by the thin doped SOI lead and not by “thick” SOI areas and W-contacts: the total resistance between 2 pads without thinning of active SOI area is kept below 2 kO, whereas the lowest device resistance exceeds 100 kO.

Figure 2: TEM cross section of thin SOI film in a typical device with high conductivity. The thin SOI access lead is ˜ 1µm long, its width is enlarged to 0.4µm away from the vicinity of the gate and it gives a large contribution to the total resistance. The wire length Lf varies from 20nm to 200nm (fig 1). The wire width W varies from 30nm to 400nm and the gate length Lg ranges from 30nm to 400nm.

Figure 3. TEM cross section of a W=0.4µm, Lg= 50nm, Tox=10nm, Tsi=3nm device. This device was found to be highly resistive.

3. 300 K resistivity measurements

We believe that etching and doping very thin and narrow SOI active regions produce a large amount of defects that can trap electrons in thin wires. The high sheet resistance in films indicates that the actual concentration of carriers is strongly reduced from the nominal doping value, making the electron gas mobility and density very sensitive to disorder in confined geometry. Many phenomena could explain the degraded conductivity of the small SOI layers. The thickness of SOI was not fully controlled during our

process as we started from standard 8’’ SOI (UnibondTM, SOITEC) wafers with thickness dispersion of ±5nm. All electrical characteristics depend strongly on the thickness measured by ellipsometry (calibrated by TEM views).

Thin Film Doping Ion implantation doping of thin films is tricky

because of possible irreversible amorphisation. In bulk silicon, monocristallinity can be recovered by an adequate thermal treatment since cristalline germs are always present unlike in very thin SOI. Recovering monocristal properties in the SOI layer is then difficult. The simulation shows (fig. 4) a high amorphisation probability for films thinner than 7nm. Our electrical measurements effectively showed a strong current decrease and a significant increase of dispersions for devices with film thinner that 7-8nm.

Figure 4: TRIM[12] simulation of 10nm SOI film

doping : Arsenic, 2e14 cm-2, 8keV, 45Å. No amorphisation of silicon is expected above 7 nm.

Etch induced depletion

The high resistivity of these thin and narrow SOI films can also be attributed to defects and/or damages induced by the RIE process. We infer that etching the active areas creates a lateral “dead region” that further reduces the wire width. Electrical measurements suggest a narrowing of ˜ 20-30nm, as compared to the technological width. This was observed on 200, 100 and 50nm wide active lines that were measured at 175±10nm, 75±10nm and 25±10nm. This agrees with the thickness dependence of the threshold voltage Vt: at room temperature Vt decreases with Tsi on all the samples, except for W=30nm. This reduction of Vt can be understood as a decrease of initial available carrier density. Since, this dependency essentially vanishes for W=30nm, we can infer that no more initial carriers are available for conduction, regardless of the thickness of the film. Similarly, the thin film regions which have been exposed to gate RIE can also be damaged.

« thick » SOI

active SOI

7 nm

1016

1017

1018

1019

1020

1021

1022

1023

-0,01 0 0,01 0,02 0,03 0,04 0,05 0,06

Defects [Atom/cm3]As Concentration [Atom/cm3]

Depth [µm]

SOI Buried Oxide

Amorphised region

4. Low temperature measurements

Two devices have been studied at low temperature, corresponding to Lf=20nm, W=20nm, Lg=100nm (sample 1) and Lf=50nm, W=50nm, Lg=100nm (sample 2). For both samples there is a strong gate overlap on the spreading regions. Samples with long access wires to the gate-controlled region (L<<Lg) have diverging resistance at low temperature. Samples 1 and 2 correspond to SOI film sheet resistance at room temperature of 4500±500Ω, amongst the lowest measured.

Figure 5: Threshold Voltage versus SOI thickness

at T=300K. Vt dependency on Tsi is very reduced for W=30nm.

Fig. 6 shows drain conductance-gate voltage Gds-Vg characteristics in the linear regime (Vds=1mV) at T=300K, 77K, 4.2K and 100mK for sample 1. A field effect is observed with a threshold voltage strongly dependent on temperature. At T=77K oscillations of Ids appear in the subthreshold regime, and develop into aperiodic resonances at T=4.2K. The large decrease of the drain-source current at low temperature (even in the open regime) is attributed to the temperature dependence of the high resistive access regions. Correlatively, these access resistances have a very non linear behavior at low temperature: by applying a finite VDS (fig. 6), we increase very much the current without changing qualitatively the CBO.

These features are commonly observed in silicon nanoconstrictions and wires, as well as in deca-nanometric MOSFETs and originate from coherent interference (resonant tunnelling) and/or charge effect (Coulomb blockade) in mesoscopic disordered insulators [3]. The comparison between samples 1 and 2 shows that these features as well as the threshold voltage itself (especially at low temperature) are strongly sample-dependent, as expected for such small constrictions. Superimposed on sample-dependent field effect, a very periodic modulation is observed in both samples. We show that these CBO are not due to the particular configuration of the disorder in the

constriction, but arise from the geometry of the sample, which is well controlled by lithography.

5. Coulomb blockade oscillations

-4 -3 -2 -1 0 1 2 31E-4

1E-3

0,01

0,1

100mK, Vds=2mV

100mK

4.2K

77K300K

G (e

2 /h)

Vg (V)

Figure 6: Drain-source conductance versus gate voltage for sample 1 at various temperatures for Vds˜ 0. At T=100mK , applying Vds˜ 2mV increases strongly the conductance.

Fig. 7 shows CBO appearing in both samples with

the same periodicity. Hundreds of oscillations are recorded in the whole range of gate voltage where Ids is measured.

The planar capacitance for 10nm thick SiO2 is Cg=3.4 10-15 Fµm-2. The periodicity in gate voltage being 5.5mV we found Cg=e/5.5mV=2.9 10-17 F, for an estimated surface of the quantum dot 8500 nm2. For a typical carrier concentration of 4e12 cm-2, such a dot can accomodate ˜ 340 electrons. The nominal surface covered by the gate, Sg, is about 6300 nm2 and 5300 nm2 for sample 1 and 2 respectively. Without a 3D calculation for the capacitance to gate, we can say that those numbers are in good agreement: the periodicity of the oscillations is well understood in terms of resonances in the quantum dot defined by Sg. Sg is the same within 15% for both samples, while the surface of the constriction itself varies by a factor of 4 (20nm×20nm in sample 1 and 50nm×50nm in sample 2). The activation energy of the minima of conductance, e2/2CΣ [13], is about 1meV from fig. 8 ](CΣ is the total capacitance of the dot).

We propose the following model to explain the origin of the Coulomb oscillations. The gate voltage simultaneously opens the constriction and creates quantum dots by accumulation of electrons in the SOI film under the gate. These dots are delimited by the highly resistive SOI film leads. As noted earlier, this resistance is much larger than the quantum of resistance, increases sharply at low temperature and is also very non-linear. It has been shown that two tunnel barriers are not necessary for Coulomb blockade [14].

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1

50 60 70 80 90 100 110

W=30nm Lg=30nmW=40nm Lg=30nmW=30nm Lg=40nmW=40nm Lg=40nm

Tsi(Å)

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Vg (V)

Vds

=3mV

Vds

=2mV

sample 2

sample 1

G (e

2 /h)

G (e

2 /h)

Figure 7: Coulomb oscillations at T=100mK in samples 1 & 2. We observe the same periodicity (˜ 5.5mV) for those oscillations although the values of Vg and the level of conductance are very different.

Another indication that the single electron effects are induced by the geometry and not by the disorder is that samples 1 and 2 exhibit very different levels of 1/f (telegraphic) noise. Sample 2 is much more noisy than sample 1, indicating more dynamic disorder, but the Coulomb oscillations are similar.

-0,96 -0,94 -0,92 -0,90 -0,88

10-4

10-3

10-2 1.9K

T=1.2K

2.4K

G (

e2 /h)

Vg (V) Figure 8: Coulomb oscillations at various temperatures in sample 1. From the activation energy of the conductance minima, we estimate a charging energy of about 1meV

7. Conclusion

We have shown in resistive thin doped SOI films that CBO appear in point contact geometry. The CBO periodicity is determined by the overlap capacitance between the gate and the SOI film. We associate this observation to the high sheet resistance of the film, outside the gate overlap. Our results show the importance of the access resistance in SOI-FET in controlling SET versus FET effects. This work has been carried out, in the frame of CEA-LETI/CPMA collaboration, with PLATO organization teams and tools .

8. References

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