analytic model for single-electron transistorsdownloads.hindawi.com/archive/2001/071879.pdf ·...

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VLSI DESIGN 2001, Vol. 13, Nos. 1-4, pp. 189-192 Reprints available directly from the publisher Photocopying permitted by license only (C) 2001 OPA (Overseas Publishers Association) N.V. Published by license under the Gordon and Breach Science Publishers imprint, member of the Taylor & Francis Group. Analytic 1-V Model for Single-Electron Transistors XIAOHUI WANG and WOLFGANG POROD* Center for Nano Science and Technology, Department of Electrical Engineering, University of Notre Dame, Notre Dame, IN 46556 We present an analytical model for the I- V characteristics of a single-electron transistor, which may be incorporated in a conventional circuit simulator, such as SPICE. Our model takes as its input the physical SET characteristics (capacitances and tunnel resistances, which may be determined experimentally), and it yields !-V curves which are in excellent agreement with the ones obtained from full-scale Monte Carlo simulations. Keywords: Nanoelectronics; Single-electron transistor; Coulomb blockade; Device simulation; Circuit simulation INTRODUCTION Single-electron transistors (SET) offer the promise of ultra-high integration densities and ultra-low power consumption [1]. Considerable effort has been expended over the past decade, or so, in the understanding of the physical principles of SET operation, and this topic has reached a quite mature stage [2]. The fabrication technology of SET’s has also come a long way, from its beginnings with individual metallic islands operat- ing at cryogenic temperatures, to device structures approaching room-temperature operation. The development of large-scale SET circuits will require the development of simulation tools, and some work has been done in this area in recognition of this need [3-5]. Most simulation approaches are based on the Monte Carlo technique, and the main challenges is to reconcile the numerical expense of this method with the requirement of an economical device model which may be used for the simulation of large circuits. In this paper, we present an analytical model for the I-V characteristics of a single-electron tran- sistor, which may be incorporated in a conven- tional circuit simulator, such as SPICE. Our model takes as its input the physical SET characteristics (capacitances and tunnel resistances, which may be determined experimentally), and it yields I-V curves which are in excellent agreement with the ones obtained from full-scale Monte Carlo simu- lators, such as SIMON [6]. THE MODEL On model is based on the schematic SET structure shown in Figure 1. Electrons may tunnel across the *Corresponding author. Tel.: + 219 631 6376, Fax: + 219 631 4393, e-mail: [email protected] 189

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Page 1: Analytic Model for Single-Electron Transistorsdownloads.hindawi.com/archive/2001/071879.pdf · Keywords: Nanoelectronics; Single-electron transistor; Coulomb blockade; Device simulation;

VLSI DESIGN2001, Vol. 13, Nos. 1-4, pp. 189-192Reprints available directly from the publisherPhotocopying permitted by license only

(C) 2001 OPA (Overseas Publishers Association) N.V.Published by license under

the Gordon and Breach Science Publishers imprint,member of the Taylor & Francis Group.

Analytic 1-V Model for Single-Electron Transistors

XIAOHUI WANG and WOLFGANG POROD*

Center for Nano Science and Technology, Department of Electrical Engineering,University of Notre Dame, Notre Dame, IN 46556

We present an analytical model for the I-V characteristics of a single-electron transistor,which may be incorporated in a conventional circuit simulator, such as SPICE. Our modeltakes as its input the physical SET characteristics (capacitances and tunnel resistances,which may be determined experimentally), and it yields !-V curves which are in excellentagreement with the ones obtained from full-scale Monte Carlo simulations.

Keywords: Nanoelectronics; Single-electron transistor; Coulomb blockade; Device simulation;Circuit simulation

INTRODUCTION

Single-electron transistors (SET) offer the promiseof ultra-high integration densities and ultra-lowpower consumption [1]. Considerable effort hasbeen expended over the past decade, or so, in theunderstanding of the physical principles of SEToperation, and this topic has reached a quitemature stage [2]. The fabrication technology ofSET’s has also come a long way, from itsbeginnings with individual metallic islands operat-ing at cryogenic temperatures, to device structuresapproaching room-temperature operation.The development of large-scale SET circuits will

require the development of simulation tools, andsome work has been done in this area inrecognition of this need [3-5]. Most simulationapproaches are based on the Monte Carlotechnique, and the main challenges is to reconcile

the numerical expense of this method with therequirement of an economical device model whichmay be used for the simulation of large circuits.

In this paper, we present an analytical model forthe I-V characteristics of a single-electron tran-sistor, which may be incorporated in a conven-tional circuit simulator, such as SPICE. Our modeltakes as its input the physical SET characteristics(capacitances and tunnel resistances, which may bedetermined experimentally), and it yields I-Vcurves which are in excellent agreement with theones obtained from full-scale Monte Carlo simu-lators, such as SIMON [6].

THE MODEL

On model is based on the schematic SET structureshown in Figure 1. Electrons may tunnel across the

*Corresponding author. Tel.: + 219 631 6376, Fax: + 219 631 4393, e-mail: [email protected]

189

Page 2: Analytic Model for Single-Electron Transistorsdownloads.hindawi.com/archive/2001/071879.pdf · Keywords: Nanoelectronics; Single-electron transistor; Coulomb blockade; Device simulation;

190 X. WANG AND W. POROD

Vg

Cd, Rd

CgCs, Rs

FIGURE SET schematic with source (s), drain (d), and gate(g) contracts. The source (drain) tunnel junctions are char-acterized by junction capacitances Cs (Cd) and tunnelresistances Rs (Rd). The gate contact is capacitively coupled(Cg) to the central island.

source and drain junctions, and these tunnelingrates la are given by the "orthodox theory" ofsingle-electron tunneling.

-AEre2 "RT exp(AE/kBT)’ (1)

where AE Eafte -Ebefore is the change in the freeenergy during a tunneling event.The main insight of our work is that out of all

many possible tunnel events which contribute tothe current (and which are included in the fullMonte Carlo models), only a few are truly sig-nificant and need to be considered. Specifically,current across the SET may be viewed as thecombined process of an electron tunneling firstacross the source- and then the drain junction(with rates las and lad respectively). The currentthen can be written as:

las" lad (2)I‘1s e.ps + la‘1

where the rates (within the "orthodox theory")are analytic functions of the SET parametersand the applied biases, Va and Vgs. Specifically,the rates given by the changes in energy whichcan be expressed as junction charges in the

following way:

eAEs ---7. Qs with

(Ca + Cg/2) V‘1, + Cg Vgs el2 + Qo

(3)e

AEa --. Q‘1 with

0,t (Cs + Cg/2) V& + Cg Vg el2 + Oo(4)

In the above expressions, C is the sum of allcapacitances and Q0 represents some backgroundcharge.

This model is valid a long as the central islandhas one extra electron, i.e., the one that carries thecurrent. The range of validity of the model can beexpressed as:

O<Qs<e and O<Qa<e (5)

For bias conditions outside this range of validity,a straightforward extrapolation procedure maybe applied for the rates, and thus the current.More details can be found in a forthcoming pub-lication [7].

RESULTS

Figure 2 shows the result of this model forsymmetric SET structure (i.e., source and drainjunctions with identical parameters; for thisexample, we chose values of Cg 5 aF, Cs Ca=aF, R-Ra= 100 Mf, and the temperature was

assumed to be T- 3 K). The lower panels show thetunneling rates and the upper panels the respectiveresulting drain currents, according to Eq. (2), as afunction of the gate bias with the drain bias heldconstant (Va 30 mV). The solid line in the upperpanels, which is the same in (a) and (c), shows thecurrent obtained from the full Monte Carlosimulation using SIMON [6]. The range of validityof the above model (i.e., only one electron hopsacross the island) is indicated by the full circles,and the open circles indicate the presence of more

Page 3: Analytic Model for Single-Electron Transistorsdownloads.hindawi.com/archive/2001/071879.pdf · Keywords: Nanoelectronics; Single-electron transistor; Coulomb blockade; Device simulation;

SINGLE-ELECTRON TRANSISTORS 191

x 10-11

8

7

6

!3p-..i !.o. ...i ..| Vdsi=30m:V

2- ,,,(a) -0.04 -0.02 0 0.02 0.04

x 10-11

8

7

6

5

4

3

2(c) -0.04 -0.02 0 0.02 0.04

0.5

x 109Source

o: o% J. oo o.-., ,0: .... ;o- % ,.o&" -,,,0 :...’,,’....’.. ;,....., ,. .-...; ,, ,....

oO %00 \ %:o Drain o

0 0

X 109Source

/%o. ..o.o..r .. o,..; -., =,,:: .-.. ..’... ok.’,, " ":

,o o. .. o,# .%Drain

-0.04 -0.02 0 0.02 0.04 -0.04 -0.02 0 0.02 0.04

(b) Vgs (V) (d) Vgs (V)

FIGURE 2 The dots in the upper panels, (a) and (c), show the SET current according to Eq. (2) for the rates in the respective lowerpanels, (b) and (d); the solid line, which is the same in (a) and (b), shows the current obtained from the full Monte Carlo simulationsusing SIMON [6]. The range of validity of the basic model (inequalities (5)) is indicated by the full circles, and the open circlesindicate that the rates need to be modified. A simple extrapolation procedure (compare (b) and (d)) yields excellent agreementbetween our simple analytical model and the full Monte Carlo simulations, as can be seen in panel (d).

x 10-1

20 mV,

lOmV 1.5

0.5

30m20 mV

Yds 10 mV

-0.04 -0.02 0 0.02 0.04 -0.04 0 0.04 0.08 0.12

(a) Vgs(V) (b) Vgs(V)FIGURE 3 Comparison of our analytical model (symbols) and the full Monte Carlo simulations using SIMON [6] (solid lines) forboth a symmetrical SET structure, shown in panel (a), and an asymmetrical SET structure, shown in panel (b).

than the one extra electron on the island. Panel (a)shows that simpy using the rates of the "orthodoxtheory" gives exellent agreement with SIMON

when only one extra electron carries the current

(full circles), but underestimates the current whenthere are extra electrons involved (open circles).

Page 4: Analytic Model for Single-Electron Transistorsdownloads.hindawi.com/archive/2001/071879.pdf · Keywords: Nanoelectronics; Single-electron transistor; Coulomb blockade; Device simulation;

192 X. WANG AND W. POROD

It is clear that the rates outside the range ofvalidity of out model (open circles) have to bemodified, and we chose the simplest modificationof simply leaving them constant. Panel (d) showsthe modified rates according to this simpleextrapolation, which takes the flow of extraelectrons into account. The resulting current is inexcellent agreement with the full Monte Carlosimulator, as can be seen in panel (c).

Figure 3 shows the results of our model forseveral drain biases and for symmetrical andasymmetrical junctions. Figure 3(a) shows theresults for a symmetrical SET with the follow-ing parameters: Cg 3.2 aF, Cs Cd= 1.6 aF,Rs=Rd=IOOMf; and Figure 3(b) is for anasymmetrical SET with parameter values of:Cg 3.2 aF, C 2.4 aF, Cd-- 1.6 aF, R 80 Mf,Rd= 100 Mft. The predictions of our unmodifiedmodel are indicated by the full dots (relations (5)are satisfied) and the open circles indicate themodification due to the extrapolation of the rateswhen inequalities (5) are not valid. The solid linesare the results for SIMON. We find excellentagreement between our simple analytical modeland full-scale Monte Carlo simulations.

SUMMARY

We have found that a simple analytical model forthe I-V characteristics of a single-electron tran-sistor yields excellent agreement with full-scaleMonte Carlo simulations. Our model is based on

the physical picture that the SET current is

primarily carried by one extra electron on the

central island and with tunneling rates which are

given by the "orthodox" theory of single-electronphenomena. When more events need to beconsidered, i.e., inequalities (5) are no longersatisfied, straightforward extrapolation proceduresmay be applied, which yield excellent agreementwith Monte Carlo simulators, such as SIMON.Our I-V model is sufficiently simple to make it

useful for circuit simulations. We have alreadyincorporated it in standard SPICE simulators, andthese results will be presented elsewhere [7].

Acknowledgement

This work was supported by the US Office ofNaval Research.

References

[1] Likharev, K. K. (1987). 1EEE Trans. Magn., 23, 1142.[2] Averin, D. A. and Likharev, K. K. (1992). Possible

Applications of Single Charge Tunneling, Chapter 9 inSingle Charge Tunneling: Coulomb Blockade Phenomenain Nanostructures, Eds. Grabert, H. and Devoret, M. H.Plenum Press, NATO ASI Series B: Physics, 294.

[3] Fujishima, M., Amakawa, S. and Hoh, K. (1998). CircuitSimulators Aiming at Single-Electron Integration, Jpn.J. Appl. Phys., 37, 1478-1482.

[4] Kirihara, M. and Taniguchi, K. (1998). Hybrid CircuitSimulator for Combined Single Electron and ConventionalCircuit Elements, Proceedings of the Osaka IWCE, p. 21;Kirihara, M., Nakazato, K. and Wagner, M. (1999).Hybrid Circuit Simulator Including a Model for SingleElectron Tunneling Devices, Jap. J. Appl. Phys., 38, 2028.

[5] Yu, Y. S., Hwang, S. W. and Ahn, D. (1999). Macro-modeling of Single-Electron Transistors for EfficientCircuit Simulation, IEEE Trans., ED-46, 1667-1671.

[6] Wasshuber, C., Kosina, H. and Selberherr, S. (1997).SIMON A Simulator for Single-Electron Tunnel Devicesand Circuits, IEEE Trans. CAD, 16, 937.

[7] Wang, X. and Porod, W., manuscript in preparation.

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