the drs2 chip: a 4.5 ghz waveform digitizing chip for the meg experiment stefan ritt paul scherrer...

The DRS2 Chip: A 4.5 GHz Waveform Digitizing Chip for the MEG Experiment

Stefan RittPaul Scherrer Institute, Switzerland

19 Oct. '04 IEEE/NSS Rome 2004 2

The MEG Experiment at PSI

1m

e+

Liq. Xe Scin tilla tionDetector

Drift C ham ber

L iq . Xe Scin tilla tionDetector

e+

Tim ing C ounter

Stopping TargetThin S uperconducting Coil

M uon Beam

Drift C ham ber

• Stopped beam of 107-108 s-1, 100% duty factor

• Liquid Xe calorimeter for detection

• Solenoidal magnetic spectrometer

• Radial drift chambers for e+

momentum determination

• Timing counter for e+

• Stopped beam of 107-108 s-1, 100% duty factor

• Liquid Xe calorimeter for detection

• Solenoidal magnetic spectrometer

• Radial drift chambers for e+

momentum determination

• Timing counter for e+

Ee = 52.8 MeV

Kinematics e= 180°

Eg = 52.8 MeV

e

97 98 99 00 01 02 03 04 05 06 07

Planning R & D Assmbl. Data Taking

Goal: → e at 10-13

N7-4

T. Iawamoto

N7-4

T. Iawamoto


Waveform Digitizing

Needed:• Pile-up rejection (BG from 108 µ

decays in unsegmented calorimeter)

• ADC dynamic range of 12 bit• TDC resolution of 40 ps• Analog pipeline (L1 trigger)

~300ns• 3000 channels

Needed:• Pile-up rejection (BG from 108 µ

decays in unsegmented calorimeter)

• ADC dynamic range of 12 bit• TDC resolution of 40 ps• Analog pipeline (L1 trigger)

~300ns• 3000 channels

t

PMTsum

51.5 MeV

0.511 MeV

~100ns

2 GS10 Bit

100€/Chn


The DRS chip: principle of operation

0.2-1 ns Inverter (“Domino”) chain Rotatingsignal

Input 1

Output 1

40 MHz

Input 2

Channels3 to 10

Output 2

Domino Ring

Sampler

Domino Ring

Sampler


Design of Inverter Chain

PMOS > NMOS

PMOS < NMOS


“Tail Biting”

enable

1 2 3 4

1

2

3

4


Domino Speed Control

UR US UR US

•Two independent voltages to control domino wave speed

•UR used to select speed range

•Us used for fine-adjustment

•Need to compensate temperature and Vdd drifts

•Two independent voltages to control domino wave speed

•UR used to select speed range

•Us used for fine-adjustment

•Need to compensate temperature and Vdd drifts


Current mode readout

• First implemented in DRS2 (DRS1 had charge readout)

• Sampled charge does not leave chip

• Current readout less sensitive to charge injection and cross-talk

• First implemented in DRS2 (DRS1 had charge readout)

• Sampled charge does not leave chip

• Current readout less sensitive to charge injection and cross-talk

write

read

C (200fF)

. . .

R(700 )I

VoutVin


Timing Reference

signal

20 MHz Reference clock

PMT hit

Domino stops aftertrigger latency

8 inp

uts

shift registerReference

clock

domino wave

MUX

Domino speed stability of 10-3 : • 400 ps uncertainty for full window• 25 ps uncertainty for timing relative to edge

Domino speed stability of 10-3 : • 400 ps uncertainty for full window• 25 ps uncertainty for timing relative to edge


The DRS2 Chip

• Fabricated in 0.25 m 1P5M MMC process (UMC), 5 x 5 mm2

• Radiation Hard (CMS Pixel library, R. Horisberger)

• 10 channels (8 data + 2 calibration), each 1024 bins (300 ns analog delay + 100 ns signal at 2.5 GHz)

• Maximal sampling speed 4.5 GHz

• Readout speed 40 MHz

• Submitted to UMC in November 2003, 58 chips (400 channels) received in March 2004

• Packaged chip costs:

• 35 € / chn. (MPW run)

• 3 € / chn. (engineering run)

• Fabricated in 0.25 m 1P5M MMC process (UMC), 5 x 5 mm2

• Radiation Hard (CMS Pixel library, R. Horisberger)

• 10 channels (8 data + 2 calibration), each 1024 bins (300 ns analog delay + 100 ns signal at 2.5 GHz)

• Maximal sampling speed 4.5 GHz

• Readout speed 40 MHz

• Submitted to UMC in November 2003, 58 chips (400 channels) received in March 2004

• Packaged chip costs:

• 35 € / chn. (MPW run)

• 3 € / chn. (engineering run)

DominoCircuit

ReadoutShift

Register

10 channels x 1024 bins

DRS2 Test Results

Preliminary !


Measured DRS2 Parameters

•Linear response up to 400mV

•Usable range of 1V p-p

•Linear response up to 400mV

•Usable range of 1V p-p

•Speed range 0.5 GHz – 4.2 GHz

•Speed range 0.5 GHz – 4.2 GHz

Linear approximation


PLL Stabilization

PLL

ExternalCommonReference

Clock (1-4 MHz)

Vspeed

Reference ClockDomino Wave Pulse

~200 psec~200 psec

R. Paoletti, N. Turini, R. Pegna

MAGIC collaboration

R. Paoletti, N. Turini, R. Pegna

MAGIC collaboration

• Unstabilized jitter: ~70ps / turn

• Temperature coefficient: 500ps / ºC

• Unstabilized jitter: ~70ps / turn

• Temperature coefficient: 500ps / ºC


Frequency stabilization

Vspeed

16-bitDAC

LUT

FPGAFrequencyCounter

• Compensate for temperature drifts• Change Vspeed only between events,

keep stable during acquisition phase• Jitter ~ 150ps• Timing accuracy with 9th channel <

25ps

• Compensate for temperature drifts• Change Vspeed only between events,

keep stable during acquisition phase• Jitter ~ 150ps• Timing accuracy with 9th channel <

25ps

150ps


Estimated Bandwidth

• Input pulse rising time: 0.9 ns

• Sampled at 2.5 GHz: 0.4 ns / sample

• Reconstructed rise time: 3 samples → 1.2 ns

• Estimated BW » 500 MHz

• Limited by protection diodes

40 MHz readout clock

Direct DRS2 output


DAQ Boards

DRS

R. Paoletti, N. Turini, R. PegnaMAGIC collaboration

USB

PSI GVME Board

FPGA with4 Power-PC


Digitized Signals

• 7 ns pulses 500 mV

• Digitized at 2.5 GHz with USB test board

• 7 ns pulses 500 mV

• Digitized at 2.5 GHz with USB test board

• Pulses are nicely reproduced

• Analog inputs not properly terminated

• Non-constant response over 1024 cells (parasitic R of current readout on chip)

• Pulses are nicely reproduced

• Analog inputs not properly terminated

• Non-constant response over 1024 cells (parasitic R of current readout on chip)ns

mV


Signal-to-noise ratio

mV

mV

• 1 V DC input signal, common mode subtracted

• Individual bin has RMS of 2 mV → SNR = 500:1 (9 bit)

• Integration over 100 ns PMT pulse (250 bins) has RMS of0.16 mV → SNR = 6200:1 (12.6 bit)

• Could be improved by better analog design of Mezzanine board

• 1 V DC input signal, common mode subtracted

• Individual bin has RMS of 2 mV → SNR = 500:1 (9 bit)

• Integration over 100 ns PMT pulse (250 bins) has RMS of0.16 mV → SNR = 6200:1 (12.6 bit)

• Could be improved by better analog design of Mezzanine board


Waveform Analysis

•MEG: 3000 channels, 100 Hz, 1024 samples → 600 MB/sec

•Compress “interesting” and pile-up events in FPGA (→ 10x)

•Fit “background” events in PC farm (~10 PCs) with individual PMT response functions, derive multi-hit ADC and TDC data

•Overall data rate ~2 MB/sec

•MEG: 3000 channels, 100 Hz, 1024 samples → 600 MB/sec

•Compress “interesting” and pile-up events in FPGA (→ 10x)

•Fit “background” events in PC farm (~10 PCs) with individual PMT response functions, derive multi-hit ADC and TDC data

•Overall data rate ~2 MB/sec

Experiment500 MHz sampling


Next generation: DRS3

DRS1 DRS2 DRS3

Estimated

First tested November 02 March 04 Fall 05

Number of channels 1 10 10 (all differential)

Number of cells/channel 768 1024 1024-8192

MIN sampling speed (GHz) 0.7 0.5 0.5

MAX sampling sped (GHz) 2.5 4.5 4.5

Readout Speed (MHz) 20 40 40

Readout Dead Time (µsec) 40 256 (1024 samples) 10 (40 samples)

Signal to Noise ratio (bit) - > 12 (250 samples) > 12

Power Consumption (mW) 25 50 50

?


Conclusions

•Successful design of DRS2 with 8 x 1024 bins, running at 4.5 GHz

•Deploy ~200 channels in MEG Experiment in spring 2005

•Use DRS2 for drift chamber readout

•Final version (DRS3, 3000 channels) in 2006

•Not specific to MEG, useful for other experiments

•Successful design of DRS2 with 8 x 1024 bins, running at 4.5 GHz

•Deploy ~200 channels in MEG Experiment in spring 2005

•Use DRS2 for drift chamber readout

•Final version (DRS3, 3000 channels) in 2006

•Not specific to MEG, useful for other experiments

the drs2 chip: a 4.5 ghz waveform digitizing chip for the meg experiment stefan ritt paul scherrer...

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