synchronous sequential design · synchronous sequential design smd098 computation structures...

SMD098 Computation Structures Lecture 4 1

Synchronous Sequential Design Synchronous Sequential Design


Synchronous sequential systemsSynchronous sequential systems• Almost all digital systems have some concept of state the outputs of a system

depends on the past values of its inputs as well as the present values. Such systems are known as sequential systems, as opposed to combinational systems.

• A sequential system be

– Asynchronous. The next state is updated as soon as the next state changes (there is no clock signal)

– Synchronous. The next state is only updated when a clock signal changes

Simple model of a synchronous sequential system


Why synchronous?Why synchronous?

• Signals are sampled at well-defined time intervals. Problems with speed variation through different paths of logic, short and long paths, can “easily” be avoided. Glitches caused by dynamic and static hazards have no effect since the data is sampled only after the glitches have had a chance to settle out

• Asynchronous designs do not operate with a clock. Relies on handshaking between logic. Sensitive to glitches and ordering of signals

• Works well under variations of temperature, voltage and process. Changing an asynchronous design from a .5 micron process to a .18 micron process will change the timing of the design. The result will most likely be that the new design will not work as intended

• Interfacing two synchronous blocks is simple. Interfacing asynchronous blocks is not simple

• Synthesis and other tools does not handle asynchronous logic very well. Designing asynchronously puts much higher demands on the designer


Never asynchronous? Never asynchronous?

• Asynchronous designs can sometimes be motivated. Asynchronous design can be faster and consume less power if designed correctly. But it is difficult -“Only idiots and geniuses designs asynchronously”. I don’t consider myself to be an idiot or a genius…

• Interfacing asynchronous input signals is unavoidable in many designs• Interfacing clock domains that are asynchronous relative to each other is

common. See lab 3.3, asynchronous FIFO

Synchronous is simple - keep it simple!Asynchronous interfaces needs special attention.

Synchronous is simple - keep it simple!Asynchronous interfaces needs special attention.


Finite State Machines Finite State Machines -- FSMFSM

Next State Logic

Inputs

State Register

OutputLogic

Moore outputs

Moore

Next State Logic

Inputs

State Register

OutputLogic

Mealy outputs

Mealy

Moore FSM: Outputs are a function of the current state

Mealy FSM: Outputs are a function of the current state and inputs. Wehave combinational paths through the FSM.


State machinesState machines

Next State Logic

Inputs

State Register

OutputLogic

Mealy outputs

Combined Mealy / MooreOutputLogic

Moore outputs

Next State Logic

Inputs

State Register

Registered output FSM

Registered outputs

Next OutputLogic

OutputRegister

Combined Mealy / Moore FSM

Registered output FSM. Outputs are registered, which prevents output glitches. Output glitches may not matter though


Example from text book Example from text book –– Low end traffic light controllerLow end traffic light controller

Moore outputsMoore outputs

Mealy outputMealy outputInputInput

A combined Mealy/Moore FSM

State nameState name

The diagram shown is probably what you are used to see from the Digital Design course, but here you will also learn the Algorithmic State Machine (ASM) chart representation


Algorithmic State Machines (ASM)Algorithmic State Machines (ASM)

• State box. A state takes exactly one clock cycle to complete. If a signal has no value associated to it (Y) it is logic one and logic zero elsewhere. The notation ZÄ 1 means that the signal is assigned at the end of the state, during the next clock cycle, and holds its value until otherwise set elsewhere.

• Decision box. Must follow and be associated with a state box. The decision is made base upon one or more input signals in same cycle as the other actions of the state.

• Conditional output box. Must follow a decision box. The outputs are asserted in the same clock cycle as those in the state box to which it is attached. The output signals are Mealy outputs since they depend on the present state as well as the inputs.


ASM chart for traffic light controllerASM chart for traffic light controller

1 clock cycle

In the digital course you should have learned how to manually obtain a hardware implementation of a FSM from a chart representation. If you have not or have forgotten read chapter 5.4.1 in the text book


State encodingState encoding

State encoding - the way binary numbers are assigned to states. You may define your own encoding or let the synthesis tool define it

Common encoding formats:

0 0000 0000 00000000000000011 0001 0001 00000000000000102 0010 0011 00000000000001003 0011 0010 00000000000010004 0100 0110 00000000000100005 0101 0111 00000000001000006 0110 0101 00000000010000007 0111 0100 00000000100000008 1000 1100 00000001000000009 1001 1101 0000001000000000

10 1010 1111 000001000000000011 1011 1110 000010000000000012 1100 1010 000100000000000013 1101 1011 001000000000000014 1110 1001 010000000000000015 1111 1000 1000000000000000

Binary GrayNo. One-hot

There is no known method for determining in advance which state assignment/encoding is best in the sense of giving simplest next state logic.

There is no known method for determining in advance which state assignment/encoding is best in the sense of giving simplest next state logic.


State assignment guide linesState assignment guide lines

• We should always provide some means of initializing the state machine when power is applied. This can be done with asynchronous sets or resets. However, do not use asynchronous resets sets that are sourced from internal combinational logic (more about this later).

• Minimizing the number of flip-flops is not necessarily good. The states may have some particular. For instance a state variable may be set in one state but in no others. This may result in simple output logic, but non-minimal number of flip-flops.

• One-hot encoding allow very simple and fast next state logic. In FPGAs there is a large number of flips-flops. If the flip-flops are not use they are wasted, so one-hot encoding is often used in FPGA implementations.

• For some reason1 we may want to minimize the number of state bits that changes between each state then Gray coding should be chosen. Note that it is not meaningful if we for instance have an FSM where each state can transition to any other state.

1. “Some” reason may be power minimization or reducing the probability of entering an erroneous state for an FSM with asynchronous inputs


Safety critical systemSafety critical system

For a safety critical system there should be logic that detects if an FSM has entered an illegal state. When an illegal state is entered the FSM should be reset.

For instance we may have an FSM with five states with binary encoding (23 = 8) . Then there are three illegal states that the FSM should never enter (but it may due to for instance alpha particles).

What is a safety critical system?


State encoding in VHDLState encoding in VHDLUsing an enumerated type, synthesis tool will decide encoding:

architecture Enc1 of StateMachine is type State is ( Idle, S1, S2, S3, S4, S5 ); signal PresentState, NextState : State;

begin . . .end architecture Enc1;

Using constants to represent states. If this is done make sure you turn off any synthesis FSM optimization, since the synthesis tool may re-encode the states.

architecture Enc2 of StateMachine is

-- One-hot constant Idle : std_logic_vector(2 downto 0) := "000001"; constant S1 : std_logic_vector(2 downto 0) := "000010"; constant S2 : std_logic_vector(2 downto 0) := "000100"; constant S3 : std_logic_vector(2 downto 0) := "001000"; constant S4 : std_logic_vector(2 downto 0) := "010000"; constant S5 : std_logic_vector(2 downto 0) := "100000";

signal PresentState, NextState : std_logic_vector(2 downto 0); begin . . .end Enc2;


Example Moore FSMExample Moore FSM

Next State Logic

Inputs

State Register

OutputLogic

Moore outputs

Moore

library ieee;use ieee.std_logic_1164.all;

entity StateMachine isport (Clk, Reset : in std_logic;A, B : in std_logic;Y : out std_logic_vector(2 downto 0));

end StateMachine;

architecture Moore of StateMachine istype State is ( Idle, S1, S2, S3, S4, S5 );signal PresentState, NextState : State;

begin-- rest of code goes here

end architecture Moore;

PresentStateNextStateA, B

Y


Example Moore FSMExample Moore FSM

Learn both types of representations!


Moore FSM Moore FSM –– threethree--process modelprocess model

Output : process(PresentState)begin

case PresentState iswhen Idle =>Y <= "000";

when S1 =>Y <= "101";

when S2 =>Y <= "111";

when S3 =>Y <= "011";

when S4 =>Y <= "110";

when S5 =>Y <= "000";

end case;end process;

FFs: process(Clk, Reset)begin

if Reset = ’1’ thenPresentState <= Idle;

elsif rising_edge(Clk) then

PresentState <= NextState;

end if;end process;

NxtState: process(A, B, PresentState)begin

case PresentState iswhen Idle =>

NextState <= S1;when S1 =>if A = ’1’ thenNextState <= S2;

elseNextState <= S1;

end if;when S2 =>if A = ’0’ and B = ’1’ thenNextState <= S3;

elsif A = ’1’ and B = ’1’ thenNextState <= S4;



end if;when S3 =>NextState <= S4;

when S4 =>NextState <= S5;

when S5 =>NextState <= Idle;


Next State Logic

Inputs

State Register

OutputLogic

Moore outputs


Moore FSM Moore FSM –– twotwo--process model process model verver. 1. 1

process(PresentState)begin

case PresentState iswhen Idle =>Y <= "000";

when S1 =>Y <= "101";

when S2 =>Y <= "111";

when S3 =>Y <= "011";

when S4 =>Y <= "110";

when S5 =>Y <= "000";


process(Clk, Reset)begin


elsif rising_edge(Clk) thencase PresentState iswhen Idle =>PresentState <= S1;

when S1 =>if A = ’1’ then

PresentState <= S2;else

PresentState <= S1;end if;

when S2 =>if A = ’0’ and B = ’1’ then

PresentState <= S3;elsif A = ’1’ and B = ’1’ then

PresentState <= S4;elsif A = ’1’ and B = ’0’ then

PresentState <= S5;else

PresentState <= S2;end if;

when S3 =>PresentState <= S4;

when S4 =>PresentState <= S5;

when S5 =>PresentState <= Idle;

end case;end if;

end process;Next State

Logic

Inputs

State Register

OutputLogic

Moore outputs


Moore FSM Moore FSM –– twotwo--process model process model verver. 2. 2

StateFFs: process(Clk, Reset)begin


elsif rising_edge(Clk) thenPresentState <= NextState;

end if;end process StateFFs;

CombLogic: process(A, B, PresentState)begin

case PresentState iswhen Idle =>NextState <= S1;Y <= "000";

when S1 =>if A = ’1’ thenNextState <= S2;


end if;Y <= "101";

when S2 =>if A = ’0’ and B = ’1’ thenNextState <= S3;




end if;Y <= "111";

when S3 =>NextState <= S4;Y <= "011";

when S4 =>NextState <= S5;Y <= "110";

when S5 =>NextState <= Idle;Y <= "000";


Next State Logic

Inputs

State Register

OutputLogic

Moore outputs

Use one of the three different models for describing your FSMs.


Combined Mealy/Moore FSM codingCombined Mealy/Moore FSM coding

process(Clk, Reset)begin


elsif rising_edge(Clk) thenPresentState <= NextState;

end if;end process;

process(Car, Timed, PresentState)begin

StartTimer <= ’0’; -- Default outputcase PresentState iswhen S1 =>MajorGreen <= ’1’;MinorGreen <= ’0’;if Car = ’1’ thenStartTimer <= ’1’; -- Mealy outputNextState <= S2;

elseNextState <= 1;

end if;when S2 =>MajorGreen <= ’0’;MinorGreen <= ’1’;if Timed = ’1’ thenNextState <= S1;


end if;end case;

end process;

Next State Logic

Inputs

State Register

OutputLogic

Mealy outputs

Combined Mealy / MooreOutputLogic

Moore outputs


Synplify and FSM encodingSynplify and FSM encodingSynplify Pro have a FSM compiler. It automatically detects state machines in the source code. The FSMs are implemented with either sequential, gray or one-hot encoding.

architecture Synplify of StateMachine is type State is ( Idle, S1, S2, S3, S4, S5 ); signal PresentState, NextState : State;

attribute syn_encoding : string; attribute syn_encoding of PresentState : signal is "onehot";

begin . . .end architecture Synplify;

architecture SynplifySafe of StateMachine is type State is ( Idle, S1, S2, S3, S4, S5 ); signal PresentState, NextState : State;

attribute syn_encoding : string; attribute syn_encoding of PresentState : signal is "onehot, safe";

begin . . .end architecture SynplifySafe;

To implement “safe” FSMs the attribute should be changed to


Synplify FSM Compiler and ExplorerSynplify FSM Compiler and ExplorerUse the FSM viewer in Synplify! You may even do so before simulation.

If FSM Explorer is enabled Synplify tries to find the optimal state encoding. The FSM Compiler uses a “default” encoding.

In simulation make sure you trace the state signal in the waveform view. You will see the name of the enumerated type (i.e. “S3”) in the waveform viewer.


FSM partitioning and linked FSM partitioning and linked FSMsFSMsDo not design “too” large FSMs. Break down large complicated control paths in to more manageable pieces. For instance you may have one master FSM and one or more slave FSMs or two or more FSMs that execute serially.

Note that this example is no standard solution. There exist many more configurations for partitioned FSMs.

As in many other cases it is very hard to find the optimal solution. But there are bad and good designs.


Data path / control path partitioningData path / control path partitioning

Advantages

• A better structural and logic decomposition of a system• Design reuse of common data path blocks• Efficient for CAD tools. Simplifies synthesis, place and route.

It is not sufficient to describe a sequential systems with one or more FSMs. It is common practice to partition a system in to control and data paths.


Simple example of data/control path partitioningSimple example of data/control path partitioning

Data andcontrol path

Extracted control path

Data and control path structurally separated. Separate VHDL entities!

X[3:0]

B[3:0]ShiftLeft

Round

ShiftRight

Data path

FSM

MuxSelX0

Control Path

ResetClock

Clock


A more complex data pathA more complex data path

Register file Branchlogic

Sgn/Ze extend

Zero ext.

Instruction memory Data memory

ALU

A

B

31

0

4+

+

= =

= =

The pipelined MIPS architecture used in SMD082. Notice the clear definition of synchronizers (D flip-flops) that makes it easy to analyze the data path. Feed back paths are always synchronized!

The SMD082 models of memories (register file, instr. and data memory) are simplified models. Don’t try to implement this data path directly!


What to do before you start to code!What to do before you start to code!

• What are the design specification? Make sure you fully understand this

• Next sit down an plan your design. Take a piece of paper and sketch your solution

• Partition the design into data and control paths• Define which units are clocked and which are combinational

• Use hierarchy when needed

• When this is done start coding in VHDL - not before!

When coding VHDL for synthesis it is not like you are using in any other programming language. Remember that it is hardware you want to implement - so think hardware! This is much easier if plan your design.


Synchronous design timingSynchronous design timing• Combinational loops• Long paths, short paths, false paths, multicycle paths

• Clock skew, race hazards

• Global clock and clock enables

• Asynchronous reset, synchronous reset or no reset?

• Asynchronous inputs, synchronizers and metastability• Crossing clock domains


WazzupWazzup??


Combinational loopsCombinational loops

Combinational loops are a “no-no” in a synchronous digital design. Unexpected behavior may result. There may be a parasitic latch or even an oscillator. The result is simply unpredictable.

Fix – break every combinational loop with a synchronizer, i.e. a flip-flop. How would you do in this case?


Timing of a positive edge triggered D flipTiming of a positive edge triggered D flip--flopflop

• Setup time, tsetupThe time the D input must be stable before the rising edge of the flip-flop (assuming a positive edge triggered flip-flop)

• Hold time, tholdThe time the D input must be stable after the rising edge of the clock

If the setup or hold time parameters are violated the Q output will be either logic 0, logic 1 or the flip-flop will enter a metastable state, but will eventually become a valid logic level.

setupt holdt1, 0 or metastable!

D

Clk

Q


Positive edge triggered flipPositive edge triggered flip--flopflop

pLH(CQ)t pHL(CQ)t

setupt

holdt

1, 0 or metastable!

D

Clk

Q

• Clock-to-output delay, tpThe delay of a low to high transition and the delay of a high to low transition may be different. We use the worst case when analyzing timing of circuits.


What is the maximum clock frequency?What is the maximum clock frequency?

D Q

Clk

D Q

FF1 FF2

Logic

Routing delays and clock skew are not taken into account

pFF1t Logict setupFF2t+ +

1f =


Timing constraints for a synchronous designTiming constraints for a synchronous design

D Q D Q D QCL1 CL2

CL = Combinatorial LogicBUFG

IOBFF IOBFFCLBFF

Xilinx FPGA

D Q Delay

Clock

Delay D Q

When we constrain a design for timing we rely on the tools to make sure that we don’t violate the setup and hold times. The constraints should at least be:

• The desired clock period (or frequency)

• Input arrival times relative to clock• Maximum output delay relative to clock

For Xilinx FPGAs always use the IOB flip-flops and always use the global buffers for clock routing


Long path and short pathLong path and short path

D Q

D QD Q

D Q

CL1CL2

5 ns1 ns

Long path - 6 ns

Short path - 1 ns

The long path or critical path of a design determines the maximum achievable clock frequency. But why do we have to worry about the short path?

D Q D Q

FF2FF1 Short path

t short

t skew

For proper operation the following must be satisfied:

t short t skewt pFF1 t hFF2+ +>

or else we will get hold time violations for FF2. As you can see the relationship does not depend on the clock period


Clock skew and race hazardsClock skew and race hazards

D Q

Clk1

D Q

FF1 FF2

Delay

IN

Clk2

Q1 Q2

IN

Clk1

Q1

Q2

Clk2

Ooops!

For proper function the following must be satisfied

pFF(min)t pLogic(min)t holdt skew(max)t+ - - > 0

The short path is important!


Clock skewClock skew

What if we route the clock in the opposite direction of the data flow? Then for proper operation we must have:

So this is better, but in most design you will have feedback paths so it is not possible to route the clock signal in the opposite direction of the data flow. Also clock skew will limit the maximum achievable clock frequency. So what is the solution?

Ensure that the clock skew between communicating registers is bonded.

For ASIC design this require careful design of the clock network. For FPGA design with Xilinx it is simple - use the global low skew clock nets. This ensures you that there will be no hold time violations, assuming you have one global clock. Use clock enable, instead of multiple clocks!

D Q D Q

FF2FF1 Short path

t short

t skewClock

t short t skewt pFF1 t hFF2+ + >


Clock treesClock trees

H-tree Balanced tree

Clock source Clock source

The delay from the clock source to each tree node should be matched as close as possible in order to reduce the clock skew.


(Unless you really know what you are doing.)


False paths False paths

EnA

EnB

A1

B1

EnA

A2

CL

EnB

B2

The paths A1 → B2 and B1 → A2 are false paths. These false paths can be excluded when performing timing driven optimization, such as synthesis and implementation. Depending on what tools are used a timing constraint should be set to indicate that the paths in fact are false paths.


Multi cycle paths Multi cycle paths

Consider this non-loadable pre-scaled counter

2 bit fastcounter

Widecounter

CarryOut

ClockEnable

Clock

The registers in the wide counter are enabled at a rate that is one fourth of the clock rate. Hence the timing constraint for the wide counter can be set to a clock rate corresponding to fclock/4. The combinatorial paths in the wide counter are multi cycle paths. The design tools do not automatically detect that so is the case, so a timing constraint, indicating the multi cycle paths must be set


Synchronization at the system levelSynchronization at the system level

Chip 1 Chip 2

D Q

DLL

D Q

DLL

Clock

A Delayed Locked Loop (DLL) can align internal and external clocks. Effectively eliminates on-chip clock distribution delay. This maximizes the achievable I/O speed.

Delay

Clock distribution

Comparator Error

Clock

Data

The Virtex FPGA have DLLs. The DLLs can also be used to divide or double incoming clock rate


Asynchronous reset/preset is dangerous... Asynchronous reset/preset is dangerous... Never glitch an asynchronous reset or preset. Use synchronous reset/preset if you generate the reset/preset signal from combinatorial logic

Counter

SomeThing

Clock

Q1

Q0

AsynchReset

Assume Q0: 1 � 0 and Q1: 0 � 1 (Q changes from 01 to 10). Variations in routing delay may cause a glitch.

Q0

Q1

Async. reset


Do all memory elements need a reset?Do all memory elements need a reset?

• Short answer - Nope!• FSMs must have a reset, so that when the chip is powered up the

FSM can enter a predefined state

• Data path registers usually do not need a reset. The control path “knows” when data path registers contents are valid.


Never synchronize an asynchronous input in more Never synchronize an asynchronous input in more than one placethan one place

Clock

D Q

SynchronizerAsynch input

FSM

D Q

Synchronizer

Bad!

Clock

D Q

SynchronizerAsynch input

FSM

Good!

Why?


Asynchronous inputsAsynchronous inputs

Asynchronous inputs are unavoidable in many applications. When an asynchronous input is synchronized to a clock there is always a risk that the synchronizing flip-flop will enter a metastable state, since the asynchronous input may change inside the setup/hold time window

In the metastable state the output of the flip-flop is undefined. The flip-flop will eventually settle to logic 1 or logic 0, but this must have happen before the next flip-flop will sample the signal or else we have a failure

1

0

Clock

t

Undefined


Where is metastability resolution time, maximum time the output can remain metastable without causing synchronizer failure. and are constants that depend on the electrical characteristics of the flip-flop.

is the frequency of the asynchronous input and is the frequency of the sampling clock

MetastabilityMetastability analysisanalysis

( )clockin

r

ffT

t

⋅⋅=

0

/expMTBF

τ

The Mean Time Between Failure of a synchronizer is determined by

rtτ 0T

inf clockf


MetastabilityMetastability analysis analysis -- exampleexample

Assume we have two identical flip-flops. Both flip-flops are clocked at 10 MHz and the synchronizing flip-flop is sampling an asynchronous 3 kHz input

τ

oT

sut

1 ns

5 10 s. 5

2 ns Clock

D Q D QCL

Synchronizer

Asynch input

Flip-flop in design13 ns

Resolution time: ( ) ns85ns2131001 =−−=−−= suCL

clockr tt

ft

( )years74.1s105.5

1031010105

85expMTBF 1320

365=⋅=

⋅⋅⋅⋅⋅=

Not that bad!


MetastabilityMetastability exampleexample

What happens if we increase the system clock to 20 MHz?

( ) ns35ns213501 =−−=−−= suCL

clockr tt

ft

( )s053.0

1031020105

35expMTBF

365=

⋅⋅⋅⋅⋅=

Not good at all!


Cascaded synchronizerCascaded synchronizer

It is possible to reduce the MTBF by using cascaded flip-flops as synchronizers

The critical input frequency to FF2 is the mean frequency of the MTBF for FF1

Clock

D Q D QCL

Synchronizer

Asynch input

Flip-flop in design13 ns

D Q

Routing delay 2 ns

FF1 FF2

( ) Hz2250exp

1031020105 365

2 −−⋅⋅⋅⋅⋅=inf

( )days8.5

1020105

35expMTBF

265

=⋅⋅⋅⋅

=inf

Changed from 0.05 s to about 6 days, but this is still not good enough. What can we do to further reduce the MTBF?


MetastabilityMetastability Recovery Recovery -- XAPP094 (1997)XAPP094 (1997)

1 2 3 4 5 6

0

1

-1

-2

-3

2

3

4

5

6

7

8

9

10

11

12

13

1 Million Years

1,000 Years

1 Year

XC4005E-3CLB

XC5206-5CLB

XC4005E-3IOB

XC3142A-09IOB

XC4005-6IOB

XC4005-6CLB

XC3142A-09CLB

XC3042-70IOB

XC3042-70CLB

1 Day

1 Hour

1 Minute

Acceptable Extra Delay (ns)

Log

Sec

onds

MTBF

X5986

Figure 2: Mean Time Between Failure for various IOB and CLB flip-flop outputs when synchronizing a ~1 MHzasynchronous input with a 10 MHz clock.


Crossing clock domainsCrossing clock domains

When clock A and clock B are totally independent, we are in trouble. There are no completely safe methods to transfer data between two unrelated clock domains. But there are good and bad solutions

One good solution: Carefully synchronize the handshaking signals at both ends. Use a toggle exchange protocol

HandShake A-B

Data A-B

HandShake B-A

Data B-A

Clock A Clock B

Clock Domain A Clock Domain B

Block A Block B

HandShake A-B

Data A-B

HandShake B-A

Valid Valid


Crossing clock domainsCrossing clock domains

In lab 3.3 you will use an asynchronous FIFO to synchronize sampled data from one clock domain to another. You will generate the FIFO with Xilinx CoreGenerator. The tricky part with the FIFO is the implementation of the twoFIFO flags, Empty and Full.

X5887

WE

WC

WE

READ ENABLE

READ CLOCK

WC

W3-0

R3-0

DUAL-PORTMEMORY

(XC4000E CLBs)

DATA OUTDATA IN

WRITE ENABLE

4

WRITE CLOCK

WRITE ADDRESS

READADDRESS

WRITECOUNTER

FULLLOGIC

DIR.LOGIC

FULL

READCOUNTER

EMPTYLOGIC

EMPTY

4

2

2

4

4

synchronous sequential design · synchronous sequential design smd098 computation structures...

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