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Download 1 SEQUENTIAL CIRCUITS DEFINITION OF SEQUENTIAL CIRCUIT SYNCHRONOUS SEQUENTIAL CIRCUIT ASYNCHRONOUS SEQUENTIAL CIRCUIT MEMORY ELEMENTS CLASSIFICATION: LATCHES

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1 SEQUENTIAL CIRCUITS DEFINITION OF SEQUENTIAL CIRCUIT SYNCHRONOUS SEQUENTIAL CIRCUIT ASYNCHRONOUS SEQUENTIAL CIRCUIT MEMORY ELEMENTS CLASSIFICATION: LATCHES AND FLIP-FLOPS LATCHES BASIC LATCH GATED LATCH EFFECT OF PROPAGATION DELAYS FLIP-FLOPS ASYNCHRONOUS SEQUENTIAL CIRCUIT ASYNCHRONOUS BEHAVIOR ANALYSIS OF ASYNCHROUNOUS CIRCUITS __________________________________________________ ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin. Revised 2005-02-14. Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill. Slide 2 2 DEFINITION OF SEQUENTIAL CIRCUIT CIRCUITS IN WHICH THE VALUES OF THE OUTPUTS DEPENT ON: THE PRESENT VALUES OF THE INPUTS THE PAST BEHAVIOR OF THE CIRCUIT ARE CALLED SEQUENTIAL CIRCUIT. IN SUCH CIRCUITS STORAGE ELEMENTS STORE THE VALUES OF THE SIGNALS. THE CONTENTS OF THE STORAGE ELEMENTS REPRESENT THE STATE OF THE CIRCUIT. THERE ARE TWO TYPES: SYNCHRONOUS, AND ASYNCHRONOUS Slide 3 3 DEFINITION OF SEQUENTIAL CIRCUIT SYNCHRONOUS SEQUENTIAL CIRCUITS: ARE SEQUENTIAL CIRCUITS CONTROLLED BY A CLOCK SIGNAL Combinational circuit Flip-flops Clock Q W Z Combinational circuit Slide 4 4 DEFINITION OF SEQUENTIAL CIRCUIT ASYNCHRONOUS SEQUENTIAL CIRCUITS: ARE SEQUENTIAL CIRCUITS: WITH NO CLOCK SIGNALS, NO FLIP-FLOPS TO STORE STATE VARIABLES Feedback signalGate-delay R S Q Yy Slide 5 5 MEMORY ELEMENTS EXAMPLES OF MEMORY ELEMENTS: AB AB Output Data Load TG1 TG2 Slide 6 6 MEMORY ELEMENTS CLASSIFICATION: LATCHES AND FLIP-FLOPS BASIC LATCH: is a feedback connection of two NOR gates or two NAND gates. GATED LATCH: is a basic latch that includes input gating and a control input signal. FLIP-FLOPS: is a storage element based on the gated latch principle which can have its output state changed only at the edge of the controlling clock signal. Slide 7 7 MEMORY ELEMENTS CLASSIFICATION: LATCHES AND FLIP-FLOPS (Continues) The state of the LATCH keeps changing according to the values of the input signals during the period when the clock is active. The state of the FLIP-FLOP changes only at the edge of the controlling clock signal. Slide 8 8 MEMORY ELEMENTS LATCHES: BASIC LATCH Slide 9 9 MEMORY ELEMENTS LATCHES: GATED RS LATCH Slide 10 10 MEMORY ELEMENTS LATCHES: GATED D LATCH Slide 11 11 MEMORY ELEMENTS EFFECT OF PROPAGATION DELAYS: Latch Setup and hold times. SETUP TIME: Minimum time that the D input signal must be stable prior to the negative (positive) edge of the Clk (clock) signal. HOLD TIME: Minimum time that the D input signal must remain stable after the negative (positive) edge of the Clk (clock) signal t su t h Clk D Q Slide 12 12 MEMORY ELEMENTS FLIP-FLOPS:They are storage elements that can change their state no more than once during one clock cycle. Two types: Master-Slave and Edge-triggered. Master-Slave Flip-flop: D Clock Q m QQ s = (b) Timing diagram D Q Q (c) Graphical symbol D Q Q MasterSlave D Q Q D Q Q Q m Q s (a) Circuit Clk Slide 13 13 MEMORY ELEMENTS FLIP-FLOPS (Continues). Edge-triggered Flip-flop D Clock P4 P3 P1 P2 5 6 1 2 3 (a) Circuit D Q Q (b) Graphical symbol Clock Q Q 4 Slide 14 14 MEMORY ELEMENTS INPUT/OUTPUT BEHAVIOR OF LATCHES AND FLIP-FLOPS* _______________________________________ * Contemporary Logic Design by R.H. Katz, Benjamin Cummings, 1994, page 290. TYPESWHEN INPUTS ARE SAMPLEDWHEN OUTPUTS ARE VALID UNCLOCKED LATCH (Basic latch) ALWAYSPROPAGATION DELAY FROM INPUT CHANGE LEVEL-SESITIVE LATCH (Gated latch) CLOCK HIGH t su, t h around falling clock edge PROPAGATION DELAY FROM INPUT CHANGE POSITIVE-EDGE FLIP-FLOPCLOCK LOW-TO-HIGH TRANSITION t su, t h around rising clock edge PROPAGATION DELAY FROM RISING EDGE OF CLOCK NEGATIVE-EDGE FLIP-FLOPCLOCK HIGH-TO-LOW TRANSITION t su, t h around falling clock edge PROPAGATION DELAY FROM FALLING EDGE OF CLOCK MASTER-SLAVE FLIP-FLOPCLOCK HIGH-TO-LOW TRANSITION t su, t h around falling clock edge PROPAGATION DELAY FROM FALLING EDGE OF CLOCK Slide 15 15 MEMORY ELEMENTS LEVEL-SENSITIVE VERSUS EDGE-TRIGGERED STORAGE ELEMENTS D Q Q D Q Q D Q Q D Clock Q a Q b Q c Q c Q b Q a Clk D Clock Q a Q b (b) Timing diagram Q c (a) Circuit Slide 16 16 MEMORY ELEMENTS FLIP-FLOPS (Continues) CHARACTERISTIC AND EXCITATION EQUATIONS OF D, T AND J-K FLIP-FLOPS TypeSymbolCharacteristicExcitation D-typeD Q + 0 1 Q Q + D 0 0 0 0 1 1 1 0 0 1 1 1 T-typeT Q + 0 Q 1 !Q Q Q + T 0 0 0 0 1 1 1 0 1 1 1 0 Q !Q D >Clk Q !Q T > Slide 17 17 MEMORY ELEMENTS FLIP-FLOPS (Continues) CHARACTERISTIC AND EXCITATION EQUATIONS OF D, T AND J-K FLIP-FLOPS TypeSymbolCharacteristicExcitation J-K-typeJ K Q + 0 0 Q 0 1 0 1 0 1 1 1 !Q Q Q + J K 0 0 0 x 0 1 1 x 1 0 x 1 1 1 x 0 SR-type (not in use; shown here for completeness) S R Q + 0 0 Q 0 1 0 1 0 1 1 1 Forbidden Q Q + S R 0 0 0 x 0 1 1 0 1 0 0 1 1 1 x 0 Q !Q J > K Clk S R Q !QClk > Slide 18 18 MEMORY ELEMENTS FLIP-FLOPS (Continues) FLIP-FLOP CONVERSIONS : Given a flip-flop as a buiding block, produce another type of flip-flop. APPROACH: Determine the input logic to the given flip-flop by satisfying the condition that both flip-flops must have identical logic behavior (their outputs are the same) Slide 19 19 MEMORY ELEMENTS FLIP-FLOP CONVERSIONS (Continues): Example: Produce the circuit of a J-K-type flip-flop using a T-type flip- flop as a building block and NAND gates as needed The corresponding circuit is shown on next slide J KQQ + JK Q+TQ+T T 0 0 1 1 0 1 0101010101010101 0100111001001110 0100111001001110 0001101100011011 T = J !Q + K Q Slide 20 20 MEMORY ELEMENTS FLIP-FLOP CONVERSIONS: Example (Continues): Circuit of a J-K flip-flop using a T flip-flop Slide 21 21 ASYNCHRONOUS SEQUENTIAL CIRCUIT IN SYNCHRONOUS SEQUENTIAL CIRCUITS A CLOCK SIGNAL CONSISTING OF PULSES, CONTROLS THE STATE VARIABLES WHICH ARE REPRESENTED BY FLIP-FLOPS. THEY ARE SAID TO OPERATE IN PULSE MODE. IN ASYNCHRONOUS CIRCUITS STATE CHANGES ARE NOT TRIGGERED BY CLOCK PULSES. THEY DEPEND ON THE VALUES OF THE INPUT AND FEEDBACK VARIABLES. TWO CONDITIONS FOR PROPER OPERATION: 1.-INPUTS TO THE CIRCUIT MUST CHANGE ONE AT A TIME AND MUST REMAIN CONSTANT UNTIL THE CIRCUIT REACHES STABLE STATE. 2.-FEEDBACK VARIABLES SHOULD CHANGE ALSO ONE AT A TIME. WHEN ALL INTERNAL SIGNALS STOP CHANGING, THEN THE CIRCUIT IS SAID TO HAVE REACHED STABLE STATE. WHEN THE INPUTS SATISFY CONDITION 1 ABOVE, THEN THE CIRCUIT IS SAID TO OPERATE IN FUNDAMENTAL MODE. Slide 22 22 ASYNCHRONOUS SEQUENTIAL CIRCUIT ASYNCHRONOUS BEHAVIOR Consider the Set-Reset latch. The gates shown below have no delay. Their delay (twice one-gate delay) is represented by the square. R S Q Yy (a)Circuit with modeled gate delay Slide 23 23 ASYNCHRONOUS SEQUENTIAL CIRCUIT ASYNCHRONOUS BEHAVIOR: Set-Reset latch (continues) The circuit behavior is represented by a State-assigned table or Flow table which show every possible transition of the circuit for each input value. Stable-states are those circled in the table because, while the inputs are stable, present state is equal to next state (internal variables stop changing). Columns with no circled sates indicate circuit oscillation for that particular input value. Figure 9.1. Analysis of the S-R latch. (b)State-assigned table Present Nextstate SR=00 011011 y YYYY 00010 11010 Slide 24 24 ASYNCHRONOUS SEQUENTIAL CIRCUIT ASYNCHRONOUS BEHAVIOR: Set-Reset latch (continues) FINITE-STATE-MACHINE MODEL: MOORE MODEL Figure 9.2. FSM model for the SR latch. MOORE MODEL (a)Statetable (b)Statediagram Present Nextstate Output state SR=00 011011 Q AAABA0 BBABA 1 10 00 11 01 00 10 A0 B1 11 01 SR Slide 25 25 ASYNCHRONOUS SEQUENTIAL CIRCUIT ASYNCHRONOUS BEHAVIOR: Set-Reset latch (continues) FINITE-STATE-MACHINE MODEL: MEALY MODEL (a) State Table (b) State Diagram Present NextstateOutput,Q state SR=00 01101100011011 AAABA000 BBABA11 10/1 00/1 11/0 01/0 00/0 10/ AB 01 11 SR/Q Slide 26 26 ASYNCHRONOUS SEQUENTIAL CIRCUIT ANALYSIS OF ASYNCHROUNOUS CIRCUITS PROCEDURE: CUT ALL FEEDBACK PATHS AND INSERT A DELAY ELEMENT AT EACH POINT WHERE CUT WAS MADE INPUT TO THE DELAY ELEMENT IS THE NEXT STATE VARIABLE Y i WHILE THE OUTPUT IS THE PRESENT VALUE y i. DERIVE THE NEXT-SATE AND OUTPUT EXPRESSIONS FROM THE CIRCUIT DERIVE THE EXCITATION TABLE DERIVE THE FLOW TABLE DERIVE A STATE-DIAGRAM FROM THE FLOW TABLE Slide 27 27 ASYNCHRONOUS SEQUENTIAL CIRCUIT ANALYSIS OF ASYNCHROUNOUS CIRCUITS: EXAMPLE D C Q Yy (a)Circuit Present Nextstate CD=00 011011 y YYYY Q 000010 111011 (b)Excitationtable Present Nextstate CD=00 011011Q AA A A B0 BB B AB 1 (c)Flowtable Slide 28 28 ASYNCHRONOUS SEQUENTIAL CIRCUIT ANALYSIS OF ASYNCHROUNOUS CIRCUITS: EXAMPLE CONTINUES Present Nextstate CD=00 011011Q AA A A B0 BB B AB 1 (c)FlowTable (d)StateDiagram: Moore Model x1 0x x0 0x 11 A0 B1 10 CD Slide 29 29 ASYNCHRONOUS SEQUENTIAL CIRCUIT SYNTHESIS OF ASYNCHROUNOUS CIRCUITS THIS TOPIC IS NOT COVERED IN THIS COURSE. IT BELONGS TO A MORE ADVANCED LOGIC DESIGN COURSE. THIS SUBJECT IS VERY IMPORTANT IN TODAYS DIGITAL SYSTEMS DESIGN BECAUSE CLOCKS ARE SO FAST THAT THEY PRESENT PROPAGATION DELAYS MAKING SUBSYSTEMS TO OPERATE OUT OF SYNCHRONIZATION. TECHNIQUES FOR SYNTHESIS OF ASYNCHRONOUS CIRCUITS INCLUDE THE HOFFMAN OR CLASSIC SYNTHESIS APPROACH HANDSHAKING SIGNALING FOR TWO SUBSYSTEMS TO COMMUNICATE ASYNCHRONOUSLY

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