chapter5: synchronous sequential logic – part 2

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Chapter5: Synchronous Sequential Logic – Part 2 Originally by Reham S. Al-Majed Imam Muhammad Bin Saud University

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Chapter5: Synchronous Sequential Logic – Part 2. Originally by Reham S. Al- Majed. Outline. Analysis of clocked SC Analysis with D FF. Analysis with JK FF. Analysis with T FF. Mealy and Moore Models of FSMs. SC Analysis. - PowerPoint PPT Presentation

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Page 1: Chapter5:  Synchronous Sequential Logic – Part 2

Chapter5: Synchronous Sequential Logic – Part 2

Originally by Reham S. Al-Majed

Imam Muhammad Bin Saud University

Page 2: Chapter5:  Synchronous Sequential Logic – Part 2

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Outline Analysis of clocked SC

Analysis with D FF. Analysis with JK FF. Analysis with T FF.

Mealy and Moore Models of FSMs.

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SC Analysis Analysis describes what a given circuit will do under certain

conditions. How changes in input with the current state will affect next state and

output.

Given: logic diagram of a SC consists of FF and gates.

Goal: 1. Find State Equations ( transition equations).

They describe the behavior of SC algebraically. They specify the next state as a function of the present state and inputs.

2. Find State Table. need state equations.3. Find State Diagram. need state table.

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SC Analysis To achieve any of the previous goals of SC Analysis we need to find:

Input equations( also called excitation equations): Boolean functions that describe the part

of the circuit that generate inputs to FF algebraically.

Output equations: Boolean functions that describe algebraically the part of the CC that

generate external output.

Characteristic equations of the used FF: The characteristic equation for the D FF:

Q(t+1) = D The characteristic equation for the JK FF:

Q(t+1)= JQ’+K’Q The characteristic equation for the T FF:

Q(t+1)= TQ

Input and output equations provide the necessary information to draw the logic diagram of SC.

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Example Find the input and output equations of the following SC logic diagram.

FFs input equations: DA= Ax + Bx

DB= A’x

Output equation: y=(A+B)x’

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SC Analysis To achieve the first goal ( finding state equations):

1. Determine input equations.

2. Substitute the input equations into FF characteristic equations to obtain the

next state of all FFs.

3. Write down the output equations.

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Example Analysis with D FF

Analyze the logic diagram by finding the state equations: FFs input equations:

DA= Ax + Bx

DB= A’x

The characteristic equation for D FF : Q(t+1) = D Substitute to find state equations:

A(t+1) = DA A(t+1) = Ax + Bx

B(t+1)= DB B(t+1) = A’x

Output equation: y=(A+B)x’

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SC Analysis To achieve the second goal ( finding state table)

1. After finding the state equations and output equations.

2. Draw a table that: Consists of four sections: present state, input, next state, and output. Has all possible binary combination of present states (#m) and inputs(#n) the

table has 2m+n rows. Fill the next state and output sections of the table according to

The state equations you obtained in step 1.

OR

The binary values of inputs to FFs along with characteristic table of a FF.

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Example Analysis with D FF

Analyze the logic diagram by finding the state table: From previous slide:

State equations:

A(t+1) = Ax + Bx B(t+1) = A’x

Output equation:

y=(A+B)x’

Page 10: Chapter5:  Synchronous Sequential Logic – Part 2

Another form of state table

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SC Analysis To achieve the third goal ( finding state diagram):

1. Draw circles that represent states of the FFs The number of circles you need depend on the number of the FFs the circuit

has if the SC has n FFs, then you need 2n circles/states. Each circle is labeled with a binary number that identifies the state of FFs.

2. Draw directed lines the connect circles according to the state table The source is the present state. The destination is the next state.

3. Label each line with two binary numbers separated by a slash. The first number is the input value during the present state. The second number is the output.

ABinput/output

AB

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Example Analysis with D FF

Analyze the logic diagram by finding the state diagram:

00

11

10

01

0/0 1/0

0/1

1/0 0/1 0/11/0

1/0

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Example Analysis with JK FF

Find state equations of the following SC logic diagram. FFs input equations:JA= B KA= Bx ’

JB= x’ KB= A The characteristic equation for D FF :Q(t+1)= JQ’+K’Q Substitute to find state equations:

A(t+1) = JAA’ +K’A A

A(t+1) = BA’ + (Bx’)’A = A’B+AB’+Ax

B(t+1) = JBB’ +K’B B

B(t+1) = x’B’ + (A)’ = B’x’ + ABx+ A’Bx’

Output equation: There is no external output .

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Example Analysis with JK FF

Find state table of the previous SC logic diagram. Fill Next state A, B from State equations:

A(t+1) = A’B+AB’+Ax

B(t+1) = B’x’ + ABx+ A’Bx’

OR

Use characteristics table of FF FFs input equations: JA= B KA= Bx ’

JB= x’ KB= A

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Example Analysis with JK FF

Find state table of the previous SC logic diagram. Fill Next state A, B from State equations:

A(t+1) = A’B+AB’+Ax

B(t+1) = B’x’ + ABx+ A’Bx’

OR

Use characteristics table of FF FFs input equations: JA= B KA= Bx ’

JB= x’ KB= A

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Example Analysis with JK FF

Find state diagram of the previous SC logic diagram.

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Exercise 1 Find the state equations, state table, and state diagram of the

following SC logic diagram.( page 219)

y

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Exercise 2 Find the state equations, state table, and state diagram of the

following SC logic diagram. (page 214)

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Mealy and Moore Models of FSM The most general model of SC has inputs, outputs, and internal states. However, there are two different models of SC:

The Mealy model: The output is a function of both the present state and the input.

The Moore model: The output is a function of only the present state.

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Mealy and Moore Models of FSM In Mealy model:

The outputs may change if the inputs change during the clock cycle outputs may have false values. Synchronize the inputs with a clock.

In Moore model: The outputs are synchronized with the clock since they

depend on FF outputs only.

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Mealy Model Example

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Moore Model Examples

y