Synchronous Sequential LogicChapter 5

Digital Circuits

5-1 IntroductionCombinational circuitscontains no memory elementsthe outputs depends on the inputs

Digital Circuits

5-2 Sequential Circuits Sequential circuits

a feedback paththe state of the sequential circuit(inputs, current state) (outputs, next state)synchronous: the transition happens at discrete instants of timeasynchronous: at any instant of time

Digital Circuits

Synchronous sequential circuitsa master-clock generator to generate a periodic train of clock pulsesthe clock pulses are distributed throughout the systemclocked sequential circuitsmost commonly usedno instability problemsthe memory elements: flip-flopsbinary cells capable of storing one bit of informationtwo outputs: one for the normal value and one for the complement valuemaintain a binary state indefinitely until directed by an input signal to switch states

Digital Circuits

Fig. 5.2Synchronous clocked sequential circuit

Digital Circuits

5-3 LatchesBasic flip-flop circuittwo NOR gates

more complicated types can be built upon itdirected-coupled RS flip-flop: the cross-coupled connectionan asynchronous sequential circuit(S,R)= (0,0): no operation(S,R)=(0,1): reset (Q=0, the clear state)(S,R)=(1,0): set (Q=1, the set state)(S,R)=(1,1): indeterminate state (Q=Q'=0)consider (S,R) = (1,1) (0,0)

Digital Circuits

SR latch with NAND gatesFig. 5.4SR latch with NAND gates

Digital Circuits

SR latch with control inputC=0, no changeC=1,S_R_0/11/S'1/R'Fig. 5.5SR latch with control input

Digital Circuits

D Latcheliminate the undesirable conditions of the indeterminate state in the RS flip-flopD: datagated D-latchD Q when C=1; no change when C=0Fig. 5.6D latchS_R_0/11/D'1/D

Digital Circuits

Fig. 5.7Graphic symbols for latches

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5-4 Flip-FlopsA triggerThe state of a latch or flip-flop is switched by a change of the control inputLevel triggered latchesEdge triggered flip-flops

Fig. 5.8Clock response in latch and flip-flop

Digital Circuits

If level-triggered flip-flops are usedthe feedback path may cause instability problemEdge-triggered flip-flopsthe state transition happens only at the edgeeliminate the multiple-transition problem

Digital Circuits

Edge-triggered D flip-flopMaster-slave D flip-floptwo separate flip-flopsa master flip-flop (positive-level triggered)a slave flip-flop (negative-level triggered)Fig. 5.9Master-slave D flip-flop

Digital Circuits

CP = 1: (S,R) (Y,Y'); (Q,Q') holdsCP = 0: (Y,Y') holds; (Y,Y') (Q,Q')(S,R) could not affect (Q,Q') directlythe state changes coincide with the negative-edge transition of CP

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Digital Circuits

Edge-triggered flip-flopsthe state changes during a clock-pulse transitionA D-type positive-edge-triggered flip-flop

Fig. 5.10D-type positive-edge-triggered flip-flop

Digital Circuits

three basic flip-flops(S,R) = (0,1): Q = 1(S,R) = (1,0): Q = 0(S,R) = (1,1): no operation(S,R) = (0,0): should be avoided

Fig. 5.10D-type positive-edge-triggered flip-flop

Digital Circuits

101!

Digital Circuits

The setup timeD input must be maintained at a constant value prior to the application of the positive CP pulse= the propagation delay through gates 4 and 1data to the internal latchesThe hold timeD input must not changes after the application of the positive CP pulse= the propagation delay of gate 3clock to the internal latch

Digital Circuits

SummaryCP=0: (S,R) = (1,1), no state changeCP=: state change onceCP=1: state holdseliminate the feedback problems in sequential circuitsAll flip-flops must make their transition at the same time

Digital Circuits

Other Flip-FlopsThe edge-triggered D flip-flopsThe most economical and efficientPositive-edge and negative-edgeFig. 5.11Graphic symbols for edge-triggered D flip-flop

Digital Circuits

JK flip-flop

D=JQ'+K'QJ=0, K=0: D=Q, no changeJ=0, K=1: D=0 Q =0J=1, K=0: D=1 Q =1J=1, K=1: D=Q' Q =Q'Fig. 5.12JK flip-flop

Digital Circuits

T flip-flop

D = TQ = TQ'+T'QT=0: D=Q, no changeT=1: D=Q' Q=Q'Fig. 5.13T flip-flop

Digital Circuits

Characteristic tables

Digital Circuits

Characteristic equationsD flip-flopQ(t+1) = DJK flip-flopQ(t+1) = JQ'+K'QT flop-flopQ(t+1) = TQ

Digital Circuits

Direct inputsasynchronous set and/or asynchronous reset

S_reset_Fig. 5.14D flip-flop with asynchronous reset

Digital Circuits

5-5 Analysis of Clocked Sequential CktsA sequential circuit(inputs, current state) (output, next state)a state transition table or state transition diagramFig. 5.15Example of sequential circuit

Digital Circuits

State equationsA(t+1) = A(t)x(t) + B(t)x(t)B(t+1) = A'(t)x(t)A compact formA(t+1) = Ax + BxB(t+1) = AxThe output equationy(t) = (A(t)+B(t))x'(t)y = (A+B)x'

Digital Circuits

State tableState transition table= state equations

Digital Circuits

State equationA(t + 1) =Ax + BxB(t + 1) = Axy = Ax + Bx

Digital Circuits

State diagramState transition diagrama circle: a statea directed lines connecting the circles: the transition between the statesEach directed line is labeled 'inputs/outputs

a logic diagram a state table a state diagramFig. 5.16State diagram of the circuit of Fig. 5.15

Digital Circuits

Flip-flop input equationsThe part of circuit that generates the inputs to flip-flopsAlso called excitation functionsDA = Ax +BxDB = A'xThe output equationsto fully describe the sequential circuit y = (A+B)x'

Digital Circuits

Analysis with D flip-flopsThe input equationDA=AxyThe state equationA(t+1)=AxyFig. 5.17Sequential circuit with D flip-flop

Digital Circuits

Analysis with JK flip-flopsDetermine the flip-flop input function in terms of the present state and input variablesUsed the corresponding flip-flop characteristic table to determine the next state

Fig. 5.18Sequential circuit with JK flip-flop

Digital Circuits

JA = B, KA= Bx'JB = x', KB = A'x + Axderive the state table

Or, derive the state equations using characteristic eq.

Digital Circuits

State transition diagramFig. 5.19State diagram of the circuit of Fig. 5.18State equation for A and B:

Digital Circuits

Analysis with T flip-flopsThe characteristic equationQ(t+1)= TQ = TQ'+T'Q

Fig. 5.20Sequential circuit with T flip-flop

Digital Circuits

The input and output functionsTA=BxTB= xy = ABThe state equationsA(t+1) = (Bx)'A+(Bx)A' =AB'+Ax'+A'BxB(t+1) = xB

Digital Circuits

State Table

Digital Circuits

Mealy and Moore modelsthe Mealy model: the outputs are functions of both the present state and inputs (Fig. 5-15)the outputs may change if the inputs change during the clock pulse periodthe outputs may have momentary false values unless the inputs are synchronized with the clocksThe Moore model: the outputs are functions of the present state only (Fig. 5-20)The outputs are synchronous with the clocks

Digital Circuits

Fig. 5.21Block diagram of Mealy and Moore state machine

Digital Circuits

5-7 Synthesizable HDL Models of Sequential CircuitsBehavioral ModelingExample: Two ways to provide free-running clockExample: Another way to describe free-running clock

Digital Circuits

Behavioral Modeling always statementExamples:Two procedural blocking assignments:Two nonblocking assignments:

Digital Circuits

Flip-Flops and Latches HDL Example 5.1

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Flip-Flops and Latches HDL Example 5.2

Digital Circuits

Characteristic EquationQ(t + 1) = Q TQ(t + 1) = JQ + KQ For a T flip-flopFor a JK flip-flop HDL Example 5.3

Digital Circuits

HDL Example 5-3 (Continued)

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HDL Example 5-4 Functional description of JK flip-flop

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State Diagram HDL Example 5.5: Mealy HDL model

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HDL Example 5-5 (Continued)

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HDL Example 5-5 (Continued)

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Mealy_Zero_DetectorFig. 5.22 Simulation output of Mealy_Zero_Detector

Digital Circuits

HDL Example 5-6: Moore Model FSM

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Simulation Output of HDL Example 5-6Fig. 5.23 Simulation output of HDL Example 5.6

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Structural Description of Clocked Sequential Circuits HDL Example 5.7: State-diagram-based model

Digital Circuits

HDL Example 5-7 (Continued)

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HDL Example 5-7 (Continued)

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HDL Example 5-7 (Continued)

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HDL Example 5-7 (Continued)

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Simulation Output of HDL Example 5-7Fig. 5.24 Simulation output of HDL Example 5.7

Digital Circuits

5-7 State Reduction and AssignmentState Reductionreductions on the number of flip-flops and the number of gatesa reduction in the number of states may result in a reduction in the number of flip-flopsa example state diagramFig. 5.25 State diagram

Digital Circuits

statea a b c d e f f g f g a input0 1 0 1 0 1 1 0 1 0 0 output0 0 0 0 0 1 1 0 1 0 0only the input-output sequences are importanttwo circuits are equivalenthave identical outputs for all input sequencesthe number of states is not importantFig. 5.25 State diagram

Digital Circuits

Equivalent statestwo states are said to be equivalentfor each member of the set of inputs, they give exactly the same output and send the circuit to the same state or to an equivalent stateone of them can be removed

Digital Circuits

Reducing the state tablee=fd=?

Digital Circuits

the reduced finite state machine

statea a b c d e d d e d e a input0 1 0 1 0 1 1 0 1 0 0 output0 0 0 0 0 1 1 0 1 0 0

Digital Circuits

the checking of each pair of states for possible equivalence can be done systematically (9-5)the unused states are treated as don't-care condition fewer combinational gates

Fig. 5.26 Reduced State diagram

Digital Circuits

State assignmentto minimize the cost of the combinational circuitsthree possible binary state assignments

Digital Circuits

any binary number assignment is satisfactory as long as each state is assigned a unique numberuse binary assignment 1

Digital Circuits

5-8 Design Procedurethe word description of the circuit behavior (a state diagram) state reduction if necessaryassign binary values to the statesobtain the binary-coded state tablechoose the type of flip-flopsderive the simplified flip-flop input equations and output equations draw the logic diagram

Digital Circuits

Synthesis using D flip-flopsAn example state diagram and state tableFig. 5.27 State diagram for sequence detector

Digital Circuits

The flip-flop input equationsA(t+1) = DA(A,B,x) = S(3,5,7)B(t+1) = DB(A,B,x) = S(1,5,7)The output equationy(A,B,x) = S(6,7)Logic minimization using the K mapDA= Ax + BxDB= Ax + B'xy = AB

Digital Circuits

Fig. 5.28 Maps for sequence detector

Digital Circuits

Sequence detectorThe logic diagramFig. 5.29 Logic diagram of sequence detector

Digital Circuits

Excitation tablesA state diagram flip-flop input functionsstraightforward for D flip-flopswe need excitation tables for JK and T flip-flops

Digital Circuits

Synthesis using JK flip-flopsThe same exampleThe state table and JK flip-flop inputs

Digital Circuits

JA = Bx'; KA = BxJB = x; KB = (Ax)y = ?Fig. 5.30 Maps for J and K input equations

Digital Circuits

Fig. 5.31 Logic diagram for sequential circuit with JK flip-flops

Digital Circuits

Synthesis using T flip-flopsA n-bit binary counterthe state diagram

no inputs (except for the clock input)Fig. 5.32 State diagram of three-bit binary counter

Digital Circuits

The state table and the flip-flop inputs

Digital Circuits

Fig. 5.33 Maps of three-bit binary counter

Digital Circuits

Logic simplification using the K mapTA2 = A1A2TA1 = A0TA0 = 1The logic diagram

Fig. 5.34 Logic diagram of three-bit binary counter