A

Paper presentation

On

“System on Chip (SOC)”(Group C)

CONTENTS:

1) ABSTRACT

2) INTRODUCTION TO SOC

3) STRUCTURE

4) DESIGN FLOW

5) FABRICATION

I. FULL CUSTOM

II. STANDARD CELL

III. FPGA

6) SOC & ITS DESIGN

I. CHALLENGE OF SOC DESIGN

II. SOC SPECIFICATION

III. SOC EXPLORATION

7) APPLICATION

8) CONCLUSION

1) Abstract:

Over the past ten years, as integrated circuits became increasingly more complex and expensive, the industry began to embrace new design and reuse methodologies that are collectively referred to as system-on-chip (SOC) design. This document contains some of the ways of reuse the component for SOC and also application of SOC that are useful for various purposes. Some are mentioned here in this paper. The concept of reuse can be carried out at the block, platform, or chip levels, and involves making the intellectual property (IP) sufficiently general, configurable, or programmable, for use in a wide range of applications.

2) Introduction to SOC

A system on a chip or system on chip (SOC or SOC) is an integrated circuit (IC) that integrates all components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio-frequency functions—all on a single chip substrate. A typical application is in the area of embedded systems. For larger systems system on a chip is hyperbole, indicating technical direction more than reality: increasing chip integration to reduce manufacturing costs and to enable smaller systems. Improvements in manufacturing capabilities allow placing of a complete embedded system on a single chip. With that it becomes possible to design a system as a mix of software running on a generic processor and specialized hardware, which performs otherwise expensive computation. This design freedom leads ultimately to highly specialized chips and cost efficient production. However the newly gained freedom in design places a burden on the SOC designer.

3) Structure

A typical SOC consists of:

Microcontroller, microprocessor or DSP core(s). Some SOC’s called multiprocessor system on chip include more than one processor core.

Memory blocks including a selection of ROM, RAM, EEPROM and flash memory.

Timing sources including oscillators and phase-locked loops.

Peripherals including counter-timers, real-time timers and power-on reset generators.

External interfaces including industry standards such as USB, FireWire, Ethernet, USART, and SPI.

Analog interfaces including ADCs and DACs.

Voltage regulators and power management circuits.

Fig. 1 Microcontroller-based system on a chip

These blocks are connected by either a proprietary or industry-standard bus such as the AMBA bus from ARM Holdings.

DMA controllers route data directly between external interfaces and memory, bypassing the processor core and thereby increasing the data throughput of the SOC.

4) Design flow

A SOC consists of both the hardware described above, and the software that controls the microcontroller, microprocessor or DSP cores, peripherals and interfaces. The design flow for a SOC aims to develop this hardware and software in parallel. Most SOC’s are developed from pre-qualified hardware blocks for the hardware elements described above, together with the software drivers that control their operation. Of particular importance are the protocol stacks that drive industry-standard interfaces like USB. The hardware blocks are put together using CAD tools; the software modules are integrated using a software-development environment.Often, one step in the verification flow is emulation: The hardware is mapped onto an emulation platform based on a field-programmable gate array (FPGA) that mimics the behavior of the SOC, and the software modules are loaded into the memory of the emulation platform. Once programmed, the emulation platform enables the hardware and software of the SOC to be tested and debugged at close to its full operational speed. Emulation is generally preceded by extensive software simulation. In fact, sometimes the FPGAs are used primarily to speed up some parts of the simulation work.After emulation the hardware of the SOC follows the place-and-route phase of the design of an integrated circuit before it is fabricated.

5) Fabrication

SOC’s can be fabricated by several technologies, including:

i. Full custom

Full-custom design is a methodology for designing integrated circuits by specifying the layout of each individual transistor and the interconnections between them. Alternatives to full-custom design include various forms of semi-custom design, such as the repetition of small transistor sub-circuits one such methodology is the use of standard cell libraries (standard cell libraries are themselves designed using full-custom design techniques).

ii. Standard cell

In semiconductor design, standard cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital-logic features. Standard cell methodology is an example of design abstraction, whereby a low-level very-large-scale integration (VLSI) layout is encapsulated into an abstract logic representation (such as a NAND gate). Cell-based methodology (the general class to which standard cells belong) makes it possible for one designer to focus on the high-level (logical function) aspect of digital design, while another designer focuses on the implementation (physical) aspect. Along with semiconductor manufacturing advances, standard cell methodology has helped designers scale ASICs from comparatively simple single-function ICs (of several thousand gates), to complex multi-million gate system-on-a-chip (SOC) devices.

iii. FPGA

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit. FPGAs can be used to implement any logical function that an ASIC could perform. FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together"—somewhat like many (changeable) logic gates that can be inter-wired in (many) different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND & XOR.

6) SOC & its Design

Challenges of SOC Design

The design of a SOC has similar goals as an embedded design. The designed system will be used in a well-specified environment, and has to fulfill strict requirements. Some requirements are clearly defined by the application like the functional requirements of an algorithm, e.g. the decoding of an MPEG 1 Layer 3 data stream, which covers certain quality restrictions. The environment poses other requirements: e.g. minimizing the cost, footprint, or power consumption. However due to the flexibility of a SOC design, achieving the set goals, involves analyzing a multi dimensional design space. The degrees of freedom stem from the process element types and characteristics, their allocation, the mapping of functional elements to the process elements, their interconnection

with busses and their scheduling. To give another perspective of the design space, it is good to look at the levels of abstraction. A SOC design has to deal with a wide range: it starts with a functional description on system level, where major function blocks are defined and no timing information is given. The other end of the spectrum is the result of the design process, where all functionalities described before are mapped to hardware and all hardware is defined down to the RTL level. At that point in time a cycle accurate model exists, which is ready for production.

Fig 2 Abstraction Levels in SOC Design

The goal of SOC design paradigm is to manage the immense size of design decisions in the hardware software co-design. This is only possible by following a well-defined flow of design steps. Those design steps and their asSOCiated models will be described in the next paragraphs.

SOC Specification

Hardware/Software co-design is an integral aspect of the SOC design. It requires a language with is capable of capturing the requirements of an hardware design from wire allocations do complex timing requirements, as well as the complexities of current software

design. Different alternatives languages for system level design were presented: the C++ library extension System C, some extensions to the UML capturing. The main focus was on the Spec C language, which is an extension of theANSI-C language. It uses the ANSI-C for description of software requirements and adds features needed for system design. It allows grouping of functionality to behaviors, which later can be freely mapped to processing elements. In order to allow this free mapping the computation has to be separated from the communication. Therefore communication between the behaviors is abstractly defined as channels. The channel specific implementation (e.g. a PCI bus protocol) will be filled in during later refinement stages. The specification model is free of such implementation detail (and constrain). The Spec C language further introduces many concepts from hardware description languages like VHDL and Verilog. It introduces the concept of capturing scheduling information in the language, such as sequential, parallel and pipelined execution.

SOC Exploration

Together with the SpecC language a design paradigm was introduced, which tries to formalize individual refinements steps and gives the designer guidelines how to handle efficiently the immense design space. Fig 2 shows an overview of the design flow, it also indicates the integration of the validation flow. The tool suite provided with the SpecC language closely follows the outlined design flow. The following paragraphs will describe the steps of the design flow.

Fig 3 SOC Design Methodologies The SOC design starts with the specification model, which is a purely functional model free of any implementation details. It focuses on capturing the algorithmic behavior and allows a functional validation of the description. The model is untimed and allows only for causal ordering. Once the specification model is finished it will serve as a “golden model”, to compare to during the design cycle. Architecture information is added during the Architecture refinement. During this step processing elements are inserted into the system and functional behaviors are mapped to them. The processing elements can be standard components such as generic processor cores or DSPs, as well as specific hardware. Parameters, such as clock frequency, of the inserted elements can be adjusted to the application needs. Based on internal statistics, first estimations about the runtime performance can be made, which gives the designer the first feedback about the design decisions.

7) Application

Fig 4 Application of SOC

Applications of SOC include digital signal processing, software-defined radio, aerospace and defense systems, ASIC prototyping, medical imaging, computer vision, speech recognition, cryptography, bioinformatics, computer hardware emulation, radio astronomy, metal detection and a growing range of other areas. Traditionally, FPGAs have been reserved for specific vertical applications where the volume of production is small. Today, new cost and performance dynamics have broadened the range of viable applications.

Intel Embedded Atom E600 Series System-on-Chip Supports Hardware Accelerated Adobe HD Flash Video Decoding on Linux. Secured & reliable wireless connectivity is now a great concern for the embedded devices.

Fig 5 Intel E600

These embedded devices are used for various purposes by the security personals or other high end communications. An inviolable cellular connectivity to support both real time voice & data over a wireless network needs a central point of control.

SOC Architecture for Audio Processing Application

Fig 6 Audio Processing system

Audio processing system shows the proposed architecture for speech processing application. This architecture utilizes processor and peripherals from the Aquarius project designed by Thorn Aitch published in Open Core under GPL license. The memory access controller sends fetched instruction bit field to the decoder unit, in turn decoder unit decode the instruction bit fields and throws many control signals for execution and data read/write access towards data path unit, multiplication unit and memory access controller. The data path unit has sixteen general registers, Status Registers, Global Base Registers, Vector Base Register, Procedure Register, and Program Counter. The CPU also has 32 bit architecture for enhanced data processing ability as multiply and accumulation like DSP functionality.

Network on chip

In order to support networking applications such as edge router functionalities, e.g., packet filtering for firewalls or network intrusion detection systems, establishing VPNs, content-based switching, etc., Dyna-CORE is attached to an NP. The NP allows an appropriate integration of Dyna-CORE because of its flexible software

programmability.

Fig. 7 VPN configuration example

Dyna-CORE is a run-time reconfigurable coprocessor for NPs and allows computationally intensive tasks to be offloaded from the NP.A suitable scenario for Dyna-CORE is a Virtual Private Networks (VPN) to connect at least two separated local area networks (LANs) and/or other spread VPN participants. The need for compression is generally motivated using strongly limited carriers such as wireless technologies. Figure 6 shows a feasible configuration. Two LANs are combined to a VPN using an edge-to-edge tunnel with encryption so that any internal VPN connection is passed through this tunnel. Additionally, a mobile host with a probably low-bandwidth connection is incorporated into the VPN by an end-to-edge tunnel with encryption and compression. DynaCORE is applied at the edge routers to perform the deep-packet processing of these applications. The internal set-up of DynaCORE highly

depends on the traffic volume. It is reasonable to assume that the edge-to-edge tunnel is more frequently used than the end-to-edge connection. Nevertheless, the system integration is limited to appropriate router systems and cryptography algorithms are fixed. Therefore, the flexibility degree is improvable and demands more flexible stream-processing architectures.

8) Conclusion

The above paper has a brief review of what SOC is to its design stages and its applications. Traditional EDA tools and methodologies have served the semiconductor and industries well and will continue to in future. FPGA architectures in the late 1990s, applications which had traditionally been the sole reserve of DSPs began to incorporate FPGAs instead. Increasingly there is a need for a much more robust and integrated ecosystem for preparing SOC designs better and more efficient. SOC realization represents the next evolutionary step in the extension of world, as it moves up another notch in abstraction and delivers new levels of value to system and semiconductor companies. In order to achieve the vision for true SOC realization, a variety of tools and methods are developed and integrated. The result is development approach that is much more in sync with the needs of the rapidly changing software rich electronics industry.