1. www.ansoft.co.kr DDR2/3 PCB SOLUTION

2. SI Design Guide for DDR2/3 PCB Ansoft SI/PI/EMI tool package APDS (Ansoft PCB Design Suite) DDR2/3 PCB SI (Signal Integrity) . APDS PCB EM SIwave Nexxim , PCB transient High Speed Digital SI . SIwave PCB layout data / Near field/far field PCB EM tool. PCB EM tool , UI PCB PI/EMI . PCB SPICE SI . Nexxim Multi-Solver Transient Harmonic Balance/Linear . SSN PCB full layout , / SI . HFSS 3 , DDR2/3 coupling/field . Q3D / / 3 RLGC , . TPA DDR2/3 BGA parasitic RLC . 2 3. DDR2/3 , ? Fail?? Pass!! Gbps DDR2/3 . PCB , . DDR2/3 PCB , PCB pattern SI . 3 4. SI Design Guide for DDR2/3 PCB Contents Part 1: Introduction DDR2/3 , DDR2/3 PCB Spec . Part 2: DDR2/3 Design Guide DDR2/3 PCB , DIMM On-board . Part 3: DDR2/3 Simulation Guide APDS DDR2/3 PCB data pattern SI , . Part 4: Automatic Verification DDR2/3 Tool APDS Wizard DDR2/3 SI . 4 5. 1. Introduction 1-1. DDR2/3 High Speed Memory 1-2. DDR2/3 1-3. DDR2/3 1-4. , Bytelane 1-5. DQS (Strobe) 1-6. DDR2/3 1-7. Key Spec: Setup time & Hold time 1-8. Module & On-Board case 1-9. Termination 1-10. ODT 5 6. SI Design Guide for DDR2/3 PCB 1-1. DDR2 High Speed Memory Dual Data Rate (DDR) DDR 400Mbps . DDR DDR2 , DDR2 (~800Mbps), DDR3 (~1.6Gbps), DDR4 (~4Gbps) . (bps) DDR2 DDR3 DDR4 400M, 533M, 667M, 800M 800M, 1066M, 1333M, 1.6G ~ 4G DDR2 DDR3/4 , . DDR2 DDR3/DDR4 . DDR2 DDR DDR DDR2 0 1 Strobe Single line Differential line . ( DQS ) DDR2 , DDR2 . 800MHz , . RF . , / RF , . DDR2/3 / , DDR2/3 PCB . 6 7. 1-2. DDR2 PCB DDR2/3/4 400M~4Gbps . RF , RF 800MHz , DDR2 / . RF , . . (Coupling Issue) . (Power Integration Issue) . (Signal Integration Issue) EMI . (Spurious Emission Issue) DDR2 PCB pattern , PCB . PCB / . 800Mbps DDR DDR2 fail . SI/PI . " !?" PCB debugging , Trace Power/GND Plane . PCB artwork "Art" . Routing PCB Pattern , PCB . PCB Pattern DDR2 Simulation . , DDR2 , . ? - PCB pattern . 7 8. SI Design Guide for DDR2/3 PCB 1-3. DDR2 DDR2 . Ctrl CMD Clock Address DM DQS DQ command line. RAS, CAS Control Signal: ODT, Buffer digital clock . Data Mask Strobe signal. DQ 1 0 data . DDR2 , . tip , SI . 8 9. 1-4. , Bytelane Bytelane , DM, DQS, DQ . DDR2 DQ (data) spec . 1 0 . DQ DQ spec DQS . DM DQ, DQS DDR2 . DQS 2 differential 1 byte DQ 8 single bit . DQS Bytelane 8 DQ DDR2/3 SI Bytelane . 9 10. SI Design Guide for DDR2/3 PCB 1-5. DQS (Strobe) ? DQ (data) DQS , spec DQS . DQ DQ , DQS . DQS DQ 1/4 DQS DQ 1 0 . DDR2 Vref , DQS Vref DQ threshold High, Low . DQ bit reference . DDR2 DQS differential line DQS . DDR (400, 533) Single line DQS 2 differential line . 10 11. 1-6. DDR2 PCB DDR2 , Setup margin Hold margin . DDR2 Eye Diagram, DQS Vref Setup time, hold time spec . Setup time high/low , Hold time . Setup/Hold time spec JEDEC , spec. Eye diagram Mask Setup V IHAC V ILAC, Hold V IHDC V ILDC . Mask , Setup Vref Setup time spec , Setup margin Hold Hold margin . Eye Diagram Mask , Setup/Hold margin . margin gray zone . 11 12. SI Design Guide for DDR2/3 PCB 1-7. Key Spec: Setup time & Hold time , DDR2 spec Setup time Hold time. Mask AC DC Threshold Voltage . JEDEC , DDR2/3 , DQS . AC DC Threshold Voltage . Threshold DQ 1 0 . V IH(AC) DDR2 DDR3 VREF+0.25 (400/533) VREF+0.2 (677/800) VREF+0.175 V IL(AC) VREF - 0.25 (400/533) VREF -0.2 (677/800) VREF - 0.175 V IH(DC) VREF + 0.125 VREF + 0.1 V IL(DC) VREF - 0.125 VREF - 0.1 VDDQ DDR2 DDR3 1.8 1.5 VREF 0.9 0.75 VTT 0.9 0.75 12 13. Spec Setup time/Hold time spec . DDR2 with Differential Strobe Setup / Hold time Data rate (Mbps) Setup Time (ns) Hold Time (ns) 400 0.15 0.275 533 0.1 0.225 667 0.1 0.175 800 0.05 0.125 Slew Rate table Buffer Strength Slew Rate slew rate Setup/Hold time . table DQ DQS slew rate delta time setup time, hold time . 13 14. SI Design Guide for DDR2/3 PCB DDR2 with Single Strobe Setup / Hold time Data rate (Mbps) Setup Time (ns) Hold Time (ns) 400 0.025 0.025 533 -0.025 -0.025 667 N/A N/A 800 N/A N/A Slew Rate table DDR2 Single Strobe spec 400 533 . , DDR2 strobe differential line DDR DDR2 single strobe DDR PCB . DDR1 DDR2 DDR2 DDR1 single strobe . , single strobe DDR2 common noise differential DDR2 spec . single spec , 667 800 spec . DDR2 Single Strobe DDR , strobe differential . 14 15. DDR3 Setup / Hold time Data rate (Mbps) Setup Time (ns) Hold Time (ns) 800 0.075 0.15 1066 0.025 0.1 1333 TBD TBD 1600 TBD TBD Slew Rate table DDR3 Setup/Hold time spec . TBD To be decided , . 15 16. SI Design Guide for DDR2/3 PCB 1-8. Module & On-Board case , Eye Diagram Mask AC DC threshold spec . AC spec AC DC , DC spec 0, 1 . AC spec DC spec . AC/DC spec Data 1 0 , Setup AC spec . , on-board DDR2, PCB DDR2 Setup/Hold DC spec . AC spec spec, DIMM DDR2 module . DIMM Motherboard PCB . DIMM on-board DDR2 AC spec , . spec AC spec . 16 17. 1-9. Termination DDR2 termination . termination . Termination tune . trade-off termination . Termination Termination DDR2/3 termination . termination , loading ripple over/undershoot . termination Eye mask SI . " " , EMI . , DDR2/3 termination ODT termination . 17 18. SI Design Guide for DDR2/3 PCB 1-10. ODT DDR2 DDR termination , ODT (One-Die Termination) DCI (Digitally Controlled Impedance) . ODT Control , switch on/off . DDR2/3 ODT , IC termination . . ODT 50, 75, 150 . ODT ODT . ODT . 18 19. DDR2/3 , controller ODT . DDR2/3 ODT disable DDR2/3 ODT on DDR2/3 load . S/W control ODT , PCB termination . DDR2/3 ODT DQ/DQS/DM pin 300 3, ODT pin 300 3 S/W . ODT disable , S/W enable 300 2 150 . A6 (SW1) 0 0 1 1 A2 (SW2) 0 1 0 1 Rtt (Normal) Disabled 75 ohm 150 ohm 50 ohm S/W 150/75/50 3 termination , A0 ~ A9 Address field A2 A6 2 bit . ODT batch file controller load , Controller , ODT . ODT , DDR2/3 ODT DDR2/3 Memory . 19 20. SI Design Guide for DDR2/3 PCB 2. DDR2/3 Design Guide 2-1. : Skew 2-2. DIMM case/On-board case 2-3. DIMM: Clock Line 2-4. DIMM: 2T mode - Address/CMD Line 2-5. DIMM: 1T mode with Termination - Address/CMD Line 2-6. DIMM: DM/DQS/DQ 2-7. On-board: Clock Line 2-8. On-board: 2T mode - Addre7s/CMD Line 2-9. On-board: 1T mode with Termination - Address/CMD Line 2-10. On-board: DM/DQS/DQ 20 21. 2-1. : Skew , . PCB Layout DDR2 DQ , . layer , . PCB Layout CAD , "" . 400Mbps DDR2 , . datarate . , , PCB . SI PCB EM , high speed digital . , EM SI skew , DQ DDR2/3 PCB layout . 21 22. SI Design Guide for DDR2/3 PCB 2-2. DIMM case/On-board case DDR2 2 , DIMM PCB DDR2 IC SMT On-board . spec , . DDR2/3 DIMM On-Board DDR2/3 DDR2/3 Design Guide part, DIMM case On board case trace , . DDR2/3 PCB trace Clock line , CMD/Address line , DM/DQ/DQS 3 part , . DIMM On-board case termination ODT , . DIMM module DDR2/3 Controller DIMM , On-board Controller DDR2/3 . , ODT termination DIMM on-board . Design guide DIMM case on-board case , DDR2/3 PCB . 22 23. 2-3. General Case "2 DIMM": Clock Line , Clock uni-directional differential signaling scheme , SSTL1.8V logic , DDR2 SDRAM differential Input buffer logic threshold 0V 500mV . 2 DIMM Hardware Interface Main Board DIMM 3 differential clock signal , clock DIMM buffer . 2 DIMM Hardware Interface 6 differential pair . Clock Trace Single Impedance 60, Zodd( 2S1 NG (S1=S2) Zdiff Impedance 100Ohm , Skew delay . differential line , signal pair S2 differential line S1 2 . pair , Signal Switching Switching Zodd, Zeven Variation Velocity , common mode noise . 26 27. NG E-Field . ( 0.1mm 0.1mm ) S1=S2 field , pair field . Signal Coupling Diff. Signaling ( ), Diff. Impedance . S2=S1 Posi Nega Nega Posi Ref. Plane S2 = 2*S1 field , field . S2=2S1 , Differential Clock Self Net skew , +/- (Phase) Uncoupled . ) 1. Pin Skew , Phase delay (Serpentine Trace). 2. Skew , Uncoupled Region , 27 28. SI Design Guide for DDR2/3 PCB Termination @ Main Board DIMM Clock input buffer differential line +/- , Main Board Shunt Termination (100Ohm) . Reflection Voltage/Timing Margin Buffer Strength Termination . Main Board 100Ohm shunt termination , DC IR drop DC noise margin . Clock , . Routing DDR2 Interface Signal , Impedance , . ( Uncoupled Region) edge-to-edge coupled type Microstrip , FR4 system Physical Dimension W=0.1mm, S=0.1mm, H(PCB Layer Stack , Prepreg Thickness)=0.1mm , Single Zo 63Ohm , Zodd 50.5Ohm . (Zdiff=2*Zodd) 28 29. 6 , 1 6 Differential Signal Coupled Microstrip , 2 5 Reference Plane (GND) PCB Layer Stackup . stackup 4 Power Plane Layer Power(4th)-Ground(5th) Plane Pair Power/Ground Impedance . 1,3,6 Layer Ground reference plane , (W 0.1mm) 60 . stackup , BGA Ball Pitch 6 (1.6T Bulk PCB) . DDR2 Interface SI/PI/EMC Layer Assign . : "Printed Circuit Board Design Techniques for EMC Compliance" Ch2. Section2.5 Layer Stackup Assignment 29 30. SI Design Guide for DDR2/3 PCB 1pF Shunt Termination 200Ohm Shunt Termination Resistor DDR2 Memory Module Differential Clock Interconnection Topology (Multi-Drop) . 1. Interconnection Topology Port (8 Multi port) , 2. Full PCB Filed Solver SIwave , 3. SPICE model 4. Nexxim Main Board clock interconnection topology SI (667Mbps - Clock: 333MHz) Schematic . SIwave DDR2 Memory Module Clock Interconnection Element PCB SPICE , IBIS differential , Differential input Clock . 30 31. Layout Clock trace , (Multi Drop) Reflection Noise edge , non-monotonic response . Non-monotonic response , Main Board Topology . DIMM Connector 5pF Shunt Capacitor . 31 32. SI Design Guide for DDR2/3 PCB 5pF Capacitor , Non-monotonic response . Capacitor Reference Event Time , trade-off . (Buffer Strength BOM ) Clock Buffer Strength . S/W H/W Output Buffer Strength , Output Buffer Strength Output Impedance . slew rate , Buffer Strength Nexxim Import Output buffer IBIS model "Model Selection" UI . 32 33. 2-4. General Case "2 DIMM": Address/CMD Line (, 2T) Address/CMD 1T 2T , Memory Controller DDR2 Interface Pin . JEDEC DDR2 DIMM Reference Design . General Case 2 DIMM Interface , . 33 34. SI Design Guide for DDR2/3 PCB Source: RAMpedia by Virtium Technology 34 35. PCB Address/CMD , "Memory Controller" Address/CMD pin Copy (Slot1, 2 Pin) . , Memory Controller Address/CMD pin 1 , , 2 DIMM . Address/CMD pin DIMM 2 , Slot2 Slot1 stub . Stub1 Stub2 Memory pin non-monotonic response . DIMM 9 DDR2 , 18 load (1DIMM 9 Receiver) . heavy load (IBIS Ccomp 1pF~3pF), address/CMD driver Power full-swing . 2T , 1T ISI (Inter Symbol Interference) Valid Window Timing margin . ISI Multi-Giga bps Serial I/O Conductive/Dielectric Loss , heavy load fan-out . 35 36. SI Design Guide for DDR2/3 PCB , Memory Controller 2 Address/CMD pin , DIMM . load , 1T . 1T , 1 Clock 1 Rising Address/CMD Sampling , 2T 2 Clock 1 Rising Address/CMD Sampling . ( ) Logic Timing Diagram . Interconnect Topology Address/CMD Pulse Width . 36 37. address/CMD 2 DIMM Mount SI . DIMM 9 DDR2 Address/CMD receiver , 667Mbps Speed grade 1T , Address/CMD 167MHz 6nsec , PW 3nsec . 1T Mode @ Single ADD/CMD BUS Pulse Width = 3nsec @ 667Mbps Eye Diagram , 1T Load Heavy ISI . Switching Bit Sequence Voltage Swing , Eye Window Timing/ Voltage Noise Margin . 37 38. SI Design Guide for DDR2/3 PCB 2T MODE @ Single ADD/CMD BUS Pulse Width = 6nsec @ 667Mbps , 2T Eye Diagram . 2T PW 2 6nsec , Bit Full Swing . ISI , Eye Valid Window 3nsec . Topology , Main Board DIMM 1 10pF Capacitor(Option) , 38 39. Termination scheme 150psec Eye Window . Main Board Interconnect Topology BOM Address/CMD , Pre Layout SI simulation . ( , BOM .) Buffer Strength . 2T MODE + 10pF + Buffer Strength (1.8V sstl class1 12mA) 39 40. SI Design Guide for DDR2/3 PCB Buffer Strength (8mA) 12mA Buffer Strength IBIS model (Memory Controller SSTL Class2 , Buffer Strength 20mA .), Eye window 750ps . (Nexxim IBIS Model Selector UI ) 2T MODE + 10pF + Buffer Strength (1.8V sstl class1 12mA) Address/CMD Timing Diagram . Clock Address/CMD Waveform Simulation, Propagation Delay, Reflection Timing Margin Post Layout (DIMM)+Pre Layout (Main Board) Simulation . Timing , Receiver DDR2 Memory Address/CMD Input Buffer Setup/Hold Time , Valid Before/After Setup/Hold Margin . Pre Layout Main Board Clock Memory Hold Margin . Clock Delay (DLL setup) Address/CMD Pulse width 1/2. 40 41. 2-5. General Case "2 DIMM": Ctrl Line (1T mode Address/CMD ) Ctrl Address/CMD 2 pin DIMM load , 1T . 2 pin DIMM Address/CMD 1T . 41 42. SI Design Guide for DDR2/3 PCB , Valid Window 1.39nsec Voltage Noise Margin . Pre Layout , SSN Crosstalk Voltage Noise Margin . 2T , 10pF Capacitor . Reflection Noise Valid Window 400ps , Noise Margin . Nexxim SI Option discrete component . 42 43. 1T Mode ADD/CMD and Control Signals (with 20pF capacitor) 1T Ctrl/Address/CMD Timing Diagram . Valid Window , Setup/Hold Margin . 2T Clock Ctrl/Address/CMD Center Align DLL . 43 44. SI Design Guide for DDR2/3 PCB 2-6. General Case "2 DIMM" : DM/DQS/DQ DDR2 SDRAM Termination ODT(On-Die Termination) Technology . DATA Group Signal Interface Memory Controller ODT Technology . Table Controller DDR2 ODT ODT. On-Board Data Table , Data Point-to-Point Table . 44 45. Signal Write Mode Operation 1R/2R Slot1 Operation DIMM SDRAM Single Side , DIMM Memory Controller Write Simulation . Simulation Memory Controller ODT Technology , Read Mode Operation Parallel Termination (0.9V Pull-up Resistor) Memory Controller . 45