enabling scalable silicon photonic circuit design …si photonics design si photonics design is less...

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Enabling Scalable Silicon Photonic Circuit Design and Fabrication INVITED TALK, OECC 2015 © IEEE 2015. PERSONAL USE IS PERMITTED. REPRODUCTION/REDISTRIBUTION REQUIRES IEEE PERMISSION 1 Xu Wang, James Pond, and Jackson Klein Lumerical Solutions, Inc., Vancouver, Canada Andy Eu -Jin Lim, Kok Kiong Chen, and Guo-Qiang Lo Institute of Microelectronics (IME), A*STAR, Singapore

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Page 1: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

Enabling Scalable Silicon Photonic Circuit Design and Fabrication

INVITED TALK, OECC 2015

© IEEE 2015. PERSONAL USE IS PERMITTED. REPRODUCTION/REDISTRIBUTION REQUIRES IEEE PERMISSION

1

Xu Wang, James Pond, and Jackson KleinLumerical Solutions, Inc., Vancouver, Canada

Andy Eu-Jin Lim, Kok Kiong Chen, and Guo-Qiang LoInstitute of Microelectronics (IME), A*STAR, Singapore

Page 2: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

OutlineIntroduction

Silicon photonic design & simulation

IME PDK Compact model library (CML)

Example

Conclusions

2 © IEEE 2015. PERSONAL USE IS PERMITTED. REPRODUCTION/REDISTRIBUTION REQUIRES IEEE PERMISSION

Page 3: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

IntroductionSilicon photonics offers many opportunities

Circuit complexity continues to grow Full design flow solutions are emerging

EDA tools + photonic simulation technologies

Si photonic process design kits (PDKs) are emerging

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edX course | Silicon Photonics Design, Fabrication and Data Analysis

scalable high-index contrast -> compact a variety of devices -> high functionality

low cost & high volume CMOS manufacturing facility

many applications optical interconnects (data centers, telecom, HPC, …) sensing (biological, chemical, …)

© IEEE 2015. PERSONAL USE IS PERMITTED. REPRODUCTION/REDISTRIBUTION REQUIRES IEEE PERMISSION

Page 4: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

IntroductionFabless model and foundry Multi-project wafer (MPW) services

Wide range of reliable components available

Packaging

Prototyping

Path to mass production

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SiEPIC-IME chip, including active components such as modulators

Book: Silicon Photonics Design

© IEEE 2015. PERSONAL USE IS PERMITTED. REPRODUCTION/REDISTRIBUTION REQUIRES IEEE PERMISSION

Page 5: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

PROPRIETARY AND CONFIDENTIAL© LUMERICAL SOLUTIONS INC

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Page 6: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

Si photonics designSi photonics design is less mature than electronic design Typically based on highly customized, user-specific component libraries

The PICs are often designed and laid out manually

Leads to errors and multiple, expensive design iterations

Solution Adopt workflows like those in the fabless CMOS semiconductor space

The fundamental components are reliably defined for a specific process

Complex systems can be built upon that library of components

Requires reliable simulation tools and models

6 © IEEE 2015. PERSONAL USE IS PERMITTED. REPRODUCTION/REDISTRIBUTION REQUIRES IEEE PERMISSION

Page 7: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

Unified work flow for Si photonics design

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Layout and Mask Generation

(Pyxis, Virtuoso, PhoeniX)

Verification(Calibre, PhoeniX)

Photonic Circuit Simulation

(INTERCONNECT)

Photonic Component DesignOptoelectronic solvers,

Experimental data

Compact Model Parameter Extraction

Optical Parameters define layout structures

Schematic Capture(INTERCONNECT, Pyxis,

Virtuoso)

PDKsDesign Rules

Compact modelsComponent parameters

Process dataLayout

Netlist exchange

© IEEE 2015. PERSONAL USE IS PERMITTED. REPRODUCTION/REDISTRIBUTION REQUIRES IEEE PERMISSION

Page 8: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

Si photonics component level designComponent design tools are relatively mature Physics-based solvers:

Optical: solving Maxwell’s equations, e.g., FDE, FDTD, EME…

Electrical: solving drift-diffusion and Poisson’s equations

8

Va

© IEEE 2015. PERSONAL USE IS PERMITTED. REPRODUCTION/REDISTRIBUTION REQUIRES IEEE PERMISSION

Page 9: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

Photonic circuit simulation challengesComplex nature of optical signals

Both electrical and optical signals are required

No standardized behavioral models exist

Frequency and time domain simulation are necessary

To meet these challenges, we must create a reliable compact model library Calibrated for a particular foundry process

9 © IEEE 2015. PERSONAL USE IS PERMITTED. REPRODUCTION/REDISTRIBUTION REQUIRES IEEE PERMISSION

Page 10: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

Frequency domain example

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Hierarchical design

© IEEE 2015. PERSONAL USE IS PERMITTED. REPRODUCTION/REDISTRIBUTION REQUIRES IEEE PERMISSION

Page 11: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

Time domain example

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Mixed signal representation:

digital, electrical and optical

waveforms

Signal integrity

analysis

Advanced modulation format

© IEEE 2015. PERSONAL USE IS PERMITTED. REPRODUCTION/REDISTRIBUTION REQUIRES IEEE PERMISSION

Page 12: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

Why do we need a PDK?

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Photonic Circuit Design & Fabrication

Foundry and end-customers

Component & Model Library Design

Lumerical & Foundry Partner

Photonic PDKDesign Rules

Component parametersProcess data

Layout

Compact models (CML)

Define Compact Model

Measured Results

Component SimulationOptoelectronic solvers Circuit

Design, Layout, Verification

Fabrication and Test

© IEEE 2015. PERSONAL USE IS PERMITTED. REPRODUCTION/REDISTRIBUTION REQUIRES IEEE PERMISSION

Page 13: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

IME PDKThe IME PDK includes Device integration and process information

Device building blocks

Mask layout

Design rules

Process control monitoring structures

Now includes a CML developed jointly with Lumerical

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Page 14: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

IME process

220 nm Si / 3 μm BOX SOI

Partial Si etches of 70 nm and 130 nm

Germanium (Ge) epitaxy

Multiple ion implantation steps

Two-level metallization

TiN heater for thermal-optic tuning

A final deep trench Si etch

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Andy Eu-Jin Lim, et al., “Review of Silicon Photonics Foundry Efforts”, JSTQE vol. 20, no. 4, 2014.

© IEEE 2015. PERSONAL USE IS PERMITTED. REPRODUCTION/REDISTRIBUTION REQUIRES IEEE PERMISSION

Page 15: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

IME componentsWafer-level test setup, grating coupler, waveguides

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Andy Eu-Jin Lim, et al., “Review of Silicon Photonics Foundry Efforts”, JSTQE vol. 20, no. 4, 2014.

© IEEE 2015. PERSONAL USE IS PERMITTED. REPRODUCTION/REDISTRIBUTION REQUIRES IEEE PERMISSION

Page 16: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

IME componentsExcellent waveguide loss uniformity

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Andy Eu-Jin Lim, et al., “Review of Silicon Photonics Foundry Efforts”, JSTQE vol. 20, no. 4, 2014.

Strip waveguide: ~2 dB/cm Rib waveguide: ~0.8 dB/cm

© IEEE 2015. PERSONAL USE IS PERMITTED. REPRODUCTION/REDISTRIBUTION REQUIRES IEEE PERMISSION

Page 17: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

IME componentsPhotodetector

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Andy Eu-Jin Lim, et al., “Review of Silicon Photonics Foundry Efforts”, JSTQE vol. 20, no. 4, 2014.

© IEEE 2015. PERSONAL USE IS PERMITTED. REPRODUCTION/REDISTRIBUTION REQUIRES IEEE PERMISSION

Page 18: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

IME CMLWaveguides

Other Passives

Actives

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Page 19: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

CML generationWaveguides

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Required: - neff- ng- loss

Advanced:- neff(λ)- ng(λ) or dispersion- multiple modes

Typical inputs from the fab:- cross-section for FDE simulation

- width, height (etch depth)- cladding material (air/SiO2)- sidewall angle (if available)

- measured propagation loss - e.g., 2 dB/cm for strip WG

© IEEE 2015. PERSONAL USE IS PERMITTED. REPRODUCTION/REDISTRIBUTION REQUIRES IEEE PERMISSION

Page 20: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

CML generationOther passive components

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Required: - S parameters

Typical inputs from the fab:- measured transmission- measured crosstalk or back

reflection- physical geometry for 3D FDTD

simulation (if necessary)

© IEEE 2015. PERSONAL USE IS PERMITTED. REPRODUCTION/REDISTRIBUTION REQUIRES IEEE PERMISSION

Page 21: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

CML generationActive devices are often much more complicated Modulators

Phase shifter characteristics: neff(V), loss (V)

Transmission spectra vs. voltage

Modulation frequency response

Travelling wave data, …

Detectors Responsivity (as a function of λ)

Dark current (as a function of bias and temperature)

Modulation frequency response

Noise, …

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Page 22: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

CML generationIME Mach-Zehnder Modulator

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Page 23: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

CML generationIME Mach-Zehnder Modulator

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simulation

vs.

experiments

© IEEE 2015. PERSONAL USE IS PERMITTED. REPRODUCTION/REDISTRIBUTION REQUIRES IEEE PERMISSION

Page 24: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

Example circuit using the CML

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Page 25: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

ConclusionSilicon photonics offers many opportunities Low cost, scalable, high volume, …

Workflows must become mature like in EDA Separation of component level design and circuit design Interface is the PDK Requires accurate circuit simulations with a calibrated CML

Many challenges with photonic circuit simulation We can create a CML that accurate represents component behavior Requires a combination of experimental and physical simulation results

IME and Lumerical have developed the first Si photonics foundry CML, available in the IME PDK.

25 © IEEE 2015. PERSONAL USE IS PERMITTED. REPRODUCTION/REDISTRIBUTION REQUIRES IEEE PERMISSION

Page 26: Enabling Scalable Silicon Photonic Circuit Design …Si photonics design Si photonics design is less mature than electronic design Typically based on highly customized, user-specific

Foundry Partners

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Featured Foundry Partners

https://www.lumerical.com/company/news/releases/sandia_partnership.html

To learn more, visit www.lumerical.com/foundry

Photonic Circuit Design & Fabrication

Foundry and end-customers

Component & Model Library Design

Lumerical & Foundry Partner

Photonic PDKDesign Rules

Component parametersProcess data

Layout

Compact models (CML)

Define Compact Model

Measured Results

Component SimulationOptoelectronic solvers Circuit

Design, Layout, Verification

Fabrication and Test

© IEEE 2015. PERSONAL USE IS PERMITTED. REPRODUCTION/REDISTRIBUTION REQUIRES IEEE PERMISSION