richard kass

LECC03, 9/30/2003 Richard Kass/OSU1

Richard Kass

Radiation-Hard ASICs forOptical Data Transmission in the

ATLAS Pixel Detector

K.E. Arms, K.K. Gan, M. Johnson, H. Kagan, R. Kass, C. Rush,A. Rahimi, S. Smith, R. Ter-Antonian, M.M. Zoeller

The Ohio State University

A. Ciliox, M. Holder, S. Nderitu, M. ZiolkowskiUniversitaet Siegen, Germany

IntroductionResults from IBM 0.25 m Prototype ChipsResults from Proton IrradiationsSummary

Outline


ATLAS Pixel Detector

Inner most charged particle tracking detectorPixel size: 50 m x 400 m

~ 100 million channels Dosage after 10 years:

middle barrel layer: 50 Mrad or 1015 1-MeV neq/cm2

optical link: 30 Mrad

2 disks/end

2 layers in barrel


ATLAS Pixel Opto-link

VCSEL: Vertical Cavity Surface Emitting Laser diodeVDC: VCSEL Driver Circuit

PIN: PiN diodeDORIC: Digital Optical Receiver Integrated Circuit

Opto-board: this board holds the VDCs, DORICs, PINs, VCSELS

use BeO as substrate for heat management


Convert LVDS input signal into single-ended signal appropriate to drive the VCSEL diode

Output (bright) current: 0 to 20 mA, controlled by external voltage

Standing (dim) current: ~ 1 mA to improve switching speed

Rise & fall times: 1 ns nominal (80 MHz signals)

Duty cycle: (50 +/- 4)%

“On” voltage of VCSEL: up to 2.3 V at 20 mA for 2.5 V supply

Constant current consumption!

Current design uses TRUELIGHT “high power oxide” VCSELs

VCSEL Driver Circuit Specs


Decode Bi-Phase Mark encoded (BPM) clock and command signals from PIN diode

Input signal: 40-1100 A

Extract: 40 MHz clock

Duty cycle: (50 +/- 4)%

Total timing error: < 1 ns

Common Cathode PIN array

Bit Error Rate (BER):

< 10-11 at end of life

Digital Optical Receiver IC Specs

40 MHzclock

command

BPM

Training period: ~1 ms of 20 MHz clock (BPM with no data)

Input transitions leading edges

Internal delays trailing edges


Status of VDC and DORICVDC and DORIC produced using IBM 0.25m CMOS process Migrated ATLAS SCT’s VDC & DORIC design in AMS 0.8m Bipolar to DMILL DMILL (0.8m CMOS) process met e-specs but was not rad hard enough

VDC-I5e and DORIC-I5e: our fifth IBM submission Use CADENCE program

5 layers, enclosed layout transistors and guard rings 4 channels per chip (VDC: 1.4mm4mm DORIC: 2.3mm4mm)

engineering run, produced enough chips for production Received chips in June 2003Electrical measurements performed on these chips: detailed measurements of many parameters: rise/fall time, duty cycle, bright/dim current… VDC-I5e and DORIC-I5e are acceptable for use in pixel detectorNeed to certify that these chips are radiation hard previous VDC and DORIC version (I4) rad hard to > 50Mrad detailed plan to certify radiation hardness


DORIC and VDC Layout

Input Pads:

Signal_in

GndA

Noise_in

VddAmp

VddA

Preamp / Digital Test Pads

Analog / Digital Bias, Resets

Ch 1

Ch 2

Ch 3

Ch 4

Ch 1

Ch 2

Ch 3

Ch 4

DORIC-I5 (2.3 x 4mm) VDC-I5 (1.4 x 4mm)


VDC-I5e Measurements

Eight VDCI5e chips with four channels per chip were measured

VDCI5e duty cycle

bright

dim

Spec is 50±4%


VDC-I5e Rise and Fall Timesrise time

fall time

spec is <1 ns


Status of BeO Opto-Board

First BeO opto-boardsarrive in April.

Find problems: many vias not filled.

Send boards back to company for repair.

Company only partiallysuccessful with repairs(~50% success rate)

We find a new company to produce the boards(more $$$ too)

two populatedopto-boards used forrad-hardness tests

convertselectricaloptical

6-7 links/board


Radiation Hardness MeasurementsCERN August 2003

Important to measure/certify radiation hardness of optical componentsVDCDORICVCSELFibersGlues, etc…

Use CERN’s T7 beam (24 GeV protons) for radiation hardness studies.

We perform two types of radiation hardness tests: Cold Box: read out VDC and DORIC electrically (copper wires) Shuttle: readout VDC and DORIC via optical fibers VDC and DORICs mounted on BeO opto-board shuttle can be moved in and out of beam remotelyFor both tests we monitor the VDCs and DORICs in real time.


0.2 m Ribbon

CERN Irradiation TestsSystem for Irradiation in Cold Box

BER Tester DORIC Distribution

20 MHz VDC Distribution

Beam Area Distribution

Test Boards

Coaxial

25m Ribbon+

25 m Coaxial

0.5m Ribbon

VDC orDORIC

Testing system at OSU before shipping to CERN

PC


Irradiation TestsOpto-board

Bit error test board in T7 control room

25 m fibers/wires

Bi-phase markedoptical signal

Decoded data

An irradiation testOpto-link

System for Irradiation in Shuttle

dataDORIC

clockPIN

VDCVCSEL

Opto-pack

VDCVCSEL

measure power of clock and data Vs dose


Setup for CERN’s T7 Shuttle

opto-boardsRemotely movesin/out of beam

25m of optical fibers

Optical fibers

shuttle test electronicsat OSU prior to shipping to CERN


Results from Irradiation

all other links: pseudo-random bit string and Ipin=100 uA

Opto-board #1

Thresholds independent of dose

Threshold for zero bit errors vs Dose

anneal anneal anneal anneal anneal


Opto-board #1(BeO#3)

Beam Iset = 0.6 mA (=10mA) for beam, 1.5mA (=1314mA) for annealing

Opto-board #2(BeO#4)

Irradiate for ~4-6 MRad (~4-5 hours) Move boards out of the beam and anneal for 12-15 hours VCSELs need time to annealMonitor the optical power of each link in real time.

Results from IrradiationClock Optical Power Vs Dose

anneal anneal anneal anneal anneal anneal anneal anneal annealanneal


Summary and Conclusions

VDC and DORIC chips satisfy ATLAS Specs

BeO Opto-board: Original vendor not able to produce quality boards

Have found new vendor updated layout submitted

Radiation studies: Cold Box: VDC and DORIC are more than hard enough!

Shuttle: VCSEL radiation hardness an issue

will VCSELs anneal enough to meet power specs ?

Move to Production in 2004 ~500 VDCs, ~400 DORICs, ~200 opto-boards (includes spares)

richard kass

Documents