perfect data reconstruction algorithm of interleaved adc
DESCRIPTION
Interleaving 12 14-bit ADC's to achieve >80dB SFDR at 1.5Gs/sTRANSCRIPT
Perfect data reconstruction Perfect data reconstruction algorithm of interleaved ADCalgorithm of interleaved ADC
Dr. Fang XuTeradyne, Inc. Boston, MA, U.S.A.
Presentation OutlinePresentation Outline
Purpose
Time Interleaved ADC
The reconstruction algorithm
Experiment
Conclusions
PurposePurpose
Test instruments are built with available parts Instrument development time is long Instruments are designed for testing future products Performance gap needs be solved by design
Year
Performance(frequency, bits)
Instrument architecture reduces Performance gap
State of art device performance
Future
ProductInstrument
Design-in
Time Interleaved ADC’sTime Interleaved ADC’s
Capture of a continuous time domain waveform
ADC7ADC6
ADC5ADC4
ADC3ADC2
ADC1ADC0
Clock generation
Interleaved samples
Time Interleaved Real ADC’sTime Interleaved Real ADC’s
ADC’s and analog sections have differentoffset, gain and phase
Gain and phase vary with frequencyUp-to 20 dB measured for gain !
Samples are not uniformly distributed Need advanced algorithm to reconstruct signal
Relative gain/phase (timing) error vs. 1st ADC @199.99 MHz
5 dB/div 50 ps/div
Time Interleaved Real ADC’sTime Interleaved Real ADC’s
ADC’s and analog sections have differentoffset, gain and phase
Gain and phase vary with frequencyUp-to 20 dB measured for gain !
Samples are not uniformly distributed Need advanced algorithm to reconstruct signal
ADC7ADC6
ADC5ADC4
ADC3ADC2
ADC1ADC0
Input
Clock generation
Datacorrection
reconstruction
FFT of Capture Before CorrectionFFT of Capture Before Correction
H2
offset
gain/phase
-120
-80
-40
Fi = 199.990200 MHz,Fs = 1.494220800 Gsamples/sSNR=20 dBc,Non harmonic spur=-25 dBc
100 200 300 400 500 600 700
Offset Discrepancy ArtifactsOffset Discrepancy Artifacts
100 200 300 400 500 600 700
Repetitive noise pattern Spurs at integer FsEasy to remove
H2
offset
-120
-80
-40
gain/phase
Gain Discrepancy ArtifactsGain Discrepancy Artifacts
0
Repetitive amplitude modulation Spur at ± input tone to integer FsNeed advanced algorithm
100 200 300 400 500 600 700
H2
offset
-120
-80
-40
gain/phase
Phase/Timing Discrepancy ArtifactsPhase/Timing Discrepancy Artifacts
0
Repetitive phase modulation Spur at ± input tone from integer FsNeed advanced algorithm
H2
offset
-120
-80
-40
gain/phase
100 200 300 400 500 600 700
Sampling and Aliasing at FsSampling and Aliasing at Fs
Aliased in frequency domain without Hermitian symmetry
Redundant information with Hermitian symmetry
Alias
Alias
Family of Mutually Aliased FrequenciesFamily of Mutually Aliased Frequencies
Repetitive amplitude/phase modulation Spur at ± input tone from integer Fs
That is a subset of whole spectrum
-40
gain/phase
100 200 300 400 500 600 700
We call this subset of frequencies including that of signal
A family of mutually aliased frequencies (FMAF)
Frequencies number equals the number of ADCs
Vector notation: iNMiMNiNkNikNiNi XXXXXX )12/(*
)2/(*
)(* ,,,,,
-20
Frequency Domain ReconstructionFrequency Domain Reconstruction
FsInput signal spectrumto be reconstructed
ADC7ADC6
ADC5ADC4
ADC3ADC2
ADC1ADC0
Clock generation
Fs/2
Spectrum at output of each ADC
Matrix of linear system FMAF
Orthogonal components outside FMAF Porous matrix (lot of 0)
Sampling with Hermitian symmetry Small matrix for each FMAF
iNMMikNMiMiNMiMNM
iNMmikNmimiNmiMNm
iNMikNiiNiMN
R
HHHHH
HHHHH
HHHHH
)12/,(1,1,1*
,1*
2/,1
)12/,(,,*
,*
2/,
)12/,(0,0,0*,0
*2/,0
.....
.....
H
Matrix RepresentationMatrix Representation
ADC7ADC6
ADC5ADC4
ADC3ADC2
ADC1ADC0
Clock generation
Fs/2
iNM
ikN
i
iN
iNkN
iMN
R
X
X
X
X
X
X
)12/(
*
*)(
*)2/(
ˆ
X
iM
im
i
R
X
X
X
,1
,
,0
~.
~.
~
~X
RRR XXH~ˆ
Fs
To be reconstructed Input signal spectrum
Within a family of mutually aliased frequencies
Hm,j
Unknowns and Knowns in EquationUnknowns and Knowns in Equation
Fs
Component at frequency i
iNM
ikN
i
iN
iNkN
iMN
R
XX
X
X
X
X
)12/(
*
*)(
*)2/(
ˆ
X
iM
im
i
R
X
X
X
,1
,
,0
~.
~.
~
~X
Unknown:All frequency
components within a FMAF
Captured data of all converters
Fs/2
Captured data
of converter m
at frequency i
iX
imX ,
~
iNMMikNMiMiNMiMNM
iNMmikNmimiNmiMNm
iNMikNiiNiMN
R
HHHHH
HHHHH
HHHHH
)12/,(1,1,1*
,1*
2/,1
)12/,(,,*
,*
2/,
)12/,(0,0,0*,0
*2/,0
.....
.....
H
Interpretation of Matrix CoefficientsInterpretation of Matrix Coefficients
Each coefficient is complex gain relative to system clock of a converter at a specific frequencyIt includes information on amplitude (flatness)and phase (group delay, clock delay)
To solve equation, each coefficient needs to be measured
Hm,j
Complex gain of converter
m for input frequency i
ADC7 FFT
Fs
ADC6 FFTADC5 FFT
ADC4 FFTADC3 FFT
ADC2 FFTADC1 FFT
ADC0 FFT
Input
N/2 times MxM linear equations
Order of data
Frequency Domain ReconstructionFrequency Domain Reconstruction
Solving linear equations for each FMAFReorder data according to Hermitian symmetry
RRR XHX~ˆ 1
-120
-100
-80
-60
-40
-20
Mag
nitu
de (
dBF
S)
Correction Result of Captured SignalCorrection Result of Captured Signal
Fi = 199.9902 MHz, Fs = 1.4942208 Gmples/sBefore correctionSNR= 20dBc, Non harmonic spur= -25dBcAfter correctionSNR= 54dBc, Non harmonic spur= -78dBc
100 200 300 400 500 600 700
DiscussionsDiscussions
Performance54dBc SNR @750MHZ BW = 142dBc/Hz
limited by signal generator-78dBc Spur –20dB dispersion better than
SFDR of ADC Hardware stability limitation
Ex: A 0.1% converter gain change will limit performance level to about -60dB
This does not cover non-linear distortion Application limitation
DFT can only start when entire segment of waveform has been captured
This method is a better fit for applications which do not need real time capture
ConclusionsConclusions
Solution based on general model of ADC
Gain and phase are functions of frequency
Complete mathematical resolution
Validation by data captured on hardware
Results exceed expectation
Base of high-performance instruments
Perfect data reconstruction Perfect data reconstruction algorithm of interleaved ADCalgorithm of interleaved ADC
Questions and Answers
? And !