a14b25gs/s8a 14b 2.5gs/s 8-way-interleaved pipelined adc...
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A 14b 2 5GS/s 8-Way-InterleavedA 14b 2.5GS/s 8 Way Interleaved Pipelined ADC with Background C lib ti d Di it l D iCalibration and Digital Dynamic
Linearity Correctiony
B. Setterberg1, K. Poulton1, S. Ray1, D.J. Huber1, V. Abramzon1,G St i b h1 J P K 1 B W 1 M Cl 1G. Steinbach1, J.P. Keane1, B. Wuppermann1, M. Clayson1,M. Martin2, R. Pasha2, E. Peeters3, A. Jacobs3, F. Demarsin3,A. Al-Adnani3, P. Brandt3
1Agilent Technologies, Santa Clara, CA2Agilent Technologies Colorado Springs COAgilent Technologies, Colorado Springs, CO3Agilent Technologies, Rotselaar, Belgium
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BackgroundADC for Test and Measurement Applications:• 2 5 GS/s• 2.5 GS/s• 14 bits• Less than 1 metastable error per year (10-17
metastable error probability)• 75 dB SFDR from DC to 1 GHz• 60 dB SNR60 d S• Works with arbitrary input signals
Silicon BiCMOS Process Technology:Silicon BiCMOS Process Technology:• 150 GHz fT Bipolar NPN• 130 nm CMOS130 nm CMOS
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Design ConsiderationsProblem:
Comparator regeneration time constants are tooComparator regeneration time constants are too slow to meet the metastability error rate goals at2 5 GS/s2.5 GS/s.
Solution:U ti i t l d ADC hit tUse a time-interleaved ADC architecture.
Consequence:Need to address interleaving artifacts.
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Time Interlea ed Architect reTime-Interleaved Architecture
ADC Slice 0
ADCADC Slice 1
0 1 2 3 0 130 1 2 2 3 0 1 2 3 0
ADC Slice N
D i t l InterleaveDe-interleave Interleave
ADC slices need to be very well matched in offsetADC slices need to be very well matched in offset, gain, sample time and bandwidth.
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Interleaving StrategyAchieve an aggregate 2.5 GS/s by interleaving eight 312 5 MS/s slicesinterleaving eight 312.5 MS/s slices.
8X 312.5 MS/s ADC Slices
Input
ADC
312 5 MS/312.5 MS/s
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Slice ADC Architecture3.5 bits
+ Voltage to 1 bit per stage,
radix-1.7redundancy
15-level flash
gcurrent
convertercurrent-mode
pipeline1
Radixx C
onve Binary GmStage 1 Stages
2-16
15
In erter Output16In
Background Calibration Engine
1K. Poulton, et al., “A 4GSample/s 8b ADC in 0.35µm CMOS,” ISSCC Dig. Tech. Papers, vol. 45, pp. 166-167, Feb. 2002. 6
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ADC First Stage Block Diagram‘1’ 161‘0’
16
13 To Radix C t
DAC
Converter
Permuter16
1
Permuter
PA
0
Dither
Residue Amp
CLK
Perm
uteA
ddress
Background Calibration Enginer
IN
e
7
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ADC Stages 2 - 16D
In
D
In
ResDith
In
Res
In1.7 X 1.7 X
St 2 St 3 St 11 St 12 St 16Stg 2D
Stg 3D
Stg 11D
Stg 12D
Stg 16D
In ResDith
In ResDith
In ResDith
In Res In
Background Calibration Engine UncalibratedStages 8
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Interleaving Errors
Mismatched paths cause:• Distortion and jitter• Spurs in the spectrum
Gain Error(need < 0.01% gain matching)
Sampling Instant Error(need < 20 fs timing skew)
Offset Error(need < 100 µV offsets)
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Minimize Sampling Time Errors with a 2 rank Track and Hold2-rank Track and Hold
8X 312 5 MS/sRank 1
T/HI t
8X 312.5 MS/s ADC Slices
Rank 2 T/H
ADC
Input
ADC2.5GS/s Low-Jitter Sampling
Clock (<70 fsRMS) 312.5 MS/s
•First rank T/H clocked at full system sample rate•Sampling instant defined by first T/H
( RMS)
•Sampling instant defined by first T/H• Insensitive to errors from slice-rate clocks 10
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Slice-to-Slice Gain & Offset Alignment
D ADCDither
DA
C
ADCG
a
Of
Chop PRBSDither
ain
ffset
Background Calibration Engine
Chop PRBS
• Injected dither provides an absolute gain reference• Chopping allows offset calibration with arbitrary input 11
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Chop and Dither InjectionR2R1
M4M3
OutDither
Bootstrap
Chop
Q2Q3Q1 Q4p
amplifiers
ChopPRBS
In M2M1In M2M1
In
Liability: Large Vds swings on M3 and M4 induce 0.1% PRBS-modulated thermal transients. 12
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Chopper Transient Removal•Uncorrected transient degrades SNR by 6 dB.•Transient removed with a poly-phase fast FIR filter.p y p•Foreground self-calibration finds filter coefficients.
Chop Filter
8 Slices
Dithe
DA
C
ADCFilter
er C
Chop PRBSDither
Background Calibration Engine
p
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ADC Block DiagramD
yna
Outp
Chop
Rad
amic Lin
put MU
X
Per-slice DSP
Filter
dix ConvADCDD
nearity C
XO
uverter
Dither
DA
C
Correct
Dither
Offset
Chop
Gain
utput MUor
DitherChop PRBS
UX
Background Calibration Engine14
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Digital Dynamic Linearity Correction
• Analog circuit nonlinearities include:Analog circuit nonlinearities include:• Nonlinear settling• Track switch nonlinearityy• Signal-modulated aperture time
• Error characteristics:• Error characteristics:• Functions of signal history• Frequency-dependentFrequency dependent• Partially correctable if we know both the
sample and its derivative
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Digital Dynamic Linearity Correction• Estimate the derivative of the signal.• Calculate selected 2nd- and 3rd-order
d t f th i l d it d i ti
x’
Slope est. filter
products of the signal and its derivative.• Calculate the correction as a weighted
sum of the product terms.dx/dt
2 3’ 2
x
( ’)2 ( ’)2’
Product Term Multipliersx
p
x2 x3x’·x2(x’)2 x·(x’)2x·x’
Programmable CorrectionCorrection Coefficients
Input x Out
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Slope Estimation FilterIdealIdeal
)|
Infinitely long impulse response H(f) = j2πf
|H(f)
response
0 Fs/2
Practical
Truncated impulse H(f) j2 f
presponse
|H(f)
| H(f) ≈ j2πf
170 Fs/2
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Dynamic Linearity Corrector Performance ( 1 dBFS Input)
90
95Performance (-1 dBFS Input)
90
85
B)
80
75
DR
(dB
70
65
SFD
60
55
SFDR with DLCSFDR without DLC
550 200 400 600 800 1000 1200Input Frequency (MHz) 18
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INL with a 450 MHz Input Signal
+2.0
SB
)
+1.5+1.0
14b
LS +0.50
INL
( -0.5-1.01-1.5
-2.0-8000 -6000 -4000 -2000 0 +2000 +4000 +6000 +8000
Code8000 6000 4000 2000 0 2000 4000 6000 8000
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Power Spectrum
-100
-1 dBFS at 1052 MHzRBW = 2 44 MHz
dBFS
)
-30-20
Without calibration or DLCWith calibration and DLC
RBW = 2.44 MHz
tude
(d
-50-40
With calibration and DLC
Mag
nit
-70-60
M
-80
0 200 400 600 800 1000 1200
HD2 HD3
0 200 400 600 800 1000 1200
Frequency (MHz) 20
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Ti i t l d ADC100
Performance Comparison
Published ADCs(ISSCC and VLSI)
Time-interleaved ADCs90
80
(dB
)
This work
(ISSCC and VLSI)80
70
SFD
R
60
5050
40
Bandwidth
3010MHz 100MHz 1GHz 10GHz 100GHz
Source: B. Murmann, "ADC Performance Survey 1997-2012.” http://www.stanford.edu/~murmann/adcsurvey.html
Bandwidth
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Power Dissipation by FunctionFunction Power
(Watts)(Watts)2-Rank Track & Hold 2.5Clock Distribution and Clock Divider 1 8Clock Distribution and Clock Divider 1.88 ADC Slices 13.1Digital Signal Path and DSP 2.6g gBackground Calibration 2.7Output Data Ports 1.2Total 23.9
Interleaving is expensive!22
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Die Photograph
7.4 mm x 14.0 mm SiGe BiCMOS 23
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Performance SummaryS 2 GS/Sample Rate 2.5 GS/sResolution 14 bitsSignal to Noise Ratio (SNR) 0dBFS Input 61 dBSignal to Noise Ratio (SNR), 0dBFS Input 61 dBNoise Spectral Density @ 2.5 GS/s -152 dBFS/HzSpurious Free Dynamic Range (SFDR)Spurious Free Dynamic Range (SFDR)DC - 1 GHz, -1 dBFS Input 78 dB
INL ±1.5 LSBSampling Clock Random Jitter 70 fsRMS
Metastable Error Rate (extrapolated from <10-17
over-clocking experiments) (<1 error/year)Input Impedance 50 Ω differentialO t t LVDSOutputs LVDS
Performance maintained with continuous background calibration.24
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Summary
High performance time-interleaving:• 2-rank track and hold• Extensive background calibration (224 loops)
Background calibrations operate continuously• Background calibrations operate continuously regardless of input signal statistics
• Digital dynamic linearity correctionDigital dynamic linearity correction
Results:Hi h t t d SFDR f ti i t l d ADC• Highest reported SFDR for a time-interleaved ADC
• Highest reported SFDR at 1 GHz bandwidth
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AcknowledgementsgThe authors thank the following individuals for their valuable contributions to this work:
Mauro Berdondini Mike Rytting
valuable contributions to this work:
Mauro BerdondiniSteven CoenenLewis Dove
Mike RyttingJimmy StorieGary ThomasLewis Dove
Bart GybelsJeanne Kaneyuki
Gary ThomasJoseph TranRamesh Vema
Pete MartinezBrad McCormackD P tt ill
Lynne ViaggiYunqiang Yang
Don Pettengill26