Practical Considerations for Application SpecificTime Interleaved ADCs

Aaron Buchwald

Abstract—Time interleaving provides an additional degree-of-freedom in achieving ultra-fast quantization at reasonablyhigh resolution, However, mismatches in multiple paths of thesignal chain create systematic errors. Mitigating all possibletime-interleaved errors comes at a heavy cost in complexity,risk, power and performance. Knowing which errors are mostimportant and which can be neglected in any given application isessential for picking an appropriate architecture and calibrationscheme. This paper will review specification requirements, specif-ically for frequency division multiplexed channels where timeinterleaved ADCs are finding increased use. Instead of lumpingall error sources into a single metric such as ENOB, differenttypes of error sources are treated separately to determine theirimpact on overall system performance.

I. INTRODUCTION

Parallel processing of ADCs leads to performance gains byexploiting efficient arrays of reduced speed quantizers thatoperate on sub-sections of the signal, partitioned usually intime [1], [2] or perhaps in frequency [3]–[5]. Interleaving inthe time-domain, Fig. 1, is more widely used as frequency sub-banding approaches require precise knowledge of channelizingfilter transfer functions and therefore more computationallyintensive reconstruction and calibration.

Whether paralyzation is implemented in the time- or fre-quency domain, the very nature of interleaving forces theinput signal to branch and traverse multiple paths on itsway to the output. Physically distinct circuits process varioussub sections of the signal: any mismatch results in pattern-dependent artifacts. Sources of errors and their impact on thecombined output of parallel ADCs have been analyzed anddescribed as early as the 1980s [6], [7], further into the 1990s[8], [9], and more recently by several authors [10]–[15].

Often the goal of proposed calibration techniques are ambi-tious with aims to provide workable solutions for virtuallyall classes of input signals. With mixed-signal SoCs beingmore common due to ever increasing integration, rarely are weconcerned with general applications, but need only concentrateon the specific. The two most common embedded applicationsfor time-interleaved ADCs are: 1) channelization of multi-channel frequency division multiplexed signals such as incable and satellite TV and 2) baseband applications for opticaland backplane transceivers. The first is best understood byviewing signals and errors in the frequency domain, whilethe second is easiest to understand in the time domain. Thispaper will focus on the requirements and impact of errorsources on ADCs for the first class of applications, broadbandfrequency channelization. Error sources will be revisited in thecontext of their sensitivity to overall system performance for

ADC

Clk1

DADC1

ADC

Clk2

DADC2

ADC

Clk3

DADC3

ADC

Clk4

DADC4

INV

Cal

ibra

tion

Fig. 1. Block diagram of a four-slice time-interleaved ADC.

these specific applications. ADCs for baseband applicationscan be viewed similarly, but differing requirements will leadto different choices for optimal design.

A. Multi-Purpose vs. Application Specific ADCs

By definition there are two classes of data converters:multi-purpose and application-specific. The most stringentrequirements are placed on multi-purpose ADCs for test-and-measure applications and stand-alone off-the-shelf converters.Without a knowledge of the input signal, all possibilities mustbe considered and accounted for. No simplifying assumptionsare allowed, thus making background calibration ”blind” andmore challenging. Furthermore, there is little tolerance fornon-idealities. In demanding applications for spectral analysisequipment, no trace of time-interleaving spurs can be tolerated.Although achieving calibrated results of 80dB SFDR at 2.5-GS/s is difficult, it is nevertheless possible [2], albeit at thecost of increased complexity and power.

This level of sophistication in calibration is difficult tomatch for high-volume SoCs (System on Chips). Fortunatelymost embedded applications do not require it. Additionally,overall performance is much less sensitive to some types oferrors than others. Armed with this knowledge, targeted sim-plifications can be made which leads to optimal architecturalchoices and drastic improvements in power, area, risk and cost.

II. ADCS FOR BROADBAND MULTI-CHANNEL SYSTEMS

Historically, multi-channel communication systems, such asbroadcast video, distributed independent channel informationacross a wide frequency band. In the case of both cableand satellite, a significant investment in hardware and systemprotocols makes it advantageous to continue using existing

ACI

desired in-band channel

tilt A

mpl

itude

Fm Fs /2 Frequency

Digitized Cable TV Spectrum

Fig. 2. Snapshot of cable TV spectrum.

ADC

IQ PLL

X

X 90o Delay

ADC

+

ADC

IQ PLL

X

X 90o Delay

ADC

+

ADC

IQ PLL

X

X 90o Delay

ADC

+

Digital

Fig. 3. Implementation of multiple analog direct conversion tuners followedby lower speed baseband or IF ADCs.

channels. Any incremental upgrade in services or increase indata rates must operate within the confines of pre-definedfrequency boundaries. An example of a cable spectrum isshown in Fig. 2. The bandwidth extends from approximatelyDC to 1-GHz. It contains legacy analog channels together withstandard-definition and high-definition digital television plusinternet protocol data. Traditionally a user would be interestedin only one channel of video or data at a time. Only one tunerwas needed for channelization and down-conversion, whileone receiver was needed for demodulation. With the continuedappetite for bandwidth, two separate service enhancementsdictate the use of multiple channelizers: gateways and gigabit-per-second modems.

To increase cable modem throughput using the existinginfrastructure of the cable network multiple channels areneeded. It is possible to transmit approximately 38-Mb/s ina single 6-MHz channel. For higher data rates, approachinga throughput of 1-Gb/s, approximately 24 physical channelsare logically bonded, appearing to the user as a single 1-Gb/s link. Providing frequency translation, down-conversionand channelization of 24 channels by traditional means inthe analog domain, requires several direct-conversion tunersas represented in Fig. 3. Synthesis of center frequencies,multiple harmonic rejection mixers, filters and image rejectionfunctions all must be accomplished by analog circuits. Chan-nelized baseband signals are eventually sampled with a parallelbank of low speed ADCs. Crosstalk and sensitivity becomesignificant problems as many critical functions residing in theanalog domain require high accuracy and isolation.

ADC

φ1

THA ADC

THA

+

-

ADC

φ1

THA ADC

THA

+

-

ADC

φ1

THA ADC

THA

+

-

Digital

Cal

ibra

tion

2

N

Fig. 4. One single time-interleaved ADC followed by digital channelizerstakes the place of several analog tuners.

Alternatively, all-digital channelization can be used,whereby a single ADC is moved to the front-end, providedit has enough bandwidth and resolution to capture the entirespectrum at once. Such an architecture using a time-interleavedADC is illustrated in Fig. 4 and can be implemented for cable[16], [17] or satellite [18]. This approach, though radicallydifferent from that of Fig. 3, uses many of the same sub-blocks.Track-and-hold circuits replace mixers. An array of sub-sampled time-interleaved ADCs replace the baseband ADCs.All the analog accuracy requirements are now localized to thefront-end of the ADC and no frequency synthesis is needed assampling occurs at a fixed rate. Signal processing happens afterquantization in the digital domain where frequency synthe-sis, down-conversation and image-rejection are accomplishedwithout error or crosstalk. Best of all, the digital channelizersare portable and scalable to as many channels as desired.

III. CATEGORIES OF PRIMARY ERROR SOURCES

Primary error sources in time interleaved ADCs are shownin Fig. 5. The first column is fundamental, including additiverandom noise and quantization. Additive noise is dictated byKT/C and 1/gm. No amount of calibration can reduce theseerror sources: they can only be mitigated by brute force design— reducing thermal noise requires an increase in either area orpower. Likewise, sufficient levels must to be included to ensurequantization noise is not detrimental to overall performance.This simply entails increasing the number of physical bits inthe converter.

Errors in the second column of Fig. 5, describe distortionmechanisms present in any single-slice ADC. These includequasi-linear distortion from the front-end buffers and track andhold, linear and nonlinear radix errors and element mismatch.Calibration is often used to eliminate these errors within asingle ADC slice without increasing area and power. Fig. 6illustrates linear radix correction of a pipelined ADC. Providedthat the interstage gains are known, the linear radix for eachstage can be adjusted for correct signal reconstruction. Thiscan also be implemented as a nonlinear combination of thesub-codes D1–D4. Possible background calibration methods

Fundamental Single-Slice Distortion

Noise

Quantization

Smooth INL

Time Interleaving

Offsets

Gain

Time-Skew

Radix errors

Cap Mismatch

probability INL Fs/2 Fs/4

Fs/2 Fs/4

Fs/2 Fs/4

probability

Fig. 5. Summary of errors in time-interleaved ADCs. Those in bold areadditive, whereas the others are multiplicative and therefore either proportionalto signal amplitude or to the signal amplitude raised to a power such a V 3

a .

Stage #1

Stage #2

Stage #3

Stage #4

D1 D2 D3 D4

x = D1 +D2A1+D3A2A1

+D4A3A2A1

x

Fig. 6. Linear radix calibration. The optimized digital output is a linearcombination of the digital outputs of each of the pipelined stages.

add a dither signal into the residue prior to amplification[2]. The dither can be explicitly added [19] or by addingan extra level to the DAC and modulating it with a pseudorandom sequence [20], [21]. The nonlinearity is then estimatedin the background through statistical analysis or through de-correlation of the output of the dithered nonlinear amplifierwith the dither sequence. While [22], [23] provided a solidframework for calibrating linear errors in a pipelined ADC, theextension to nonlinear calibration is more complex as notedin [22], the desired approach is a computationally efficienttechnique that operates in a nonlinear fashion directly on theraw digital bits of the pipeline, referred to as the code domain,[24]. This, together with a look-up table, compensates for thestatic nonlinear transfer function of the interstage amplifierand MDAC.

The third column of errors are those associated with multi-path mismatches which only become problematic in the pres-ence of time-interleaving. These include offset errors whichare often viewed as static. Offsets can drift due to 1/f noiseproducing artifacts that show up in the output spectrum ifthe correction bandwidth is not fast enough. Mismatch ingains generate amplitude modulated errors while time skew insamplers result in phase modulation of errors with the inputsignal. Additional variations in bandwidth of the slices makesthe gain and time-skew errors both frequency dependent andnon-orthogonal.

A. Additive vs. Multiplicative Errors

All error sources affect the signal in either an additive ormultiplicative way. Additive errors are thermal noise, quanti-

PPV

Fig. 7. Probability density function of a single sine wave of amplitude a.

zation, radix errors, element mismatch and offsets. These arethe most problematic in frequency channelization applicationsbecause they do not scale with the signal. As the amplitudeis reduced, signal information eventually drops below thefixed noise. Conversely, multiplicative errors are much lessimportant. These errors reduce accordingly when the signalenergy drops, meaning if the SNR is adequate for largesignal, it is still adequate when the signal is small. Whendesigning a time-interleaved ADC for broadband capture, itis precisely these multiplicative errors, namely smooth, quasi-linear distortion and mismatch of gain and time skew that canbe significantly relaxed. This leads to design tradeoffs whichdrastically simplify the front-end circuitry and the calibrationscheme.

B. Subtle Effects and Problems with Simple Metrics

One of the difficulties in producing an optimal multi-channel time-interleaved design from a standard list of metricsis that traditional ADC specifications assume a sine waveinput. Any metric can have contributions from many differenttypes of error sources. For example, THD (Total HarmonicDistortion) may result from compressive distortion of thesmooth quasi-linear front-end transfer function, but it alsoarises due to ”jagged” radix errors and element mismatch.These errors scale differently with amplitude, rendering alumped specification for THD virtually meaningless. We donot care much about lumped THD. What we care about ishow the THD scales with amplitude. What is needed then isa separate specification for ”smooth” multiplicative distortionand abrupt, ”jagged,” distortion, otherwise the ADC is likelyto be over-designed in one area and under-designed in another.

C. Clipping and Distortion

Back-off desensitizes ADC-based broadband channelizers tomultiplicative error sources. In order to prevent hard-clipping,the rms level of the signal is set significantly lower than for afull scale sine wave. Previously when dealing with a singlebaseband channel the optimal signal level was determinedby the peak-to-average ratio of a given modulation technique(256 QAM). For broadband applications, where hundreds ofchannels are captured simultaneously, the modulation schemein any one channel is irrelevant. Independent signals combineto produce a Gaussian distribution regardless.

Despite the actual distribution of the input signal, ADCs aregenerally specified assuming a full-scale sine wave input of theform a cos (2πfnt) which has a probability density functionshown in Fig. 7. If 128 independent sine waves spanning thespectrum are added, but are not allowed to clip, each tone

PPV

very little signal activity at the ends.

Rare occurrence.

Fig. 8. Probability density function of 128 equal amplitude sine waves.

PPV

Hard clipping at ADC

significant clipping occurs

Fig. 9. Probability density function of 128 equal amplitude sine waves. Eachtone is scaled down by a factor of

√128.

needs to be scaled linearly.

a

128

128∑

n

cos (2πfnt) . (1)

The resulting probability density function is nearly Gaussianas Fig. 8 shows. Clearly, most of the signal energy is centeredin the middle with a large percentage of extreme levels rarelyexercised. To improve SNR the amplitude must increase.However, putting the rms level back to that of a full-scalesine wave via square root scaling, results in the probabilitydensity function of Fig. 9, which will exhibit significant hardclipping.

D. Optimal Back-off

Knowing that the signal is Gaussian distributed can beexploited to determine the optimal back-off. For discrete tonesthe scaling is backed-off relative to a full-scale sine wave bykbo.

1

kbo

a√128

128∑

n

cos (2πfnt) (2)

Initially considering an ”ideal” ADC, when this backed-offGaussian distribution is applied to the input, the error is zerofor all levels. Errors only exist due to an over-range conditionand increases linearly with the difference between the signaland the clipping level. This is illustrated in Fig. 10. Thesquared clipping error, or cost c(x)2, is multiplied by theprobability, producing a weighted error energy. For a Gaussianprobability density, the average squared error is calculated as

errsq(σ) =1

σ√

2π

∫ ∞

−∞c(x)2 · e− 1

2 ( x−µσ )2

dx (3)

Optimal back-off depends on the level of additive noisepresent. If the noise is large as illustrated conceptually inthe top half of Fig. 11, The signal level can be increasedfurther before clipping-induced distortion becomes dominant.However when the additive noise is small, as in the lower partof Fig. 11, the distortion will exceed the additive noise at asmaller signal amplitude. A family of curves can be plottedfor various additive noise levels to determine the back-off that

INL Assume an Ideal INL Profile

PPV

Clipping error

Clipping error

Signal Probability

Weighted squared

error

Weighted squared

error

INL2

Squared error

Fig. 10. For an ideal ADC there is no error in the operating range. As thesignal clips, the error is equal to the difference of the signal value and theclipped value.

Clipping Distortion

Total Noise

Clipping Distortion Vpp RMS

Vpp RMS

errsq(�) =1

�p

2⇡

Z 1

�1c(x)2 · e�

12 (

x�µ� )

2

dx

Gaussian Squared

INL

Fig. 11. Changing the back-off impacts the total error due to clipping. Thehigher the noise floor the larger the signal needs to be before the distortionequals the integrated noise.

8910111213141526

28

30

32

34

36

38

40

42

44

Backoff with respect to Full−Scale (dB)

SNR (dB)

8.3-bit Front-End Noise

7.3-bit Front-End Noise

6.3-bit Front-End Noise

Backoff with respect to Full-Scale (dBFS)

15 14 13 12 11 10 9 8

28

30

32

34

36

38

40

42

Fig. 12. For low amplitude signals increasing amplitude increases the SNRone dB per dB until clipping dominates and SNR falls abruptly. The optimalback-off depends on the level of additive noise.

produces the best SNR. Fig. 12 illustrates the optimal back-offwith respect to full-scale for cases where the front-end noiseis at three different levels. For 6.3-bits of additive noise theideal back-off is 11-dBFS, while for additive noise of 8.3-bitsthe signal must be attenuated further to 12-dBFS to obtain thepeak SNR.

E. Optimal Back-off with Distortion

The impact of distortion on the overall error is evaluatedin the same way as clipping. Rather than assuming the INLprofile is ideal, the actual ”smooth” memoryless transfercharacteristic such as that coming from compressive distortionin the front-end is used, Fig. 13. This squared error now begins

INL Continuous Time or Quasi-Linear Distortion Amplifiers, Buffers, THA

INL2

Extreme INL errors are still stimulated by the tail of a Gaussian signal although much less frequently

Squared Error due to quasi-linear distortion

THD improves 2dB per dB for sinewaves

Total integrated distortion ratio improves 1dB per dB for broadband

Fig. 13. INL errors for compressive distortion with overlay of Gaussian andsingle-tone probabilities.

−1.5 −1 −0.5 0 0.5 1 1.50

0.005

0.01

0.015

0.02

0.025

0.03

Normalized Input Signal

Prob

abili

ty ×

Err

or2

Errors Due to Clipping with Broadband signal At 11-dB Backoff = 7.8 bits

Errors Due to Clipping with Broadband signal At 11-dB Backoff =7.8 bits

Errors Due to LNA Distortion = 7.67-bits

Fig. 14. The optimal back-off level must include the static distortion. Thismethod allows calculation of overal system sensitivity to distortion.

to increase and show soft-clipping before full-scale is reached.Weighting the squared error by the probability density functiongenerates a family of weighted error curves: one example isshown in Fig. 14. The total error is found by integrating. Theback-off needed to achieve optimal SNR is obtained and willbe somewhat higher (lower signal) and the peak SNR willbe lower than for an ideal ADC. The actual back-off settingdepends on the distortion profile of the front-end circuits.

1) Quasi-Linear vs. Abrupt Discontinuities: There aremany types of distortion. The INL profile used in the ad-justment for back-off should consider only the quasi-lineardistortion which arrises from buffers and track and hold cir-cuits. It should not account for abrupt nonlinearities from radixerrors or capacitor mismatch. To determine how distortionimpacts overall performance, consider the probability densityfunction for a sine wave. This has the same rms value as theGaussian as shown at the bottom of Fig. 13. Large distortionat the extremes of the input range are never seen by the lowamplitude sine wave and are not exercised at all. Distortionfor a sine wave is reduced by the cube of the back-off for asystem dominated by the 3rd harmonic while the signal itselfis reduced linearly: the resulting THD improves by the squareof the back-off or 2-dB per dB.

The key observation that allows for relaxed distortion inADC designs is seen from Fig. 13. The signal energy fora broadband signal is primarily concentrated in the centerwhere the transfer function is linear. The tails of the Gaussianrarely hit the larger compressive distortion errors. It is found inpractice that this distortion can be relaxed by approximately

the rms back-off relative to a full-scale sine wave or 1-dBper dB. For example, an ADC requiring a 62-dB (10-bits)noise floor with an optimal back-off of 15−dBFS (12-dB withrespect to a sine wave) will have a distortion requirementof only 62- minus 12- or 50-dB (8-bits). This reduction inrequired accuracy of the front-end buffers and track and holdby two bits, significantly simplifies the design and impactsarchitecture and circuit choices.

F. Time Skew ErrorsSignals are generally sampled on a uniformly spaced grid.

Any timing variations causes the value to differ from what isexpected. For small timing deviations, errors are proportionalto the timing skew and the slope of the signal at the samplinginstant.

err(nT ) = ∆t · ∂s(t)∂t

∣∣∣∣nT

(4)

Integrating the squared error over a full sine wave period, theSNR is found to be

1

SNR= 2πfin∆trms (5)

Because the error of a single tone is proportional to the signalslope and therefore proportional to the input frequency, lowerfrequencies have lower time skew errors. Finding the overallnoise in general requires taking the derivative of the completespectrum. This can be approximated quite accurately assuminga flat spectrum. Because the noise adds in an rms fashionhowever, the integration of squares involves a factor of 1/3in squared noise. Therefore, it’s not surprising that the totalbroadband noise relative to the maximum frequency is reducedby√

3 (4.77-dB). Time skew is also a multiplicative error.The accuracy is significantly relaxed in the presence of back-off. Continuing with an example of an ADC with a 62-dBnoise floor, time skew requirements are reduced by 12-dB dueto back off and another 4.77-dB from the above broadbandconsiderations. To achieve a noise floor of 62-dBFS, the timeskew needed is only 62- minus 12- minus 4.77 or only 45.23-dB. The rms timing accuracy needed to achieve this moderateSNR is given by

∆trms =1

SNR · 2πfmax(6)

For a maximum frequency of 1-GHz the timing skew accuracyis relaxed to 869-fs as opposed to 126-fs which would havebeen needed to achieve 62-dB. For this rms skew of 869-fsthe ±2σ peak-to-peak spread is 3.75-ps or ±1.75-ps. Thisdesign target is within the limits to achieve without requiringbackground calibration.

G. Gain ErrorsGain errors are simple to calculate and are clearly propor-

tional to the signal. Therefore, a one percent mismatch in gainresults in an error signal with an amplitude of one percent ofthe intended signal. For a converter with 62-dB additive SNR,and back-off of 15-dBFS the gain accuracy needs to be 62-minus 12- or 50-dB. This can easily be achieved digitally sothat all slices are matched to better than 50-dB.

H. Offsets

It is straightforward to approximate the level of offsetcorrection needed. Broadband noise spreads evenly across theentire Nyquist band. The amount falling in any one channel ofbandwidth fBW is equal to the equivalent quantization noiseof n effective bits improved by the processing gain such that

ninband = nnyq

√fBW

fs/2. (7)

If the total energy from all offset errors is split equally betweenNslice/2 bins then the rms offset tone, which falls in oneof the desired channels needs to be smaller than the in-bandnoise. If a margin of 2nmargin is assumed to avoid the offseterror dominating the SNR, then the accuracy of the offsetcorrection needs to be significantly better than the resolution ofbroadband noise. The offset accuracy required is given belowin bits.

noffset = nnoise + nmargin+

16.0210 log

[fs/2fBW

]− 1

6.0210 log[Nslice

2

] (8)

This calculation is best represented by example. If a 12-bitADC is implemented with a 10-bit (nnoise) noise level and asample rate of fs equal to 3.6-GHz where the bandwidth ofeach channel is 6-MHz (fs), then the resolution of the offsetcorrection needed for Nslice = 4 is

noffset = 10 + 1 + 4.11− 0.5 = 14.6 bits (9)

Although the converter outputs 12 bits and has a 10-bitnoise floor, the offset needs to be corrected to the equivalentquantization noise of 14.6 bits (1/(214.6

√12)). This is 1-LSB

error at the 16.4 bit level so offset correction needs to extendto 16 bits to avoid corrupting performance in the channels inwhich the offset spurs fall.

IV. ARCHITECTURE CONSIDERATIONS

System SNR is 2-bits less sensitive to distortion, gain andtime-skew errors. Relaxing front-end distortion leads one touse as few slices as possible. Even if there is distortion inthe input network due to insufficient tracking or settling time,the modest requirements of 50-dB are not difficult to meet andlikely would not necessitate additional parallization to increasetracking or settling time. Four slices allows symmetric layout,balanced loading and simple clock generation. 1 An exampleof a four slice architecture is shown in Fig. 15, [17], [25]. Thedesign for both the clock and input network can be laid outin a star configuration, thus matching these paths to all fourslices as closely as possible. Offsets and gain errors are easy toremove statistically by setting the mean and variance of eachslice to that of a master slice. Since the requirement for timesskew (section III-F) is only to maintain a peak-to-peak range

1Using two slices is not a good choice. Time-interleaving entails manycomplications, so that if the design can be achieved with two slices, oneought to eliminate all the calibration and try harder to achieve performancegoals with only one slice.

INV

ADC

Clk1

DADC1

ADC

Clk3

DADC3

ADC

ADC

Calibration

Clk2

DADC2

Clk4

DADC4

Calibration

ClkFs

Fig. 15. Four slice time-interleaved ADC for cable applications.

of 3.5-ps, several simplifications in the calibration algorithmcan be adopted. A course correction of any systematic skewcould be made during factory test or at start-up. Calibrationcan remain frozen thereafter. Background adjustments are notnecessary as the differential skew will track temperature andvoltage changes to well within range.

V. SECOND-ORDER EFFECTS

Nonidealities in physical implementations result in errorsources being both nonlinear and correlated. Although all theprimary errors were described as independent in section III,problems arise when these errors interact with each other,which impacts global convergence and causes limit cycling orsettling to non-optimal points. An assortment of these effectsare described in the context of the ADC of the followingsection.

A. 8x Time-Interleaved ADC with Slow Reference

An example of an eight-way time interleaved pipelined ar-chitecture is shown in Fig. 16. A slow (∼ 1-MS/s) recirculatingADC with dynamic capacitor shuffling is used to provide areference sample: the error between the actual sample and thereference is used to drive all background calibration. A singleLMS loop converges all error sources simultaneously [24].Within each ADC slice the radix is corrected: a lookup tableis populated to mitigate errors due to capacitive mismatch inthe MDAC. The gain, offset and time-skew errors of each sliceare corrected by forcing them to match the reference ADC.System-identification (SI) methods are used for calibration inthis design. Since LMS updates are driven by observationsfrom a known reference, this approach, which is common incontrol systems and adaptive equalizers, is known to be robustand have good convergence properties.

The layout of the ADC is shown in Fig. 17. All calibrationcircuitry resides on chip as does an 8k-sample memory foruse in test. All error correction is performed exclusively inthe digital domain, directed only by the magnitude of the sub-sampled error between the main ADC slices and the referenceADC, with the exception of the sample phase. Time-skewcorrection is similar to clock recovery in that informationabout both magnitude and direction are necessary. Here, ahybrid approach is used to determine direction, which is acombination of small additional analog and digital circuitry[26]. The LMS engine then drives a digital code, which in

IV

SLOW ADC - TH

Measure & Compare

LMS Calibration

x! =G ⋅ y(D1,D2 ,D3,D4 )+Voff

1D 2D 3D 4D

Radix and Cap mismatch correction

Stage #1

Stage #2

Stage #3

Stage #4 TH

8

Fig. 16. Block diagram of an eight-slice time-interleaved, backgroundcalibrated ADC.

AGC

HIGHSPEED

INTERFACE

PLL

SERIAL INTERFACE

2.7  GS/s12-­‐b  ADCLNA

Tx

Tx

DDFS

LOWPASSFILTER

LOWPASS FILTER

24  Digital  Tuners

XTALOSC

BUF

PLL#&#

CLK#Gen#

LNA##&#

PGA#

Memory#

Calibration#FFT#Processor#

Channelizers#1:12#

Channelizers#13:24#Serial#Output#

Fig. 17. Layout of a 2.5GS/s 12-bit ADC with 71dB SFDR through the firstNyquist zone and 60dB through the 3rd Nyquist zone.

0 200 400 600 800 1000 1200-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

Am

plitu

de d

BFS

3rd

Nyquist Zone 1 1

Am

p

1GHz 2GHz 3GHz 4GHz 5GHz 6GHz

SFDR 75dBc

Frequency (MHz)

Fig. 18. Measured frequency response with an 8k-sample FFT for an inputin the first Nyquist zone, fin = 252-MHz and fs=2.525GS/s.

turn adjusts the edge position of eight capacitive clock-delay-DACs, thus closing time-skew correction in the analog domain.

B. Kickback and Vdd Modulation

A measured 8k-sample spectrum of the ADC with a 2.525-GHz external sample clock and an input near fs/10 is shownin Fig. 18. SFDR of 75-dBc is achieved and is limited by thethird harmonic of the input buffer and track and hold Despiteeffective background calibration, artifacts of time interleavingremain in the output spectrum. Global convergence using oneLMS engine has the potential to achieve an optimal solutionassuming all error sources are orthogonal. The extent to which

the calibration is incomplete is due to the limited resolutionof the correction circuit (50-fs step size for skew adjust) andthe fact that error sources interact. Albeit small, the calibratedspectrum still shows some artifacts of time-interleaving, whichare visible. These artifacts are common and also seen in otherimplementations at various levels. [27], [28].

Slice-dependent kickback provides an explanation for in-complete convergence as was identified in the lab [29]. Kick-back on any one slice will be sampled on the successive slicesuntil it completely settles. Any kickback independent of thesignal appears as an offset when it is subsampled by the nextslice and mixed to DC. Signal dependent kickback results ina linear filter. This alters gain and skew errors in a frequencydependent way. In the design of Fig. 16 the timing adjustmentsare made in the analog domain. Whenever the time instantmoved, the kickback changed. This changed offsets and causedfrequency dependent gains and time skews. The LMS loopwandered around in a limit cycle trying to converge all errorssimultaneously. Interactions of error sources will always pre-vent the total system error from converging to its ideal value.Improving this situation must be addressed at the architecturallevel as described in the following section.

VI. ARCHITECTURE CONSIDERATIONS

Because there is no perfect isolation between slices, errorsources interact when adjustments are made in the analogdomain. Kickback and instantaneous Vdd droop modulates thesignal. In order to minimize this interaction a hybrid approachcan be adopted. Course analog adjustments are used to get thecircuit close to ideal performance followed by fine adjustmentsin the digital domain.

Digital time skew adjustments require filtering at full-speed. Although a general purpose interpolation filter can becostly, a simpler method using a digital slope estimator ismore efficient. The correction at each sample is estimatedby multiplying ∆t by the slope [27]. Implementing timingcorrection with a slope estimater is economical when cal-ibrating nonlinearities of buffer and track and hold [2] asthe slope of the signal is also needed to correct dynamicdistortion in the front-end. An efficient and robust calibrationscheme is illustrated in Fig. 19. It uses a slope estimationfilter for both time skew correction and as input to a Volterrafilter which corrects for front-end nonlinearity. Digital finecorrection breaks the interaction between control loops makingerror sources orthogonal which leads to more predictableconvergence. This architecture has the ability to achieve highlinearity of the front-end via calibration and very low residualtime-interleaving artifacts.

VII. CONCLUSION

ADCs are specified assuming a full-scale sine wave isapplied as an input. However, performance of the converterwith a single tone is not representative of ADC performancewith actual signal statistics. ADCs for broadband channelizersmust back-off the rms level of the signal to avoid hardclipping. As the input is broadband, Gaussian-distributed and

ADC

XTAL OSC PLL

PGA LNA

Course Skew 500-1000fs

Non-Linear MDAC

RMS

Σ X

d/dt X

ΔT

Σ

a( ) 3

b( ) 3

Σ

Σ

Cap-Mismatch

LUT Mean & Zero

Crossing

Radix

Simple Volterra Filter

Time Skew Adjustment

Fig. 19. Block diagram of a time-interleaved ADC system using a slopefilter for timing correction and as a Volterra filter for buffer and track andhold calibration.

concentrated at low to moderate amplitudes, performance ismuch less sensitive to multiplicative errors such as quasi-lineardistortion, time skews and gain errors. Additionally the signalstatistics for embedded applications are known in advanceso that significant simplifications in calibration schemes canbe reliably used. Auto-correlation and zero-crossing timingmeasurements work well in these environments because therichness of the signal spectrum provides more than sufficientrandomness. As a rule-of-thumb multiplicative errors can eachbe relaxed by the back-off, or reduction in amplitude ascompared to a full-scale sine wave, by as much as two fullbits for cable applications. This has profound implications onarchitecture choices and circuit design.

ACKNOWLEDGMENT

The author would like to thank the team formerly at MobiusSemiconductor for all their original ideas, enthusiasm andhard work on multiple time-interleaved ADCs with variousarchitectures spanning a wide range of sample rates in manyprocessing nodes: primarily, Dr. Avi Madisetti, Dr. RalphDuncan, Dr. Jurgen van Engelen, Espen Olsen, Dr. Sasid-har Lingham, Jatan Shah, Howard Baumer, John Sin, Dr.Francesco Gatta Dr. Hairong Yu, Dr. Tommy Yu, RajeshRadhamohan and Ted Buchwald.

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