domino free 4-path time-interleaved second order sigma...

Analog Integrated Circuits and Signal Processing, 43, 225–235, 2005c© 2005 Springer Science + Business Media, Inc. Manufactured in The Netherlands.

Domino Free 4-Path Time-Interleaved Second Order Sigma-Delta Modulator

KYE-SHIN LEE,1 YUNYOUNG CHOI1 AND FRANCO MALOBERTI1,2

1Department of Electrical Engineering, University of Texas at Dallas, P.O. Box 830688, EC33, Richardson, TX 75083-0688, USA2Department of Electrical Engineering, University of Pavia, Via Ferrata 1, 27100 Pavia, Italy

E-mail: [email protected]

Received September 24, 2004; Revised November 1, 2004; Accepted December 15, 2004

Abstract. A domino free 4-path time-interleaved second order sigma-delta modulator is proposed. This time-interleaved scheme uses only one integrator channel along with incomplete integrator output terms to completelyeliminate the quantizer domino which is a key limit for the practical circuit implementation of conventional multi-pathtime-interleaved sigma-delta modulators. In addition, the single integrator channel leads to considerable hardwarereduction as well as path mismatch insensitivity, since only one global feedback path is required. As a result, theswitched capacitor implementation of the 4-path time-interleaved second order sigma-delta modulator is enabledwith the conventional 2-phase clocking scheme by using only 5 op-amps.

Key Words: quantizer domino, path mismatch, sigma-delta modulator, time-interleaved

1. Introduction

Sigma-delta (��) modulators are well suitable for lowbandwidth and high resolution applications such asvoice, audio, and instrumentation due to the oversam-pling and noise shaping property [1, 2]. However, therehave been considerable efforts to enlarge the bandwidthof the modulator whereas maintaining the high resolu-tion, in order to meet the emerging new telecom stan-dards [3–5]. Generally, to increase the signal bandwidthof the �� modulator, either high order or multi-bit ar-chitectures can be used. But, higher order modulatorssuffer from inherent stability problems [6, 7] and re-quire high order digital filters [1]. For multi-bit mod-ulators, dynamic element matching (DEM) techniquesare necessary to tackle the non-linearity of the feedbackDAC, which increases the complexity of the design[8–10].

An alternative approach is using parallel �� mod-ulators [11]. So far, several parallel �� schemes havebeen proposed which include multi-band �� (MB��), modulation based parallel �� (�-��), andtime-interleaved �� (TI ��). MB �� divides thesignal band into sub-bands which uses a different noisetransfer function to shape the noise of each sub-band.The output is reconstructed after attenuating the out-

of-band noise of each band using an FIR filter bank[12, 13]. �-�� decouples the input signal and thequantization noise of each channel by modulatingthe input, then demodulating the input and the quan-tization noise. Thus, the input can be bypassed tothe output while filtering the quantization noise [14].Among the parallel �� schemes, the TI �� is anattractive solution, since the effective sampling ratecan be increased without using fast analog circuits.However, the recursive operation of �� modula-tors, which is not present in Nyquest rate TI con-verters [15] complicates the direct conversion intotheir TI structures. The block digital filtering approach[16, 17] and the extended hardware reduction scheme[18, 19] conceptually works well, but some limita-tions discussed in Section 2 make the practical useunfeasible.

In this paper, we present a novel TI scheme for ��

modulators which is completely free of the quantizerdomino. Furthermore, the proposed method is appliedto a conventional second order��modulator, to obtainan equivalent 4-path TI structure. An overview of TI�� modulators is given in Section 2. Section 3 presentsthe proposed TI scheme and the 4-path TI second or-der �� modulator. The effect of major non-idealitiesare discussed in Section 4, and the circuit schematic is

226 Lee, Choi and Maloberti

x(n)

y(n)

M

M

M M

M

M

x1

z-1

z-1

z-1

z-1

z-1

z-1

x2

xM

y1

y2

yM

M-path

Σ∆ Μodulator

Fig. 1. M-path TI �� modulator.

shown in Section 5. Finally, the conclusions are givenin Section 6.

2. TI Σ∆ Modulator

In TI �� modulators, the input signal is sampled with ahigh frequency clock and then distributed within eachpath which operates at a lower clock rate. Figure 1shows the block diagram of an M-path TI �� modula-tor with the input decimation and the output multiplex-ing block. Here, the channel outputs which correspondto each time slot output of the conventional �� mod-ulator are simultaneously generated, and finally multi-plexed to obtain the same output sequence as the con-ventional counterpart. With this approach, the effectivesampling rate of the M-path TI �� modulator becomesM · fs assuming that each path is operating at fs . Thus,the bandwidth of the modulator can be increased by afactor of M whereas maintaining the same resolution.

The difficulty of converting a �� modulator intoits TI structure is due to the feedback loops which areresponsible for the recursive operation of the �� [1].Fortunately, by using the block digital filtering scheme[16, 17], first proposed in 1993, arbitrary �� topolo-gies can be transformed into equivalent TI structures[18]. However, the block digital filtering scheme suf-fers from quantizer domino and path mismatch effects.Quantizer domino is defined as: a certain quantizer out-put connected to another quantizer input via an ana-log block without passing through a delay. Figure 2shows the concept of the quantizer domino. Further-more, this situation is unavoidable in TI �� mod-ulators when M consecutive modulator outputs aresimultaneously generated by M quantizers. With thequantizer domino, switched capacitor (SC) implemen-tation of the TI �� modulator is impossible. Althoughthe quantizer domino can be avoided in the block dig-ital filtering TI modulators by redistributing the de-

Qk

Qk-1

AnalogCircuit

yk

yk-1

Fig. 2. Quantizer domino.

lays, this requires a complex clocking scheme and be-comes extremely difficult for TI modulator with morethan 2 paths [17]. Another drawback of this approachcomes from the multiple global feedbacks, since themismatches within the feedback path can increase thein-band noise level of the TI modulator.

3. Proposed TI Σ∆ Modulator

3.1. TI Scheme Overview

Figure 3(a) is the simplified model of a conventionalL-th order �� modulator with feedback and feed-forward branches where pi , for i = 1,. . . , L is theoutput of the i-th integrator, and ai and bi are constantcoefficients. Figure 3(b) shows the proposed M-pathTI �� modulator corresponding to Fig. 3(a) where theinput x , output y, and integrator output pL is redefinedsuch that it is assigned to the j-th path of the TI mod-ulator as

x j (n) = x [M(n−1) + j] for j = 1, . . . , M (1a)

y j (n) = y [M(n−1) + j] for j = 1, . . . , M (1b)

pL j (n) = pL [M(n−1)+ j] for j = 1, . . . , M (1c)

In the proposed TI scheme, instead of simulta-neously generating M complete integrator outputs,we generate only one complete integrator output pL1

and M-1 incomplete integrator outputs p∗L2, . . . , p∗

L Mwhich are equivalent to the complete integrator out-puts pL2,. . . , pL M without the modulator output terms.Now, pL1, and p∗

L2,. . . , p∗L M are applied to the input of

the quantizers which will generate a complete modu-lator output y1 and M-1 incomplete modulator outputsy∗

2 , . . . , y∗M . However, y∗

2 ,. . . , y∗M are linear combina-

tion of the complete modulator outputs, and since y1

Domino Free 4-Path Time-Interleaved Second Order Sigma-Delta Modulator 227

y(n)

x(n)

Linear Section

Qp1 p2

pL

-a1-a

2-aL

b1

b2 bL

-a3

b3

DAC

x(n)

y(n)

QM

Q2

Q1

M

M

M M

M

M

x1

z-1

z-1

z-1

z-1

z-1

z-1

x2

xM

pL1

p*L2

p*LM

IncompleteIntegrator

OutputGeneration

y1

y*2

y*M

CompleteOutput

Genearation

y1

y2

yM

d1

d2

dL

p11p21

pL1

DACL

DAC1

~

(a)

(b)

∫ ∫ ∫

∫ ∫∫

Fig. 3. L-th order �� modulator. (a) Conventional. (b) Proposed M-path TI.

is valid, the M-1 complete modulator outputs y2,. . . ,yM can be obtained by a simple digital processing ofy1 and y∗

2 ,. . . , y∗M . Furthermore, the proposed scheme

requires only one integrator channel which generatesthe outputs corresponding to the initial integrator out-puts of Figure 3(a). That is

pi1(n) = pi [M(n − 1) + 1] for i = 1, . . . , L (2)

where pL1 is the only complete L-th integrator outputwhich is generated in the proposed TI scheme that isused for the input of quantizer Q1. The remaining M-1incomplete L-th integrator outputs can be obtained bycombining (1a) and (2), since the incomplete integra-tor outputs do not contain the modulator output termsy1,. . . , yM .

In this way, the quantizer domino is completely elim-inated. Moreover, the single integrator channel whichrequires only one global feedback path can reduce thepath mismatch effects caused by mismatch within mul-tiple global feedbacks.

3.2. 4-Path TI Second Order Σ� Modulator

The transformation of the conventional second order�� modulator into its equivalent 4-path TI structureis described in the following procedure. Figure 4(a)shows the conventional second order �� modulatorand Figure 4(b) represents the corresponding 4-path TIcounterpart based on the proposed TI scheme.

Assuming p1(n) and p2(n) are the initial outputsof the 1st and 2nd integrator shown in Figure 4(a), weexpand it into 4-consecutive time slots which can beexpressed as

p1(n) = p1(n−4) + 0.54∑

i=1

[x(n−i) − y(n − i)] (3)

p2(n) = p2(n−4) + 24∑

i=1

[p1(n−i) − y(n − i)] (4)

where x is the input and y is the output of the modulator.Now, replacing p1(n − i) for i = 1, . . . , 3, in (4) withthe expanded terms which contain the p1(n −4) terms,and applying (1a), (1b), and (2), the integrator outputs


x(n) y(n)p1 p2

1 - z-10.5z-1

1 - z-12z-1

Q

DAC

4

1 - z-1z-1

1 - z-12z-1

4

x(n)y(n)

DigitalProcessing

3

2

2

3

3

2

32

34

2

0.5

1.5

p21

2p11

Q4

Q3

Q2

Q1

y4

y3

y2

y1

DAC2

DAC1

4

4

44

p*22

p*23

p*24

y*2

y*3

y*4

z-1

z-1

z-1

(a)

(b)

Fig. 4. Second order �� modulator. (a) Conventional. (b) 4-path TI structure.

of the 4-path TI modulator can be rewritten as

p11(n) = p11(n − 1) + 0.54∑

i=1

[xi (n − 1)

− yi (n − 1)] (5)

p21(n) = p21(n − 1) + 2[4p11(n − 1)

+ 0.54∑

i=2

(i − 1) · xi (n − 1)

− 0.54∑

i=1

(i + 1) · yi (n − 1)] (6)

where the quantization of p21(n) will lead to the com-plete modulator output y1(n). In addition, the future 2ndintegrator outputs of the conventional �� modulatorexpanded into r consecutive time slots are given by

p2(n + r ) = p2(n) + 2r∑

i=1

[p1(n + r − i)

− y(n + r − i)] for r = 1, 2, 3

(7)

In addition, (7) with the missing modulator outputterms are expressed as

p∗2(n + r ) = p2(n) + 2

r∑

i=1

[p1 (n + r − i) ]

for r = 1, 2, 3 (8)

Applying 1(c), the 3 incomplete 2nd integrator out-puts of the 4-path TI modulator obtained from the in-puts and the initial integrator outputs are given by

p∗22(n) = 2p11(n) + p21(n) (9a)

p∗23(n) = x1(n) + 4p11(n) + p21(n) (9b)

p∗24(n) = x2(n) + 2x1(n) + 6p11(n) + p21(n)

(9c)

Noticing that the above incomplete integrator out-puts are simply complete integrator outputs without themodulator output terms, (9a)–(9c) can be rewritten as

p∗22(n) = p22(n) + 2y1(n) (10a)

p∗23(n) = p23(n) + 2y2(n) + 3y1(n) (10b)

p∗24(n) = p24(n) + 2y3(n) + 3y2(n)+4y1(n)

(10c)


where p22(n), p23(n), and p24(n) are the completeintegrator outputs. Furthermore, the quantization of(10a)–(10c) leads to the incomplete modulator outputsy∗

k (n) = Qk[p∗2k(n)] for k = 2, 3, 4. In addition,

the complete modulator outputs can be obtained byrearranging the incomplete modulator output termswhich are

y2(n) = y∗2 (n) − 2y1(n) (11a)

y3(n) = y∗3 (n) − 2y2(n) − 3y1(n) (11b)

y4(n) = y∗4 (n) − 2y3(n) − 3y2(n) − 4y1(n)

(11c)

It is shown that the incomplete modulator outputsare simply linear combination of the complete outputs.Thus, the complete modulator outputs y2(n), y3(n), andy4(n) can be obtained by a suitable processing of y∗

2 (n),y∗

3 (n), and y∗4 (n) with y1(n) in the digital domain, since

the complete output y1(n) is always available. This dig-ital operation does not involve quantizer domino, sinceonly the final outputs of the quantizers are used. How-ever, the cascade operations cause latency problemswhich can limit the speed of the TI �� modulator.The solution for this problem can be using fast oper-ation blocks for the digital processing such as the fastadders proposed in [20–22].

Finally for the proposed 4-path TI modulator, (5)and (6) implements the integrator channel, the incom-plete integrator outputs are obtained by (10a)–(10c),and the digital processing block is based on (11a)–(11c). However, the feedback of the 2nd integrator isdivided into two parts, to reduce the resolution of thefeedback DACs. Furthermore, the input sampling blockis simplified by applying identical inputs to each path.This is similar to the zero insertion interpolation tech-nique used in [18]. The input sampling part shown inFig. 4(b) is realized by applying the below conditionfor (5)–(8) and (9a)–(9b).

x(n) = x4(n) = x3(n) = x2(n) = x1(n) (12)

The performance of the proposed TI �� modulatoris not degraded as far as the oversampling rate (OSR)is larger than the number of input channels, since inthis case the input sampler will still meet the Nyquistcriterion. In spite of the previously mentioned advan-tages, the proposed TI �� modulator requires largernumber of quantization levels for the quantizers whichgenerate the incomplete modulators outputs y∗

j (n) for

Table 1. Quantizer and DAC resolution.

Element Q1 Q2 Q3 Q4 DAC1 DAC2

Resolution 2 3 4 5 3.5 3(bits)

j = 2, 3, 4. This is obvious, since the dynamic rangeof y∗

j (n) is larger than y j (n) due to the missing out-put terms. Table 1 shows the required quantizer andDAC resolution of the proposed 4-path TI second or-der �� modulator corresponding to the conventionalsecond order �� modulator with a 2-bit quantizer. Ifthe feedback path of the 2nd integrator is not dividedinto 2 parts, the resolution of the 2nd integrator feed-back DAC becomes 4.5 bits.

4. The Effect of Non-Idealities

The non-ideality analysis of the TI �� modulator isimportant, since it shows different behavior comparedto the conventional �� modulator even with the samesource of error. We investigate how the major circuitnon-idealities affect the proposed TI �� modulatorthrough non-ideality analysis and behavioral level sim-ulations. Throughout the simulations, an equivalent 4-path TI structure of the conventional second order ��

modulator with a 2-bit quantizer was used. Here, thequantizer and DAC resolution of proposed 4-path TImodulator corresponds to Table 1.

4.1. Ideal Modulator Performance

The ideal performance of the proposed 4-path TI ��

modulator is compared with the conventional ��

modulator through behavioral level simulations. Non-idealities were not included for this case. Figure 5shows the output spectra of the conventional and 4-pathTI modulator with -6 dBFS, 305.18 kHz sinusoidal in-put where the resolution of Q1 is 2-bits. Each spectrumwas obtained by a 16384 point FFT. For both modula-tors, the sampling clock frequency was set to fs = 100MHz with signal bandwidth of 3.125 MHz. Thus, theeffective clock frequency of the 4-path TI modulatorbecomes 4 · fs . As expected, the SNDR improvementof the 4-path TI structure is approximately 30 dB, sincethe SNR improvement of the second order �� modu-lator is 15 dB by doubling the OSR [1]. Figure 6 showsthe SNDR vs. input amplitude, which validates the pre-vious result.


Fig. 5. Output spectra with same sampling clock rate.

Fig. 6. SNDR vs. input amplitude.

4.2. Non-Ideal Integrator

The non-ideal integrator which includes the phase er-ror and gain error is a major error source for ��

modulators. The finite DC gain of the op-amp whichis used in the SC integrator is responsible for thephase error whereas the gain error is due to thecapacitor mismatches and improper settling causedby the finite GBW and slew rate of the op-amp[23].

To find out the error terms owing to the phase errorand gain error, the transfer function of the proposed4-path TI modulator is derived by replacing each inte-grator with the non-ideal integrator which the z-domain

transfer function is expressed as [24]

H (z) ∼= c (1 + λ) z−1

1 − (1 + 1

Ao

)z−1

(13)

where c is the integrator gain, Ao is the DC gain ofthe op-amp, and λ is gain error of the integrator. Thetransfer function analysis shows that the error due tothe finite op-amp DC gain of the 1st integrator is notnoise shaped whereas the error of the 2nd integrator is1st order noise shaped in the proposed 4-path TI mod-ulator. Now, the equivalent error power due to the finiteDC gain of the op-amp is obtained from the additionalerror terms included in the transfer function. Assumingthat each quantizer of the TI modulator has identicalquantiztion step size, the error power due to the finiteop-amp DC gain Ao for the 1st and the 2nd integratorare given as

PAo,1st =(

2

A2o

)1

(OSReff)σ 2

+(

2

A2o

)π2

3 (OSReff)3σ 2 (14)

PAo,2nd =(

5

A2o

)π2

3 (OSReff)3σ 2 (15)

where OSReff is the effective oversampling rate of theTI �� modulator and σ 2 is the quantization errorpower of each quantizer. It is shown that the error powerof the 1st integrator include both a non-noise shapedterm and a 1st order noise shaped term, which the er-ror power will be dominated by the non-noise shapedterm. For the integrator gain error, the analysis resultsshowed the error of the 1st integrator is 1st order noiseshaped and the error of the 2nd integrator is 2nd or-der noise shaped. In addition, the error power owing tothe gain error λ of the 1st and 2nd integrator are givenby

Pλ,1st = (8λ2)π2

3 (OSReff)3σ 2 (16)

Pλ,2nd = (4λ2)π4

5 (OSReff)5σ 2 (17)

Figures 7 and 8 are behavioral simulation resultswhich each shows the SNDR degradation respect to


Table 2. The effect of integrator phase error and gain error.

Phase error Gain error

Modulator type 1st integrator 2nd integrator 1st integrator 2nd integrator

Conventional 1st order 1st order Only affects the Only affects the

second order �� noise shaped noise shaped modulator poles modulator poles

Proposed 4-path Not noise 1st order 1st order 2nd order

TI �� shaped noise shaped noise shaped noise shaped

Fig. 7. SNDR degradation vs. op-amp DC gain.

op-amp DC gain and integrator gain error, respectively.As shown in Fig. 7, the SNDR degradation due to the1st integrator op-amp gain is severe compared to thedegradation caused by the 2nd integrator op-amp gain.This can be explained by the non-noise shaped errorpower term in (14). The SNDR degradation respectto the integrator gain error is relatively less than thedegradation due to the DC gain of the op-amp.

For nowadays deep sub-µ CMOS processes us-ing metal-insulator-metal (M-i-M) capacitors, the ratiomismatch can be reduced to 0.1% by using well knownlayout techniques [3, 25]. Furthermore, the settling in-accuracy of the SC integrator can be controlled within0.1–0.2% even with 2-stage op-amps [26]. Therefore,the expected range of the integrator gain error can beat most 0.5% in practice. With a gain error of 0.5%, theSNDR degradation of the proposed TI �� modulatoris around 1.5 dB. Table 2 shows the effect of integratorphase error and gain error for the conventional secondorder �� modulator and the proposed 4-path TI ��

modulator.

Fig. 8. SNDR degradation vs. integrator gain error.

4.3. Path Mismatch

Path mismatch is an additional drawback of multi-pathTI �� modulators. Especially, the mismatch betweenthe feedback paths can be critical, since this can leadto non-noise shaped error terms at the output of the TI�� modulator. Thus, the single global feedback pathof the proposed TI �� modulator can be advantageousin this aspect. We go through a feedback mismatchanalysis for the proposed 4-path TI �� modulator toclear this point.

Figure 9 is the feedback path mismatch model forthe proposed TI �� modulator where α1 and α2 is

x(n) H1(z)

DAC2

H2(z)

α2

DAC1

α1

Fig. 9. Feedback path mismatch model of the proposed TI ��

modulator.


Fig. 10. Output spectra with 0.5% path mismatch.

the gain error of DAC1 and DAC2, respectively. Thetransfer function analysis shows that both errors are1st order noise shaped, which the error power due toα1 and α2 are given by

Pα1 = (8α2

1

) π2

3 (OSReff)3σ 2 (18)

Pα2 = (5α2

2

) π2

3 (OSReff)3σ 2 (19)

As a result, the effect of path mismatch can be minorfor the proposed TI �� modulator, since any mismatcherror between the feedbacks will all be 1st order noiseshaped. Figure 10 shows the output spectra of different4-path TI �� modulators with 0.5% path mismatchwhere the mismatch is applied between the feedbackpaths as the gain error of the DAC. TI-(I) and TI-(II) arebased on the block digital filtering scheme, which TI-(I) is with the k-factor technique [17] and TI-(II) is thehardware reduction approach [18]. The SNDR degra-dation of the proposed TI modulator is only 1.5 dB,which is relatively less than the other TI structures.However, for the block digital filtering structures, thepath mismatch effect can be reduced by using thek-factor technique, but this is not feasible in TI-(II).

4.4. Quantizer Error

The offset and input common mode variation of thecomparator, reference error, and quantizer mismatchesare major contributors for the quantizer error. However,

the effect of the quantizer error was minor for the pro-posed 4-path TI �� modulator, although 4 quantizersare used. This is because the additional error of eachquantizer is 2nd order noise shaped.

4.5. DAC Non-Linearity

In multi-bit �� modulators, error due to the non-linearity of feedback DAC appear as in-band whitenoise or harmonic tones that are not shaped by the loopfilter operation [9]. However, in most cases this prob-lem can be solved by DEM techniques.

The DAC non-linearity was included in the behav-ioral model of the proposed 4-path TI modulator by ap-plying a 0.5% random capacitor mismatch to the feed-

Fig. 11. The effect of DAC non-linearity. (a) Without DEM. (b)With DEM.


C4C

C

6C

4C

2C

2C

C

21

2 1

1

1

2

2

1

1

2

2

1

1

2

2

1

1

2

2

1

1

2

2

x

Digital

Blocky

Q1

Q2

Q3

Q4

3C 22

2

2

3C1

1

-x

1

5C

C

1

2 1

2C 22

2

2

C1

1

-x

1

3C

C

1

2 1

C

2

2

2

2 1

1

2CC

1

1

1

2

1

2

1

2

DAC2

DAC1

1

2

1

2

DummyCapacitors

1stIntegrator

2ndIntegrator

SummingCircuit

8

4

2

Fig. 12. SC configuration of the proposed 4-path TI second order �� modulator.

back DAC of the 1st integrator. In addition, the DWAalgorithm was applied at the feedback of the 1st inte-grator along with the mismatch error. DWA is a DEMtechnique which operates on a rotation basis [10]. Fig-ure 11 shows the effect of the DAC non-linearity. It isshown that harmonic tones are generated by the 1st inte-grator DAC non-linearity, but the tones are completelyremoved by using the DEM technique. The effect of the2nd integrator feedback DAC non-linearity was minorfor the proposed 4-path TI �� modulator.

5. Circuit Schematic

Figure 12 shows the SC configuration of the proposed4-path TI second order��modulator using 5 op-amps.The TI modulator is divided into 3 sub-blocks which arethe integrator channel, summing circuits, and the digitalprocessing block. The output of each integrator is validduring clock phase 2, thus the integrator outputs and themodulator input are summed during clock phase 2, todetermine the incomplete integrator outputs which areapplied to the input of quantizers Q2, Q3, and Q4. Next,the quantizer outputs are latched at the end of clock

phase 2, so the digital block and the DACs are able togenerate their outputs during the next clock phase 1. Asa result, the 4-path TI modulator can operate based onthe conventional 2-phase clocking scheme. In addition,the input of the quantizers Q2, Q3, and Q4 are attenu-ated by a factor of 0.5, 0.25, and 0.125, which is realizedwith the dummy capacitor used in each SC summingcircuit. This is to make the input range of the quantizersidentical. However, this input attenuation is compen-sated by the gain block at the output of each quantizer.

The area overhead of the proposed 4-path TI secondorder �� modulator can be the reduced analog compo-nents compared to the TI modulator proposed in [17],since a 4-path TI second order �� modulator based onthis scheme requires at least 8 op-amps with additionalcapacitors and sampling switches. However, the areaoccupied by the quantizers and digital blocks for theproposed TI modulator will be larger than Ref. [17].

6. Conclusions

In this paper, we have proposed a quantizer domino free4-path TI second order �� modulator. The 4-path TI


modulator is realized based on the proposed TI schemewhich eliminates the quantizer domino by using onlyone integrator channel along with incomplete integratoroutputs for the quantizer inputs. Non-ideality analysisresults show the proposed TI modulator is less sensitiveto path mismatch effects compared to other TI struc-tures. However, the most critical error source is thefinite op-amp DC gain of the 1st integrator. Finally, theSC implementation of the proposed 4-path TI secondorder �� modulator is enabled with the conventional2-phase clocking scheme by using only 5 op-amps.

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Kye-Shin Lee received the B.S. degree in electricalengineering from Korea University, Seoul, Korea, in1992 and the M.S. degree in electrical engineering fromTexas A&M University, College Station, in 2002. He iscurrently working toward the Ph.D. degree in electricalengineering at the University of Texas at Dallas.


He was with LG Semicon Co. (now Hynix Semi-con Inc.), Seoul, Korea from 1994 to 1999, where hewas involved in mixed signal circuit design and test-ing of BW/Color CCD chipsets including timing/sync.signal generator, camera signal processor, USB cam-era interface, and sigma-delta CODECs for audio andvoice band applications. His research has been focusedon switched-capacitor circuits, sigma-delta modula-tors, and pipeline ADCs.

Yunyoung Choi received the B.S. degree fromKwangwoon University, Seoul, Korea, in 1999 and theM.S. degree in electrical engineering from Texas A&MUniversity, College Station, in 2002. He is currentlyworking toward the Ph.D. degree in electrical engi-neering at the University of Texas at Dallas. He workedfor Texas Instruments, Dallas, from May to December2003 at the Wireless Business Unit. His research inter-est includes sigma-delta A/D and D/A converters foraudio systems and RF applications.

Franco Maloberti received the Laurea Degree inphysics (summa cum laude) from the University ofParma, Parma, Italy, in 1968 and the Dr. Honoris Causadegree in electronics from the Instituto Nacional de As-

trofisica, Optica y Electronica (Inaoe), Puebla, Mexico,in 1996.

In 1993, he was a Visiting Professor at ETH-PEL, Zurich, Switzerland. He was Professor of Mi-croelectronics and Head of the Micro Integrated Sys-tems Group, University of Pavia, Pavia, Italy, andthe TI/J.Kilby Analog Engineering Chair Professor atTexas A&M University, College Station. He is cur-rently with the University of Pavia and an adjunct Pro-fessor at the University of Texas at Dallas. His profes-sional expertise is in the design, analysis, and character-ization of integrated circuits and analog digital applica-tions, mainly in the area of switched-capacitor circuits,data converters, interfaces for telecommunication andsensor systems, and CAD for analog and mixed A/Ddesign. He has written more than 250 published papers,three books, and holds 15 patents.

Dr. Maloberti was a 1992 recipient of the XII Pedri-ali Prize for his technical and scientific contributionsto national industrial production. He was co-recipientof the 1996 Institution of Electrical Engineers (U.K.)Fleming Premium for the paper “CMOS triode tran-sistor transconductance for high-frequency continuoustime filters.” He has been responsible at both technicaland management levels for many research programs in-cluding ten ESPRIT projects and has served the Euro-pean Commission as ESPRIT Projects’ Evaluator andReviewer and as a European Union expert in manyInitiatives. He served the Academy of Finland on theassessment of electronic research in Academic institu-tions and on the research programs’ evaluator. He wasVice-President, Region 8, of the Editor of IEEE Cir-cuits and Systems (CAS) Society from 1995 to 1997and an Associate Editor of the IEEE TRANSCATIONS

ON CIRCUITS AND SYSTEMS II. He received the 1999IEEE CAS Society Meritorious Service Award, the2000 CAS Society Golden Jubilee Medal, and the IEEEMillennium Medal. He is the President of IEEE Sen-sors Council and a member of the Board of Governorsof the IEEE CAS Society. He is also the member of theItalian Electrotechnical and Electronic Society (AEI)and the Editorial Board of Analog Integrated Circuitsand Signal Processing.

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