an interleaved sampling adc...

11/19/19An Interleaved Sampling ADC Module

A. Mann, H. Angerer, I. Konorov, S. Paul

Technische Universität München, Physik Department E18

11.10.2005

An Interleaved Sampling ADC Module


OutlineOutline" The "old" SADC Module

" Wish List for the new SADC

" Interleaved SADC System Overview• System Control

• ADC Operation

• Calibration for Interleaving

" First Prototype Module

" Outlook


The "old" SADC ModuleThe "old" SADC Module" 6U VME module

" 32 channels, differential input with amplifiers

" 80 MHz sampling rate

" 10 bit ADC resolution" 1.5 V dynamic range" 1.5 mV/LSB sensitivity

" optical data interface" synchronous clock" HotLink data interface


Wish ListWish List• different module shapes to match to detector frontends

• component reduction (FPGAs, ADCs)

• easier data access for debug/development and small lab-setups

• less power consumption

• environment monitoring (temperature, voltages, currents)

• local firmware memory

• unique ID for every module

1change to serial multicannel ADCs

1interleaved operation for higher sampling rate (option)

1common PC interface (USB)

1display for debug output

1dedicated microcontroller for monitoring tasks


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New System OverviewNew System Overview

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FPGA

ADC sample clock

ADC serial data

ADC serial clock

RAM

synchronous clockdata downlink

USB

monitorµC

OLED display

D A

preamp baseline offset

DA

temperaturecurrent

voltages

Flashfirmware load

fiber interface


System ControlSystem Control

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FPGA

ADC sample clock

ADC serial data

ADC serial clock

RAM


USB

monitorµC

OLED display


D A

DA

temperaturecurrent

voltages

Flashfirmware load

fiber interface


System Control (2)System Control (2)• Cypress CY7C68013 USB 2.0 interface chip

• 8051 based controller

• KEIL C compiler demo version available (limited to 4K)

• USB-Firmware loaded via USB or from external EEPROM

1handles all USB data/control transfer via FIFOs

1controls FPGA-Firmware flash memory

1loads firmware(s) to FPGA

1flash holds also module ID (write protected)


System Control (3)System Control (3)• Atmel AVR ATmega128 as monitor controller

• C optimized RISC processor core

• free GNU C compiler available

• free AVRStudio from Atmel for simulation/debugging

• AVR-Firmware loaded via JTAG, SPI or self-programming

1temperature, voltage and current monitoring via SPI ADC (10bit)

1power control of frontend modules

1setting of preamplifier offset via SPI DAC (16bit)

1handling of OLED display and switches

1bus interface to FPGA firmware registers


System Control (4)System Control (4)• OSRAM Pictiva OLED display

• 128x64 full graphic display (no character set)

• 16 grayscales per pixel

• simple display memory write access

• easy readable (self-emitting)

1character generator implemented in AVR controller

18 lines x 21 ASCII characters (5x7)

1display temperatures, voltages, buffer fill levels, ...


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ADC OperationADC Operation

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FPGA

ADC sample clock

ADC serial data

ADC serial clock

RAM


USB

monitorµC

OLED display

D A


DA

temperaturecurrent

voltages

Flashfirmware load

fiber interface


ADC Operation (2)ADC Operation (2)• TI ADS5270 - pipelined 8 channel ADC

• 10 and 12 bit versions available, up to 75 MHz sampling rate

• 3.3 V analog and digital power supply

• 907 mW power consumption (12 bit @ 40 MHz)

• same clock for all 8 channels

• serial data output for each channel via LVDS lines (240 MHz DDR)

• slow SPI interface for ADC control


ADC Operation (3)ADC Operation (3)• Xilinx Virtex4 XC4VLX25 FPGA

• 24192 logic cells, 1296 Kb block RAM, 448 user IO pins

• SERDES included in IO cells

1ADC data interleaving

1noise suppression

1trigger detection, feature extraction (time, amplitude)

1data buffering (external 32 MB DDR RAM)

1handling of data/control messages (USB, fiber interface)


Interleaved ADC OperationInterleaved ADC Operation• price comparison

• 12 bit @ 40 MHz : ~ 45 $

• 12 bit @ 75 MHz : ~ 121 $

• Virtex4 allows precise phase adjustment of clocks via DCMs

1get 12 bit @ 80 MHz from two interleaved 40 MHz ADCs

time

amplitude

ADC 1

ADC 2


Interleaving ProblemsInterleaving Problems• different clock path delays for the two ADCs

• offset and gain differences

• component variations between the 8 channels of one ADC

1additional noise in interleaved data

1clock delays can be compensated by DCMs in the Virtex4

1offset correction is simple ADD/SUB operation on ADC data

1gain correction by ADD/SUB of amplitude dependent valuecalculated from gain mismatch

1inter-ADC mismatches may be corrected by additional digital filters


Clock Delay CorrectionClock Delay Correction

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1000-100-80-60-40-20 0 20 40 60 80100

0

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600

800

1000

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1400

FFT frequency

correction delay

FFT count

x

y

z

simulation withsine input signal

and added gaussian noise

sigma = 2

FFT calculation of interleaved ADC data:


Calibration ProcedureCalibration Procedure• determine offset error

1FFT of data with ADC input = 0 V

1minimize peak at fS/2

• determine gain error

1FFT of data with ADC input = max. value

1minimize peak at fS/2

1calculate gain correction slope

• adjust clock phase

1FFT of data with ADC input = fixed frequency fi

1minimize peak at fS/2 - f

i


Calibration ProcedureCalibration Procedure

0 200 400 600 800 100012001400160018002000

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-4

-2

0

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8

0 200 400 600 800 1000120014001600180020000

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400

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1000

0 200 400 600 800 100012001400160018002000

-200

-150

-100

-50

0

50

100

150

200

0200

400600

8001000

-10-8

-6-4

-20

24

68

100

10

20

30

40

50

60

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80

90

200400

600800

1000

-20-15

-10-5

05

1015

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100

150

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250

10051010

10151020

1025

-100-80

-60-40

-200

2040

6080

1000

5

10

15

20

25

30

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40

simulation withgaussian input noise

sigma = 2

offset = 3 gain mismatch = 0.01 delay mismatch = 0.4

FFT frequencycorrection

value

FFT count

x

y

z


First Prototype ModuleFirst Prototype Module

preamplifiers ADCRAMFPGA

USBFirmware Flash

HotLinkfiber interface

OLEDdisplay


OutlookOutlook

• test interleaved ADC operation

• automated system test and calibration procedures

• change outdated HotLink interface (gigabit SerDes)

This research is part of the EU Integrated Infrastructure Initiative Hadronphysics Project I3HP

under contract number RII3-CT-2004-506078

an interleaved sampling adc...

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