leakage reduction techniques
DESCRIPTION
Leakage reduction techniques. Mohammad Sharifkhani. Introduction. Leakage current is important in Standby mode: no T. activity Active mode: Static units: (e.g., SRAM cells) Active mode: Non-critical path logics It is the current that does not do anything for us The lower the better. - PowerPoint PPT PresentationTRANSCRIPT
Leakage reduction techniques
Mohammad Sharifkhani
Introduction
• Leakage current is important in– Standby mode: no T. activity– Active mode: Static units: (e.g., SRAM cells)– Active mode: Non-critical path logics
• It is the current that does not do anything for us
The lower the better
Power components (revisit)
• Speed
• Energy Battery lifetime
• Instantaneous power Package, cooling
The leakage power is a function of Vth, VDD and transistor size.
Power Down
• Complexity:– Cellular phone: checks
base-station every sec. in cell waiting mode partitioning the design
• Floating output nodes between 0.7V/0– High
leakage in subsequent stage pull-downer area, power
Power Down
• 100uSec settle time for power up. Windows-CE demands 1uSec
• On board level:– Turn off: All input signals to a chip 0;
otherwise short through ESD. Then turn off chip VDD
– Turn on: Reverse order. Except for the active low inputs which may disrupt the operation (e.g., CE, OE)
– Un-conventional power up/down methodology
Power Down
• High Vth Sleep T.– Multi-Threshold MTCMOS
• Both VDD and Virtual VDD Area
• Sizing Sleep T.:– Speed: virtual VDD bounce
Large enough– Discharge pattern virtual
VDD bounce Delay– VDD↓ Larger W/L; @
VDD=0.7 super cut-off T. SCCMOS
Power Down
• Example Input Pattern: 8x8 Multiplier speed penalty <5%– Second pattern W/L=60, First pattern W/L=170
• Right pattern is hard to find– In consistent with conventional CMOS design
Power Down
• High Vt Sleep T.– Does not operate at Vdd<0.7V
• Super cut-off transistor (SCCMOS)– Instead of high-Vt transistor, a regular
transistors is used for Sleep T.– The gate of the Sleep T. is connected to
Vdd+0.4V during cut-off– Operates at lower voltages (<0.7V)
Layout
Standard Cell implementation
Multiple Vt
• Multiple Vt is a common standard today
• It can be used in – Static CMOS– Domino
• It can be used as– In block level (Sleep T.)– Circuit level
Dual Vt for Domino
Preserving State
• Virtual supply collapse in sleep mode will cause the loss of state in registers
• Putting the registers at nominal VDD would preserve the state– These registers leak
• Can lower VDD in sleep– Some impact on robustness, noise and SEU
immunity
Low-leakage FF w. Sleep
High Vt
Stacking
Stacking
Stacking
3 Challenges
• High standby current in low Vth
• IDDQ testing failure
• Degradation of worst case speed due to Vth variation @ low Vth– Vth scaling to keep delay
constant: for 3V => 2V change 25% Vth reduction is needed
Vth controlling
• Solves all three problems together– Variable threshold CMOS (VTCMOS)– Can be used as a low-voltage (low active power)
method
• Two main blocks:– Leakage current monitor (LCM)– Self substrate bias (SSB)
• Two major schemes:– Self-adjusting threshold voltage (SAT)– Standby Power Reduction (SPR)
VTCMOS
• The body of the T. is the key controlling knob.– All properties of CMOS is carried over
(unlike Power Down) – Much smaller current flows through
Substrate. – Slow turn off, Fast turn on
• <0.1um Sec. good for Windows-CE
Self-Adjusting Threshold-Voltage Scheme (SATS)
SATS Experimental Results
VTCMOS
VTCMOS (LCM+SSB)
• Two sets of circuits:– Feedback control of SSB, LCM– Switch between Standby and Active
• LCM controls SSB when ILeak and IRef don’t match
• Controls the average Vth on the chip
VTCMOS (LCM+SSB)
• SSB is turned on and off intermittently and sets Vth– Real time and process independent
• LCM design criteria
• Large ILCM High power
• Too small ILCM slows LCM response speed; Vth unevenness and longer periods of Vth control hence error
VTCMOS (LCM+SSB)
• Typical values:– ILCM = 1uA, when ILeakage chip = 1mA,
XLCM =0.1%.– Given Vb=0.2V and S (the slope of
leakage current)= 0.1V/Dec W LCM T. = 0.001% of W leakage, chip
• Design of Vb– W1,2 @ subthreshold
VTCMOS (LCM+SSB)
• Hence:– XLCM set by transistor ration; independent of
VDD, Temp., process variation – Consider deriving Vb using a resistive V.
divider:• Dependency on all above
– @ corners X does not vary more than 15% sufficient tolerance to keep Vth in check
Substitution in the previous equation yields:
VTCMOS (SPR)
• There is an Standby Signal• Active: M1 on VBB:VSS• Standby: M1 off
– First: D1 off (N2 turns on M1)– SSB pumps out current (N2 v.
drops)… until M1 turns off– D1 only turn on (SSB connected
to VBB) when N2<-0.7V (M1 is OFF)
– When D1 is on; SSB pulls down VBBn
– M3?– M3 prevents M2 from over
voltage (drain of M2 < VSS+Vth)
VTCMOS (SPR)
• Going back to Active:– M2 turns on (St’by low)– LCM, SSB disabled– N2 charges up through M2, M3– M1 turns on
• Over voltage on M1 gate • Reliability
– D2-4 is to solve it • Clamp: VGS <1.8V (N2 v.
restricted)
– When VBB is VSS –Vth: NMOS cuts the clamp; M1 gate jump to VDD
VTCMOS (Performance/Penalty)
• Vth controllability– Sample: 40 chips
• Some with Vth=0.15• Some with Vth=0.05• Two gray distributions
– Each: 3 scenario• Vth conv.• Vth active mode• Vth standby mode
VTCMOS (Performance/Penalty)
• Standard deviation↓– +/- 0.1V +/-0.05V– Raise average Vth to
0.25 @Stby
• Temp. Dependency Reduction ↓– Mobility ↓ as T ↑ – 2mV/oC 0.7mV/oC
VTCMOS (Temp.)
• @ Sub 1V, Vth is small (speed)– Leakage current may dominate
– T↑ , I↑ T↑ , I↑ : Positive feedback– A leakage monitor is necessary
VTCMOS (Power/Area)• IVTCMOS = ISSB + ILCM
– ISSB independent of switching activity only a function of impact ionization (VDD and W chip) ISSB can be 1% of total power;
• Active: I pwell very small (<0.1% of total power)– ILCM must be large
enough (3uA) (VBB control)
• Energy consumption due to substrate V. variation– 5nF for 10mm2; 3V voltage variation
0.05uJoul– Suppose every 25mSec 2uW (Good only if
not very frequent)
• Area penalty– VTCMOS 1%– Separation of substrates 6% (substrate
contacts)
VTCMOS (Power/Area)
Substrate noise
• Variation of the VBB can influence the substrate noise– Noise affecting the SRAM stability– Noise affecting the jitter
• Same substrate for a DLL and an SRAM• SRAM shmoo plot no significant
differnce• DLL jitter almost the same
– In inverter chain only one inverter is operating
VTCMOS (within die Vth var.)
• In deep submicron, Vth is a VDrain than the body, especially for shorter devices
• Shorter devices small Vth, less affected by VTCMOS remain small Vth
• Longer devices higher Vth, affected more by VTCMOS– Vth variation increases
VTCMOS (within die Vth var.)• Measurement: true
leakage current for a given nominal Vth
• Note: the leakage controlled pretty well
• The variance of I leakage is not too much– Leakage is an
exponential function of Vth Vth variation reflected in leakage
– The std of leakage is not increased Vth variation is negligible
Inter-die variation
Inter-die variation with ABB
Experimental Results
Experimental Results
Design example I
• TX3900– 32bit RISC– Variable Supply (VS) DC-DC
converter– Vth control (SAT+SPR)– Placed at the corners
Design Example I
• Measurement– 1.3V @10MHz – 1.9V @40MHz– 20mW @ DC-DC converter
(85% efficiency)
• @ 20MHz– Conv. CMOS: 150 MIPS/W– VTCMOS: 480 MIPS/W
Design Example II
• SPR+SAT
• Distributed supply switches