Joining the Design and Mask Flows for Better and Cheaper Masks

Andrew B. Kahng (abk@cs.ucsd.edu)

Puneet Gupta (puneet@ucsd.edu)

Outline

• Introduction

• Design Aware OPC

• Placement for Better DOF

• Gate Length Biasing

• Tying CMP and OPC

• Design-Based Qualification of RET

Today’s Design-Manufacturing Interfaces

Litho/Process(Tech. Development)

Library(Library Team)

Layout & libs (Corner Case

Timing)

Design(ASIC Chip)

Mask: Dataprep(Mask House)

Design RulesDevice Models

Tapeout Layout

(collection of polygons ?)

RET

Guardbanding all the way in all stages!! (e.g. clock ACLV guardband ~ 30%)

What do we lose ?• Performance Too much worst-casing• Turnaround time Huge OPC runtimes, overdesign• Predictability RET is applied post-design• Mask costs Overcorrection• Designer’s intent lost RET is not driven by design

• Bidirectional design-manufacturing data pipe– Fundamental drivers: cost, value

• Pass functional intent to manufacturing flow– Example: RET for predictable timing slack, leakage, yield

– RETs should win $$$, reduce performance variation

cost-driven, parametric yield constrained RET

• Pass limits of manufacturing flow up to design– Example: avoid corrections that cannot be manufactured

or verified e.g., design should be aware of metrology

N.B.: 1998-2003 papers/tutorials: http://vlsicad.ucsd.edu/~abk/TALKS/

Foundation of the DFM Solution

Outline

• Introduction

• Design Aware OPC

• Placement for Better DOF

• Gate Length Biasing

• Tying CMP and OPC

• Design-Based Qualification of RET

OPC and Design Intent: Many Known Opportunities

• OPC applied post-tapeout – Overcorrection (matching corners) mask

cost– Large runtimes – Impact of OPC on performance unknown

• Designer’s intent: OPC quality metrics– CD (Poly over active)

• Non-critical poly need not be well-controlled

– Contact Coverage• “Perfect” corners unnecessary if there is enough contact overlap

– Line end shortening Poly should not “cut into” active

Today’s OPC and Design Intent

• Annotate features with “required amount” of OPC– E.g., why correct dummy fill?– Determined by design intent

• E.g., setup and hold timing slacks, parametric yield criticality of devices and features

• Goal: reduce total OPC inserted (e.g., SRAF usage) Decreased physical verification runtime, data volume Decreased mask cost resulting from fewer features

• Supported by formats (OASIS, IBM GL-I, OA/UDM)– Design-to-mask tools need to make and use annotations

“Design for Value” in the OPC Context

Given: Admissible levels of (OPC) correction for each layout feature, and corresponding delay impact (mean and variance)

Find: Level of correction for each layout feature, such that a prescribed selling point delay is attained

Objective: Minimize total cost of mask corrections

MEBES Volume vs. Gate CD Error

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0 5 10 15 20 25 30CD Tolerance (%)

No

rma

lize

d d

ata

vo

lum

e130nm

90nm

• Total post-fracturing MEBES data volume averaged over all cells in Artisan TSMC libraries (130nm, 90nm)

• Model-based OPC and fracturing by Calibre

Potential Mask Data Reduction

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% Mask Data Volume Reduction

No

. of

sta

nd

ard

ce

lls (

%)

130nm

90nm

• Difference in data volume between 4%, 24% CD error• 90nm flow and data volume include SRAF insertion

Performance-Driven OPC (130nm)

Notes: 1) Early experimental results based on subset

of available optimizations2) Same worst-case delay (corner-based STA)3) Preserves CD tolerance for critical gates4) Mask data savings shown result from gate

poly optimization only. Results will improve substantially with inclusion of field poly and metal layers.

5) Runtime savings shown do not include pattern-based OPC technology under development

New Tool Savingstestcase Run time Mask dataalu128 35% 24%c7552 28% 22%c6288 24% 18%c5315 6% 21%c432 28% 17%

Traditional OPC Flow Updated OPC FlowTestcase CD Distribution OPC Delay CD Distribution OPC Delay Normalized

All Gates (nm) Runtime (ns) All Gates (nm) Critical Gates (nm) Runtime (ns) MEBESmean (s) mean mean (s) Volume

alu128 126.1 1.48 51516 3.28 131.5 4.93 130.8 2.04 33535 3.28 0.76c7552 126.2 1.89 7149 1.59 132.0 4.77 130.1 1.99 5142 1.59 0.78c6288 126.0 1.37 12830 5.21 131.4 4.45 129.7 1.27 9710 5.21 0.82c5315 126.1 1.82 4539 1.94 131.7 4.70 129.7 1.89 4247 1.94 0.79c432 126.8 1.57 1020 1.33 131.3 3.90 129.9 1.67 737 1.33 0.83

Thanks: Dennis Sylvester and Jie Yang, Univ. of Michigan

The OPC Tug-of-War

OurTool

• Current OPC situation– Degree of correction is global compromise

between mask cost and yield loss– Many chip features are over corrected,

some are under corrected– Sub-optimal for both yield and cost

• A New Tool (i.e., our tool):– Customized correction target per cell

instance– Automatically computed based on timing

and yield analysis– Superior solution for both yield and cost

Increasing mask cost

Increasing yield loss

Degree of correction

# of

fe

atur

es

Degree of correction

# of

fe

atur

esCheaper masks Better yield

Design Aware OPC for Better Yield

• Obtain signed EPE tolerances and acceptable direction of variation from design power/performance constraints– E.g., a setup-constrained gate has a constrained +ve EPE

tolerance, a recommended –ve tolerance due to leakage with acceptable direction being gate CD getting smaller

• Obtain direction of CD variation of the features with defocus if not same as above, flag

• Design aware fragmentation– Finer fragmentation for smaller tolerance features

• Result: Tradeoff OPC effort in non-critical regions of layout with critical geometries

• Potential fallback: some loss in hierarchy• Another example: dual damascene vias have high

resistivity barrier on bottom coverage of “up” vias more important than “down” vias

Outline

• Introduction

• Design Aware OPC

• Placement for Better DOF

• Gate Length Biasing

• Tying CMP and OPC

• Design-Based Qualification of RET

Assist Features and Variation

• SRAFs are dummy geometries– Improve process window

overlap for dense and isolated features

– Not supposed to be printed– Unavoidable for 90nm poly

0.04

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0.12

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0.22

0.0 0.1 0.2 0.3 0.4 0.5 0.6

SB2 SB1 No SB

2 SB 1 SB W/O SBDOF

CD

SB = Scattering Bar SRAF

Thanks: Chul-Hong Park, UCSD

Layout Composability for SRAFs

• Feature spacings are restricted to a small set• Two components

– Assist-correct library layouts Inter-device spacing within a standard cells Intelligent library design

– Assist-correct placement space between cells needs to be adjusted Intelligent whitespace management

x+x x

Better than

Cell boundaryForbidden pitch Before AFCorr After AFCorr

Example

Forbidden Pitch Rules

-30

10

50

90

130

170

100 300 500 700 900 1100 1300 1500

pitch (nm)

CD

(n

m)

W/O opc(Best DOF)

W/O opc(Deocus)

Bias OPC(Defocus)

SRAF OPC (Defocus)

SB=1 SB=2 SB=3 SB=4

allowable

forbidden

#SRAF = 0

Pitch (X:um)

#SRAF = 1

#SRAF = 2

#SRAF = 3

#SRAF = 4

0<=X<0.51

0.51<=X<0.73

0.73<=X<0.95

0.95<=X<1.17

1.17<=X

Bias OPC

Forbidden pitches

SRAF OPC

[0.37, ∞]

[0.37, 0.509], [0.635, 0.729],[0.82, 0.949],[1.09, 1.16]

0

50000

100000

150000

200000

90 80 70 60 50

Utilization(%)

# T

ota

l SB

0

5000

10000

15000

20000

25000

30000

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40000

# S

B D

iffe

ren

ce

SB difference (130)

SB difference (90)

SB w/o AFCorr(130)

SB w AFCorr(130)

SB w/o AFCorr(90)

SB w AFCorr(90)

Experimental Results

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25

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90 80 70 60 50

Utilization(%)

Red

uct

ion

(%

)

EPE (130)F/Pitch (130)

EPE (90)F/Pitch (90)

• The number of total SRAFs increases due to AFCorr benefit even though the benefit decreases in the lower utilization.• At the same manner, number of EPE and forbidden pitch is reduced in 130nm and 90nm technology nodes.

Outline

• Introduction

• Design Aware OPC

• Placement for Better DOF

• Gate Length Biasing

• Tying CMP and OPC

• Design-Based Qualification of RET

Multi-Lgate Design for Leakage

• Lgate biasing from 130nm to 140nm

• Leakage benefit = 29%

• Delay overhead = 5% ; Dynamic power overhead = 3.5%

• Potential alternative/supplement to multi-Vt design

• Avoid high variability in low Vt and manufacturing overheads of multi-Vt

• CD variability (as a %) is less for larger Lgate design

Delay

0.00E+00

1.00E-11

2.00E-11

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8.00E-110

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Lgate

Leakage

0.00E+00

2.00E-08

4.00E-08

6.00E-08

8.00E-08

1.00E-07

1.20E-07

1.40E-07

1.60E-07

1.80E-07

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Lgate

Thanks: Puneet Sharma, UCSD

Gate-Length Biasing

• Reduces leakage variability• Can be implemented transparent to design in the MDP flow• Potential side benefit of a larger process window for biased gates for the same pitch

Leakage Variability

Gate-length

Lea

kag

e

Leakage Variability

Gate-length

Lea

kag

e

Biasing

Results: Leakage Reduction

00.10.20.30.40.50.60.70.80.9

1

No

rmal

ized

Lea

kag

e

c5315 c6288 c7552 alu128

SVT-SGL

SVT-DGL

DVT-SGL

DVT-DGL

With less than 2.5% delay penalty

• Design Compiler used for VT assignment and gate-length biasing• Better results expected with better sizers

Thanks: Puneet Sharma, UCSD

Results: Leakage Variability•Biasing “flatter” region of Lgate-leakage dependence•Leakage distribution for the testcase alu128 (500 samples)•Traces shown

•Unbiased circuit•Technology level biasing•Uniform biasing

0.00%

10.00%

20.00%

30.00%

40.00%

50.00%

60.00%

c5315 c6288 c7552 alu128

Percentage Reduction in Leakage Spread

Outline

• Introduction

• Design Aware OPC

• Placement for Better DOF

• Gate Length Biasing

• Tying CMP and OPC

• Design-Based Qualification of RET

CMP

Post-CMP ILD thicknessFeatures

Area fillfeatures

wafer carrier silicon wafer

polishing pad

polishing table

slurry feeder

slurry

Chemical-Mechanical Planarization (CMP)Polishing pad wear, slurry composition, pad elasticity make this a very difficult process step

Depth of focus budgets are the biggest determinants of planarization budgets and in turn hard to achieve (and detrimental to performance) density constraints

CMP Aware OPC• Compute local defocus from CMP simulation of

underlying layer– CMP simulation can be as simple as density based models

• Divide layout GDS into defocus regions and run model-based OPC on each region with different “best-focus” condition– In case of unavailability of defocus models, simple “right

direction” biasing may help • Advantages:

– Better depth of focus– Less stringent CMP requirements

• More relevant for Metal 1 and above• Possible design implications:

– Enforced regularity on metal layers (less stringent than “single pitch” though)

– Tighter density control on pre-identified timing critical regions

Outline

• Introduction

• Design Aware OPC

• Placement for Better DOF

• Gate Length Biasing

• Tying CMP and OPC

• Design-Based Qualification of RET

OPC Quality Verification• ORC does “shape” checks only

– E.g., shorting of redundant vias is not a fault– A post-RET LVS is needed to avoid false fails

• Power/performance qualification– Post-RET leakage/dynamic power/timing analyses

• Reliability qualification– Check for “necking”, small vias and other EM hotspots

• Catastrophic yield qualification– Critical area analysis on simulated wafer images

• Concept of “design process window”– Constant X% CD tolerance for PW computation is

overkill PW-critical features may not be timing critical– Compute PW over timing paths rather than individual

features

Conclusions• Several optimizations and simplifications of RET

flow possible with design input– We have not even talked about design-awareness in

mask inspection• MDP can help increase parametric yield

– Gate length biasing decreases leakage variability• Process window improvements by design input

– CMP-driven OPC– Timing aware “true” process windows

• RET quality of result– Simple “geometric” ORC not enough– Explicit awareness of designer metrics like power,

performance, yield and reliability is needed