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Valeriy Sukharev

An accurate compact modeling – A key component of the full-chip reliability assessment: EM and low-k TDDB

www.mentor.com© 2012 Mentor Graphics Corp. Company Confidential

EM is a growing reliability issue in modern ICs in the wake of smaller feature sizes

1 2

3 4 5 6

Current density

in M

A/c

m²

2014 2016 2018 2020 2022 2024Year

Minimum gate length in nm18 17 15 14 13 12 11 10 9 8 7

Currently used manufacturing solutions Manufacturable EM-robust solutions are known Manufacturable EM-robust solutions are NOT known Required current density for driving four inverter gates

Expected evolution of required and maximum IC wires (ITRS). While the required current density scales with frequency and reducing cross-section, the maximum tolerable current density is shrinking due to smaller structure sizes

• Excessive current density within interconnects – which if not effectively mitigated causes electromigration(EM) and electrical overstress – is a major concern for integrated circuit (IC) designers.

• The latest edition of the ITRS roadmap predicts that all minimum-sized interconnects will be EM-affected by 2018, potentially restricting any further downscaling of wire sizes.

• Current density verification and thus the detection of electromigrationissues are already an integral part of the sign-off verification of circuit layouts. Current density violations detected during sign-off are corrected by layout modifications – by the widening of wires, for example.

Jens Lienig, ISPD’13, p. 33-40, 2013.

IRSP 2016, Dresden


EM in advanced nodes

Year 2014 2016 2018 2020 2022 2024 2026

Gate length (nm) 18.41 15.34 12.78 10.65 8.88 7.40 6.16

On-chip local clock frequency (GHz)

4.211 4.555 4.927 5.329 5.764 6.234 6.743

DC equivalent maximum current (µA)*

18.14 12.96 10.33 7.36 5.53 4.45 3.52

Metal 1 properties Width – half- pitch (nm)

23.84 18.92 15.02 11.92 9.46 7.51 5.96

Aspect ratio 1.9 2.0 2.0 2.0 2.1 2.1 2.2

Layer thickness (nm)*

45.29 37.84 30.03 23.84 19.87 15.77 13.11

Cross-sectional area (nm²)*

1,079.7 716.0 451.0 284.1 187.9 118.4 78.13

DC equivalent current densities (MA/cm²) Maximum tolerable current density (w/o EM degradation)**

4.8 3.0 1.8 1.1 0.7 0.4 0.3

Maximum current density (solutions unknown)**

25.4 15.4 9.3 5.6 3.4 2.1 1.2

Required current density for driving four inverter gates

1.68 1.81 2.29 2.59 2.94 3.76 4.50

Predicted technology parameters based on the ITRS, 2011 edition; maximum currents and current densities for copper at 105°°°°C.

25 10,0

20IEM

15

1,0

Jmax

10 Imax

5JEM

0

20142018 2022

Year

2026

0,1

20142018 2022

Year

2026

Expected development of currents (Imax, left) and current densities (Jmax, right) needed for driving four inverter gates, according to ITRS 2011. EM degradation needs to be considered when crossing the yellow barrier of currents (IEM) and current densities (JEM). As of now, manufacturable solutions are not known in the red area.

• The global trend in size reduction leads to improved circuit performance, efficiency at higher circuit frequencies and smaller footprints.

• Line widths will continue to decrease over time, as will wire cross-sectional areas. As shown in Table, the cross-sectional area shrinks from about 1,000 nm² in 2014 to less than 500 nm² in 2018.

• Currents are also reduced due to lower supply voltages and shrinking gate capacitances.

• However, as current reduction is constrained by increasing frequencies, the more marked decrease in cross-sectional areas (compared to current reduction) will give rise to increased current densities in ICs going forward.

Jens Lienig, ISPD’13, p. 33-40, 2013.

IRSP 2016, Dresden


Current Methodology

• Foundries generate the EM Reliability Rules, which provides metal Imax dependence on metal length & width, and temperature. For example for T = 110oC:

Metal Wiring Level Metal Length, L (um) Metal Width, W (um) Imax (mA)

M1, Mx, Mxa, Mxc

L <= X Any width 3 x Z x (w – Y)

L > X W >= Y 2 x Z x (w – Y)

L > X W < Y Z x (w – Y)

• Digital layout tools verify interconnect regarding the current densities in each segment vs EM rules. Verification tools for current densities, such as Cadence Virtuoso Power Systems, Synopsys CustomSim, Mentor Calibre PERC, and Apache Totem MMX, have been available for some time.

- They extract a netlist from the layout (including parasitics). - This netlist is then used to simulate the currents in all wires. - If any of the resulting current densities exceed an EM-relevant boundary, a violation is

detected, highlighted, and repaired in most advanced cases.

But … Based on ITRS, All minimum-sized interconnects will be EM-affected for nodes below 10nm!!!

IRSP 2016, Dresden


PROBLEM … H-M-M … NOT SURE

What Do We Do About It?

All minimum-sized interconnects will be EM-affected bellow 10 nm mode

Goal : Manage the EM Effect on Chip Performance

Option 1a : Do Nothing — Hope for the best

Option 1b : Reactive Strategy = Wait till it Happens— Manage it with foundry required EM design

rules

Option 2 : Proactive Strategy = Design around it — Manage it Through IC Design: Design a chip that

does not care about EM effects

IRSP 2016, Dresden


EM problem is severely exuberated!

• EM problem is severely exuberated! Why?

• Because, the limiting JEM was, is, and will be predicted wrong until

the correct underneath physics will be accounted!!!

WHAT IS WRONG WITH CURRENT METHODOLOGY?1. Existing EM checking tools and flows make use of the empirical

Black’s model, developed in the 1960s. However, when Black’s model is used to check EM in power grids, we run into many problems, because that model was originally derived for individual lines and not for large interconnected wire meshes such as modern power grids.

2. To use Black’s model, one has to subdivide a power grid into straight line segments and then assess the susceptibility of every line, separately and independently.

Flaw: Segments are not independent. Reliability

predictions computed using Black’s model can be wildly inaccurate. If the metal layer happens to be (artificially) segmented into short metal lines, the grid can appear immortal due to the Blech effect, which becomes dangerously optimistic.

IRSP 2016, Dresden


EM problem is severely exuberated!

3. Adopted a weakest segment approximation: a power grid fails as soon as any one of the lines fails.

Flaw: This series model of grid failure ignores the inherent redundancy in the many parallel paths of the power grid. When mesh structure of the power grid is used the grid lifetime is 4X longer then provided by the series model. Adding a pessimism generated by ignoring a material flow between segments results almost 6X over-estimation of the TTF. It means that chips that are supposed to live for 10 years in the field are being unnecessarily over-designed today to survive for 30-60 years.

8

1000 800 600 400

200

100 80 60 40

20

10 8 6 4

2

0.1

0.6 0.4

Experiments on a 2-Segment 3-Terminal Test Structure

1 2 5 10 20 30 40 50 60 70 80 90 95 98 99

Cumulative Failure (%)

Most failures occur in the right limb (i-iii), even though the current density is much higher in the left limb.

Tim

e T

o F

ailu

re (

hrs

)

Electromigration (EM) is a degradation mechanism

in which metal atoms move in the opposite direction to the electric current, under the influence of the electron wind. Eventually, the stress buildup due to this movement is such that a void forms in the metal line, disrupting the flow of current and causing a failure.

C. Gan, C. Thompson, et. Al, J. Appl. Phys. 94, 1222 (2003).IRSP 2016, Dresden


EM related pessimism isn’t a good strategy

• One might think that pessimism is not a bad strategy in VLSI. However, too much pessimism in the power grid can be a big problem. It leads to overuse of metal area, leaving little room for signal routing, which makes EM signoff extremely difficult in modern designs, thus increasing design complexity and design time.

• Foundry generated EM rules promise 10 years lifetime for each wire obeying the rules (we know it isn’t very true). Does it mean that the whole design will survive 10 years, or may be more? How much more exactly?

• If a project with the foundry recommended EM design rules (schedule, cost, size, etc.) in jeopardy, it will be good to know how far the current budgeting is from the cliff.

• A trusted info about how far can be crucial.

Current assessment methodology cannot provide this info.

Physics-based EM assessment provides location of the “cliff” for each design.

Excess margin

EM design rules(JEM, T, geometries, …)

Performance, power, size, schedule, cost …

Cliff = EM failure

???

IRSP 2016, Dresden


On-chip interconnect

Interconnect functionality • interconnectivity for signal propagation (signal lines)

- bidirectional pulsed currents

• voltage delivery (power/ground lines)

- unidirectional current

(a) (b) (c)

(a) The layout and output pin position options for INV X4. Charge/discharge currents when the output pin is at:(b) node 4 and (c) node 3.The red [blue] lines represent rise [fall] currents.

Standard cells are the current sources in the p/g mesh.

Power (voltage) sources

P/G meshG. Posser ; V. Mishra ; P. Jain ; R. Reis, S. Sapatnekar; ICCAD 2014, pp. 486-491

IRSP 2016, Dresden


Criterion for the full-chip EM failure

• Signal lines are immune to EM failure due to their short lengths (less 1um) and bidirectional currents.

• P/G nets are subjects to fault due to unidirectional currents and long lengths (may be longer 100 um).

• Major function of the p/g grid is delivering voltage (Vdd and Vss) to every gate. • EM induced degradation can affect this functionality.• The inherent redundancy in the many parallel paths of the power grid prevents

a catastrophic failure.• Voiding induced increase in the resistance of p/g segments is responsible for

IR-drop increase, which can result a parametric failure.

P/G grid is deemed to have failed, not when the first line fails, but when the voltage drop at any grid node exceeds a user specification.IRSP 2016, Dresden


Voltage evolution

IRSP 2016, Dresden

- Nucleated void - Growing void

- Saturated void

• We want to simulate voiding evolution in all trees• To convert it to the branch resistor evolution• To solve a linear system for a power grid network with n nodes,

G(t) × v(t) = I(t), where G(t) is a n×n time-varying conductance matrix; I(t) is transient current source vector; v(t) is the corresponding vector of nodal voltages.


P/G grid EM assessment

P/G located in each metal layer should be subdivided on “interconnect trees” – elemental units of EM reliability (Carl Thompson).

An interconnect tree is a continuously connected structure of straight metal lines within one layer of metallization such that atomic flux can flow freely within it.

Current densities and current directions should be assessed for each branch in each tree.

These currents are generated by both the voltage and current sources. Thus, the current assessment in all cells is needed.

Stress evolution in each tree should be resolved. Voiding (nucleation and growth) should be resolved. Physics based Compact Models are needed!

M2 VDD

Contac

t

M1 VDD

Via1

….

Current sources

Current sources

IRSP 2016, Dresden


Current assessment

τ

T

j+

0

t+

3TmT

. . . . .

.Time, t

• Each current source generates time-dependent unidirectional pulse current.

• Conventional approach transfers it to effective DC as:

which isn’t physically correct.• Physically correct should be

defined as a DC current, which generates the critical stress at the same time as a given time-dependent current .

• Solutions of the Korhonen’s equations for the identical lines loaded with and provide:

• Condition: results:

( ) ττ djT

j

T

eff

DC ∫=0

1

eff

DCj

( )τj

eff

DCj

( )τj

( ) ( ) ( )

( )( )

τπ

κρ

σστ

πκ

πκ

detjeL

xnCos

L

eZtx

t

L

n

n

tl

n

TTD ∫∑+∞

=

+−+

Ω+=

0

12

0

122

22

2

22

124,

( )

( )

( )

( )

+

+

+−Ω

−=+

−∞

=

∑t

L

n

n

eff

DCTDC e

n

l

xn

L

xLjeZtx

2

2212

022

12

12cos

42

1,

πκ

π

π

ρσσ

( ) ( ) critnucTDnucDC tt σσσ == ,0,0

critσ

( ) ττπ τ

π

dejLTk

BDj

LTk

BDt

mB

aeff

DCmB

anuc2

2

0

2

2Ω

−

∫Ω

=

V. Sukharev, et al. J. Appl. Phys. 118, 034504 (2015)

Different current sources have different effective lengths L and periods T extracted from user specified activity factors.

M2 VDD

Contac

t

M1 VDD

Via1

Current sources

Current sources

L

L

IRSP 2016, Dresden


General Physical Model

dxxx +

W

H x

y

z

ejJa(x)

Ja(x+dx)

If atom an flux divergences somewhere inside metal line then accumulation or depletion of atoms is happening there:

0=∇+∂

∂A

A Jt

N rr

Fast diffusion

Slow diffusion Slow diffusion

∂

∂+

Ω∂

∂=

∂

∂

x

jeZ

xt

HydHyd σρκ

σ

Evolution of the hydrostatic stress (a) along the metal line loaded with DC current, and at the cathode end of line, (b) j = 5x109A/m2, T = 400K.

critσ

critσ

nuct

IRSP 2016, Dresden

V. Sukharev, “Beyond black’s equation: Full-chip Em/Sm assessment in 3D IC stack,” Microelectronic Engineering, vol. 120, pp. 99–105, May 2014.


Stress evolution in interconnect tree

Current density Hydrostatic stress

IRSP 2016, Dresden

P. Gibson, M. Hogan, and V. Sukharev, “Electromigration analysisof full-chip integrated circuits with hydrostatic stress,” in 2014 IEEEInternational Reliability Physics Symposium, 2, pp. 2.1–2.7, 2014.

A typical interconnect tree structure A simple 3-terminal tree

Continuity equation for limbs:

Boundary conditions for all junctions:

HB Chen, et al., Analytical Modeling and Characterization of Electromigration Effects for Multi-Branch Interconnect Trees, IEEE TCAD, 2016.


Closed-form analytical solution for stress evolution in the multi-branched interconnect tree

T-shaped interconnect tree.

Evolution of the stress distribution along the segment of the shown T-shaped tree; (a) line 1, (b) line 2, and (c) line 3.

(a) (b) (c)

If we disassemble these brunches a standard stress evolution will take place in each of them:

IRSP 2016, Dresden

HB Chen, et al., Analytical Modeling and Characterization of Electromigration Effects for Multi-Branch Interconnect Trees, IEEE TCAD, 2016.

• Employment of the proper BC at the segment junctions, representing the continuity of stress and atomic fluxes, secures an accurate calculation of stress evolution inside multi-segment tree.


Critical stress & Void nucleation time

IRSP 2016, Dresden

• The model of the homogeneous nucleation suggests that any void-like flaw in a metal subject to hydrostatic tension will enlarge if the stress exceeds the value

• Here, is the surface energy per unit area, and is the flaw size. For and σ = 200MPa we can estimate .

• Solution to the Korhonen’s equation with blocking BC:

• Keeping the slowest decaying term, we can get an approximation for the void nucleation time at the cathode end of line (x=0):

f

critr

γσ

2=

γ fr 21 mJ=γ

nmrf 10=

−Ω

+

Ω

Ω≈

critTa

B

nucjLeZ

jLeZ

BD

TkLt

σρ

σ

ρ

2

2ln

2

( )

( )

( )( )

+−

+

+

−+−= ∑∞

=

tL

n

n

L

xn

GLGL

Gxtxn

T

2

022

12exp

12

12cos

42

,π

κπ

π

σσ

critσ


Void nucleation time

IRSP 2016, Dresden

0

100

200

300

400

500

600

700

0 5E+10 1E+11

Nucleation tim

e, s

j, A/m2

n=1.243

Void nucleation time as a function of the test current density and temperature

j/Ttest, K

323

373 423 473 523 573 623

1.00E+09 T-void 4.58E+05 IMMORT IMMORT IMMORT IMMORT IMMORT

2.00E+09 T-void 2.25E+05 1.79E+05 IMMORT IMMORT IMMORT IMMORT

3.00E+09 T-void 1.49E+05 9.86E+04 1.88E+04 IMMORT IMMORT IMMORT

4.00E+09 T-void 1.11E+05 6.85E+04 1.06E+04 2.79E+03 IMMORT IMMORT

5.00E+09 T-void 8.89E+04 5.26E+04 7.51E+03 1.54E+03 6.03E+02 IMMORT

6.00E+09 T-void 7.40E+04 4.27E+04 5.86E+03 1.10E+03 3.04E+02 2.19E+02

7.00E+09 T-void 6.34E+04 3.60E+04 4.81E+03 8.69E+02 2.19E+02 7.80E+01

8.00E+09 T-void 5.54E+04 3.11E+04 4.09E+03 7.19E+02 1.73E+02 5.60E+01

9.00E+09 T-void 4.22E+04 2.74E+04 3.55E+03 6.14E+02 1.44E+02 4.40E+01

1.00E+10 T-void 4.43E+04 2.44E+04 3.14E+03 5.37E+02 1.24E+02 3.70E+01

1.10E+10 T-void 4.03E+04 2.21E+04 2.82E+03 4.77E+02 1.08E+02 3.20E+01

1.20E+10 T-void 3.69E+04 2.01E+04 2.55E+03 4.29E+02 9.70E+01 2.80E+01

3.00E+10 T-void 1.47E+04 7.79E+03 9.54E+02 1.54E+02 3.30E+01 9.00E+00

5.00E+10 T-void 8.84E+03 4.63E+03 5.62E+02 9.00E+01 1.90E+01 5.00E+00

7.00E+10 T-void 6.31E+03 3.30E+03 3.99E+02 6.30E+01 1.30E+01 4.00E+00

9.00E+10 T-void 4.91E+03 2.56E+03 3.09E+02 4.90E+01 1.00E+01 3.00E+00

Extracted current density exponent for Ttes=573 K, TZS=723 K, and σcrit=600 MPa.

−Ω

+

Ω

Ω≈

critTa

B

nucjLeZ

jLeZ

BD

TkLt

σρ

σ

ρ

2

2ln

2

Extracted dependency of n on Ttest for TZS=723 K, σcrit=600 MPa vs. experimental data:

Exp. 1: M. Hauschildt, et Al, IEEE Int. Reliab. Phys. Symp.Proc. (2013) 2C.1.1-6.Exp. 2: M. Hauschildt, et Al, AIP Conf. Proc. 1601, 89-98 (2014).

( )jBeZD

LTkt

a

TcritB

nucρ

σσ −=

2


Void precursor statistics

IRSP 2016, Dresden

• Thus, the voiding is a superposition of two events:

1. Defects (void precursors) of different sizes are distributed along a line. Each defect is characterized by a specific critical stress determined by its size ( ), which is needed to initiate its growth.

2. EM generates a time dependent distribution of the stress along the line.3. When the stress somewhere in the line reaches one of the needed , the growth of the

corresponding i-th defect is initiated.

• Hence, a process dependent character and distribution of defects – void precursors, (interfacial micro delamination, micro caverns, barrier pinholes, etc.) in combination with the grain distribution are major causes of the statistical nature of EM.

i

i

crit rγσ 2≈ir

i

critσ


Post-voiding evolution of line resistance

IRSP 2016, Dresden

• A missing part of the global picture describing the kinetics of voltage drop degradation in P/G grid is the kinetics of the post-voiding evolution of the resistances of individual lines.

• Knowledge of the analytical formulation of this kinetics (extended to the interconnect trees) will allow to perform fast analysis of the power grid based on solution of the linear system: . Here, is the time-dependent conductance matrix, is the transient current source vector, and is the corresponding vector of nodal voltages.

• Hence, a void size evolution is the next question that should be addressed.• A role of stress gradient in void size evolution.

( ) ( ) ( )tIttG =Φ× ( )tG( )tΦ

( )tI

H

W

L

Void

Hhlin

W

( ) ( ) ( )

( ) ( )( )

( )( )HWWHh

tV

HWWHhtLtR

HW

tLR

hW

tLR

hH

tLR

RRRR

RRR

TavoidCuTavoid

voidTa

Void

Cuvoid

Ta

bottomvoid

Tavoid

Ta

wallvoid

Ta

bottomvoid

Ta

wallvoid

Ta

wallvoid

Ta

Void

Ta

Void

Cu

Void

Ta

22

;;

1111

__

___

+≈

−

+=∆

===

++=

−=∆

ρρρ

ρρρ


Void evolution

IRSP 2016, Dresden

• There are two different venues for EM induced void development:(i) Void evolves from the microscopic (~10 nm) precursor.

(ii) A current induced growth of a preexisted volume saturated void.

• Different kinetics of postvoiding stress evolution are derived due to different initial stress distribution: critical stress near precursor (i) and zero stress everywhere (ii)

Evolution of the distribution of the hydrostatic stress along the metal line loaded with the DC current of 1x1010A/m2 at T=400 K

Initially void-less metal line. V. Sukharev, A. Kteyan, X. Huang,IEEE TDMR 16, 50 (2016).

A line with the preexisted saturated void at the cathode end. J. He, Z. Suo, et. Al, Appl. Phys. Lett. 85, 4639 (2004).


Void volume evolution

IRSP 2016, Dresden

• Different void volume evolution kinetics exist in these cases:

Initially void-less metal line. A line with the preexisted saturated void.

• First, the void volume increases much faster in the case of initially void-less line.

• Second, at initial times (up to 104 s for the chosen parameter values) the void growth, in this case, doesn’t depend on the current density. It contradicts to the case of a line with the preexisted void where the void growth at initial times is linearly proportional to the current density.

( )L

tD

TkV

tV a

B

crit

line

void Ω=

σ


Blech Strip Test Structure of EM

IRSP 2016, Dresden

• Hydrostatic stress distribution in the Blech structure.

Current density flux Total atomic flux

• Atom flux is initiated at the strip edge where j is almost zero.

Voiding caused by current, temperature and concentration gradients

Voiding caused by current, temperature and concentration gradients + stress gradient


Edge drift ~ Voiding

IRSP 2016, Dresden

• Current crowding induced atomic depletion generates field of stress gradients directed toward the crowding location.

• Atoms migrate along these gradients and being picked by EM force migrate toward anode.

• Tension is gradually developed at the strip edge results the surface atom dissolution in the metal (~void nucleation) when critical stress is developed.

• Similar voiding mechanism works in the case of void nucleation at the cathode end of line above the upstream via.


Double-Damascene structure

IRSP 2016, Dresden

Model Experiment

V Sukharev, E Zschech - Journal of applied physics, 96, 6337-6343 (2004)


Voltage evolution

IRSP 2016, Dresden


- Saturated void

• We want to simulate voiding evolution in all trees• To convert it to the branch resistor evolution• To solve a linear system for a power grid network with n nodes,

G(t) × v(t) = I(t), where G(t) is a n×n time-varying conductance matrix; I(t) is transient current source vector; v(t) is the corresponding vector of nodal voltages.


• Assume (just for a moment) that the void less steady state was achieved in the tree.

• Consider the redistribution of the atoms between sub-segments due to unblocked sub-segment ends:

σ i

cathod − σ j

anode = ∆σ ij =eZρ jij Lij( )

ΩFor the steady state:

( )∑

=

−

=

Ω+

+−

7

1

023i

ij

ijijkT

E

iTi L

LjeZe

RBZS

V ρ

δσσ

If , this sub-segment is suspiciousto EM failure.

Example of an interconnect tree

jmn is the density of electron flow (opposite to the current direction).

criti σσ ≥

Distribution of the steady state hydrostatic stressalong the considered tree

• Previously, we use uniform temperature distribution:The shortest void nucleation time is characterized by the biggest steady state stress ,

j23

j34

j54

j46

j68

j76

j13

1

3

2

5

4

7

6

8

• With temperature variation: Void nucleation time is affected by both T and hydrostatic stress. Consider both factors to find the first nucleated void (mintnuc

i)

σ m j1, j2,..., jn( )

Steady state distribution of the hydrostatic stress inside interconnect tree in void-less regime

IRSP 2016, Dresden

X. Huang, T. Yu, V. Sukharev, and S. X.-D. Tan, “Physics-basedelectromigration assessment for power grid networks,” in DesignAutomation Conference (DAC), 2014, 51th ACM/EDAC/IEEE, 2014.

−

−

Ω≈

Ω−

+

critm

resmkT

f

kT

EE

m

nuc

critDV

eB

kTe

D

Lt

σσ

σσσ

ln2 0

2

max


Physics-based criterion for EM failure

• As an alternative to the current EM assessment methodology we have recently developed the EM mesh model to account for the redundancy, and its key feature is that a grid is deemed to have failed, not when the first line fails, but when the voltage drop at any grid node exceeds a user specification.

• It provides an accurate estimation of the time-to-failure for any design.• Chip fails when the maximum IR drop exceeds the threshold level.

Initial IR drop distribution Final IR drop distribution (at lifetime)

12 14 16 18 20 22 24 26 281.62

1.625

1.63

1.635

1.64

1.645

1.65

1.655

Simulation Time (yrs)

No

de

Vo

lta

ge

(V

)

Reaches minimum nucleationtime, begin to degradate

Reaches thresholdvoltage, TTF

Voltage at the first failed node over time.

IRSP 2016, Dresden



- Saturated void

EM-induced voiding results IR-drop growth

IBM power grid benchmarks

Steady state hydrostatic stress distribution predicted by the initial current densities,(a), and initial voltage drop (V),(b), in the layer that directly connects to circuits (M3) of IBMPG2.

Void distribution,(a), and the voltage drop (V) distribution in the layer that directly connects to circuits (M3),(b), of IBMPG2 at t=TTF. Void volume saturation is taken into account.

Voltage drop of the first failed node and maximum voltage drop in IBMPGNEW1 change over time.

Effect of temperature on TTF

IRSP 2016, Dresden


IR-drop based Chip-scale EM analysis

thermal simulation

EM simulation

Input

Extract

• power gird parasitic R netlist

• DC I sources, V sources

------------------------------

• Temperature distribution

• Technology parameters

• Time step Δt

Find mintnuc

1. Divide p/g net into interconnect trees

2. Obtain initial current density

3. Tree-based stress analysis: steady

state hydrostatic stress

4. Immortality check; find the minimum

void nucleation time

5. tstart = mintnuci

6. Start the analysis from time t = tstart;

branch with nucleation time tstart

enters the growth phase

Loop

6. Move to next instant in time t := t + Δt ;

update resistance of branches in the

growth phase

7. Update node voltage and current density

Check:

maxIR drop > threshold or t > lifetimeth ?

NO:

9. Update hydrostatic stress.

10. For each tree: Check immortality, find

mintnuci, if mintnuc

i ≤ t, corresponding

branch steps into the growth phase11. Go to step 6YES:

Output: MTTF = t and failed segment, or

satisfies the required lifetime, IR drop info, etc.

• power net or ground net: no update if no void has

been nucleated (have not reached the mintnuc of

this network)

• Step 6: generate modified .spef file

• Step 7: run PERC calcd solver, get new node voltage


New types of EDA tools

Presented tool-prototype provides an opportunity to develop a new type of EDA tools:

1. To perform EM-aware IR-drop assessment. It can be a novel differentiation of the existing “time=0” commercial tools, for example EMIR flow of the Cadence Virtuoso, Cadence Voltus-DP, ANSS Apache Gear RedHawk, SNPS PrimeRail, which can help designers to solve the inverse problem for the IR-drop analysis: generate circuit block current constraints which, if satisfied, will ensure that the grid is safe from voltage drop.

2. To perform EM checking for power grids using physical models (that comprehend material flow between lines) in a mesh model framework (that factors in the redundancy in the power grid).

- It will provide an accurate assessment for time-to-failure.- It will allow to rebalance the metal usage in different parts of the die without impacting the

overall life-time. Some lines can be sized up (widened) and so made more reliable while others are sized down, making them less reliable, while keeping the same overall EM reliability.

- It will be able to generate constraints on the circuit block currents that load the grid, so that if the blocks are designed (or placed) in a way that respects those constraints, then the grid is safe from EM failures by construction and has the required life-time

IRSP 2016, Dresden


Compact model based full-chip EM assessment was developed.

Summary

32

TEAM:Mentor Graphics: Jun-Ho Choy, Armen Kteyan, Marko Chew, Patrick Gibson

UC Riverside: Xin Huang

Shanghai Jiao Tong University: Hai-Bao Chen


THANK YOU

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