introduction to xilinx cplds. introduction to cplds 2 agenda cpld introduction xc9500 family...
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Introduction to Xilinx CPLDs
Introduction to CPLDs 2
Agenda
• CPLD Introduction• XC9500 Family Overview• CoolRunner XPLA3 Overview• CoolRunner-II Overview• IQ Products for Automotive and Industrial• Software Updates and Online Support• Customer Success Stories
Introduction to CPLDs 3
A hybrid of PLD blocks & interconnect for mid-size logic designs
Complex Programmable Logic Deviceinterconnect macrocellsmacrocells
Introduction to CPLDs 4
CPLD Design FlowSynthesisSchematic
Capture
Simulation
Timing AnalyzerBack-AnnotationFitting
0 1 0 0 1 1 1 0 1 1 0 0 1 1 1 1
Specification
VerificationCPLD Design Flow
libraries
netlist
HDL
test vectors
device
printedcircuitboard
Download/Program
System Debug
Implementation
Translate
Gates of the design ...
... are “fitted” to the CPLD
Introduction to CPLDs 5
High Performance• Pin-to-Pin combinatorial delay
– Time from input, thru interconnect to output (ns)
• Maximum registered frequency– Fastest operation of flip-flops (MHz)
CPLD
Macrocell
fMAX (MHz)
CPLD
TPD (ns)
Introduction to CPLDs 6
Wide Package Offering
• High pin count package for lots of I/Os• Maximum logic with minimal I/Os• Logic consolidation for space (vs. discrete devices)• Lower cost packaging
CPLDCPLDCPLD
A smaller CPLD package means a smaller board!
Introduction to CPLDs 7
CPLD Voltage Integration 5v, 3.3v, 2.5v, 1.8v and 1.5v
• 3.3v & 2.5v is the current market trend moving to 1.8v and below for portable and low power applications
• Cost reduction to eliminate 5v supply and regulators with 5v tolerance• Some components will not migrate to 3.3v or below• Need to interface with 3.3v, 2.5V, 1,8v and/or 1.5v components
CPLD3.3/2.5/1.8v
3.3v* 1.8v* 2.5v*
5v*
5v* 5v* 5v* 5v*
* 3.3v CPLD required to interface with 5v, 3.3v & 2.5v components* 2.5v CPLD required to interface with 3.3v, 2.5v & 1.8v components*1.8v CPLD required to interface with 3.3v, 2.5v, 1,8v & 1.5v components
1.5v*
Introduction to CPLDs 8
System Integration Advantage
Introduction to CPLDs 9
System Level Savings• High volume economies of scale
– Single chip for multiple system solutions• Increase volume means reduction in all related costs
• Reference designs– Minimize risk and shorten design cycle
• Lowest cost per I/O– Examples include
• On The Fly (OTF) reconfiguration– Two devices for the price of one
Introduction to CPLDs 10
Designers Need Low Power
• Longer lasting battery life• Lower overall system cost (eliminate fans/ reduce
power supplies)
• Increased system reliability
• Fits into hand-held applications
Introduction to CPLDs 11
TQFP 100
XCR3128XL
Or XCR3064 XL
3.3V parts in the same packagebridging two densities for added
design flexibility
XPLATM Architecture
Equivalent to
CPLD Advantage over Discrete Logic
Real design example: Aircraft Passenger Handset- Smaller PCB with less layers (lower cost) - 7 to 3 layers!- One part to purchase & stock, less inventory- One part to pick and place in manufacture, saving time - Design can be changed and enhanced without PCB re-layout - even in the field- Stock and purchase one part instead of 17 in this example!
High Speed CMOS Logic
74HC373
74HC137
74HC374
74HC137
74HC373
74HC137
74HC373
74HC374 74HC374
74HC138 74HC138 74HC138
74HC157 74HC157 74HC00 74HC00
74HC20 74HC20 74HC21 74HC21
TSSOP 24
SOL 24
SOL 24
Discrete Part No. Function Qty
74HC373 Octal D-type transparant latch 3
74HC374 Octal D-Type Flip Flop 3
74HC157 Quad 2-input multiplexer 2
74HC00 Quad 2 input NAND 2
74HC21 Dual 4 input AND 2
74HC20 Dual 4 input NAND 2
74HC138 3 to 8 line decoder 3
Introduction to CPLDs 12
Xilinx CPLDHigh Volume Shipments
Uni
ts S
hipp
ed
1996 1997 1998 1999 2000 2001 2002 2003 est
• Xilinx currently ships >10M CPLD units per Qtr• WW CPLD market share growing at >1% per Qtr
Introduction to CPLDs 13
CPLD Product Portfolio
– 1.8V RealDigital core– 1.5V - 3.3V I/O – SSTL, HSTL, LVCMOS,
LVTTL– Lower power
• DataGATE– Clocking features
• Clock Divide• CoolCLOCK• DualEDGE
– I/O banking
– 2.5V core– 1.8V - 3.3V I/O– LVCMOS, LVTTL– I/O banking
– 3.3V core– 2.7V - 5V I/O– LVCMOS, LVTTL– Low power
• Fast Zero Power
– 3.3V core– 2.5V - 5.0V I/O– LVCMOS, LVTTL
Quick Design Capability with CPLDs
Introduction to CPLDs 15
Product Lifetime Dynamics
New products stay in volume for shorter periods, Time To Market is critical!
Years in Production
Units
11
Cellular
PCGames
TV
PDA
22
Target high volume,short production life
applications
Introduction to CPLDs 16
ASIC Development Take Too Long!
• Product life cycles maybe shorter than ASIC development time– Multiple ASIC spins may miss the market window– Smaller than expected run rates may not justify the ASIC
development cost
• Long ASIC development times do not allow last minute design revision changes– Revisions leave little time to run in production– Programmable logic allow customers to address market
changes quicker
Introduction to CPLDs 17
ASICs Give Designers Only ONE Chance
CPLD flexibility allow performance analysis and late HW/SW changes meeting customer needs and improves Time To Market with faster, lower risk designs
FirstShip
Spec Design &Verification
System Integration
CPLD
Spec Design & Verification SiliconPrototype
System Integration
SiliconProduction
FirstShip
ASIC
Freeze design here
Freezedesign here
Re-programming allowslast minute design changes
No chance for last minute design changes
Introduction to CPLDs 18
CoolRunner Reference Designs• Shorten design cycle time
– Eliminate code porting costs for next design cycle• Re-use of HDL is reliable and stable
• Minimize design risk by using reference designs– Availability of reference designs prepares you for unexpected system changes
• Update main processor but it does not incorporate correct bus interface
• Further improve customer’s Time To Market– Proven designs for quick turn requirements
Introduction to CPLDs 19
Faster Designs with FREECoolRunner Reference Designs
Application Reference DesignReference
NumberLanguage Macrocell
Target Device
% Utilized
XPATH Module Design XAPP356 VHDL 225 XC2C384 58Springboard Module Design XAPP147 Pocket C, VHDL 67 XC2C128 528 Channel DVM Springboard XAPP146 Pocket C, VHDL 184 XC2C256 71
SECDED XAPP383 VHDL 66 XC2C128 52 N x N Crosspoint Switch XAPP380 VHDL 193 XC2C256 75
IrDA and UART XAPP345 VHDL or Verilog 87 XC2C128 67UARTs XAPP341 VHDL or Verilog 61 XC2C128 47
16b/20b Encoder/Decoder XAPP336 VHDL 76 XC2C128 59
SPI XAPP386 VHDL 128 XC2C256 50
Compact Flash Interface XAPPXXX VHDL XC2C128
I2C Bus Controller XAPP333 VHDL or Verilog 131 XC2C256 51
SMBus Controller XAPP353 VHDL 158 XC2C256 61
Manchester Encoder/Decoder XAPP339 VHDL or Verilog 55 XC2C64 85NAND Interface XAPP354 VHDL or Verilog 9 XC2C32 28
Interface to DDR SDRAM XAPP384 VHDL XC2C256Wireless Wireless Transceiver XAPP358 VHDL 156 XC2C256 60
Multimedia MP3 Player XAPP328 VHDL 219 XC2C256 868-bit Microcontroller XAPP387 VHDL & C 107 XC2C128 848-bit Microcontroller XAPP387 VHDL & C 212 XC2C256 83
8051 Microcontroller Interface XAPP349 VHDL 57 XC2C64 89Microcontroller
PDA
Datacom
Bus Interface
Memory
Free VHDL design code: www.xilinx.com/products/xaw/coolvhdlq.htm
Coming soon
Introduction to CPLDs 20
CoolRunner-II Design Kit
Introduction to CPLDs 21
Development Board & Cable SupportXilinx CPLD Family Manufacturer Description Part Number
XC9500 Memec XC9572XL Deveolpment Board DS-KIT-95XL
XC9500 MemecXC9572XL Dev board, JTAG cable & WebPACK CD DS-KIT-95XL-PAK
CoolRunner XPLA3 Memec XPLA3 Development Board DS-KIT-XPLA3
CoolRunner XPLA3 MemecXPLA3 Dev Board, WebPACK CD & JTAG Cable DS-KIT-XPLA3-PAK
CoolRunner XPLA3 Memec Sprinboard Development Board DS-KIT-SPRINGBOARD
CoolRunner XPLA3 Memec
Sprinboard Development Board, WebPACK CD, JTAG cable, Pocket C Software
DS-KIT-SPRINGBOARD-PAK
CoolRunner II Memec CoolRunner II Development Kit DS-KIT-2C64
CoolRunner II MemecCoolRunner II Development Kit, WebPACK CD & JTAG Cable DS-KIT-2C64-PAK
CoolRunner XPLA3 (XCR3256XL) SilicaXPLA3 Evaluation kit with JTAG cable ADS-XLX-X3-EVL
CoolRunner II SilicaCoolRunner II Evaluation board - XC2C64 & XC2C256 ADS-XLX-CR2-EVL
All CPLDs Xilinx JTAG Parallel Cable HW-JTAG-PC
CoolRunner II XilinxCoolRunner II Demo Board - XC2C64
Note: There may be regional variations because of differentmains voltages - check locally for full part number
Introduction to CPLDs 22
CPLD Software Improvements in 6.1• Ease of use
– Improved CPLD process flow • Single process (Implement Design) will pull
the design through the entire fitting process• Granular control still possible for power
users by expanding individual processes– New design creation aids
• New project wizard leads the user through the project creation process
• Add existing source / Create new source processes - assist in getting started faster
– Centralized process properties menu
• Web Update– Built in utility checks for service packs and
supplemental CPLD updates– Downloads and installs update in single step
XC9500XL / XV Product
Overview
File Number Here
Introduction to CPLDs 23
Xilinx CPLD Process Leadership
Non-VolatileTechnology Memories
Year used inSPLD/CPLD
SPLD/CPLDPioneer
Year used in
Bipolar Fuse 1973 1978 MMI (AMD)
EPROM 1979 1984
5V EEPROM 1986 1991
5V FLASH 1990 1995
3.3V FLASH 1993 1998
Altera EP-series
Lattice ispLSI
Xilinx XC9500
Xilinx XC9500XL
2.5V FLASH 1996 2000 Xilinx XC9500XV
Introduction to CPLDs 24
XC9500Families
XC9500Families
Higher Voltage CPLD Solutions To Fit Every Need
XC9500XC9500 XC9500XLXC9500XL XC9500XVXC9500XV
• 5 / 3.3 / 2.5V core• 36-288 macrocells• High Performance• Superior pin-locking• Low cost
5V core 3.3V core 2.5V core
Introduction to CPLDs 25
XC9500/XL/XV Family FeaturesOverview
• High fMAX = 278 MHz
• Fast TPD = 3.5nS• Instant productivity software tools• Best pin-locking capability• Best ISP/JTAG support• Support for all ATE manufacturers• Advanced packaging including CSP• XC9500XL for 3.3v (5v tolerant & 2.5v I/O)• XCR9500XV for 2.5v (1.8v & 3.3v I/O)• Best CPLD pricing in the industry!
High Performance
Time to Market
Fit in Existing Flow
Package offering
5v,3.3v & 2.5v
Lowest cost
CPLD Designer Needs
Introduction to CPLDs 26
XC9500XL / XV Families3.3v ISP XC9536XL XC9572XL XC95144XL XC95288XL2.5v ISP XC9536XV XC9572XV XC95144XV XC95288XV
Macrocells 36 72 144 288Usable Gates 800 1600 3200 6400tpd (ns) XC9500XL 5 5 5 7.5tpd (ns) XC9500XV 4 5 5 6Registers 36 72 144 288fSYSTEM XC9500XL XC9500XV
178200
178178
178178
125151
Packages PC44 PC44
CS48 CS48
VQ44* VQ44*
VQ64 VQ64
TQ100 TQ100
TQ144 TQ144
CS144 PQ208
BG256
FG256*
CS280*
Introduction to CPLDs 27
XC9500 5V Family
XC9536
Macrocells
UsableGates
tPD (ns)
Registers
Max. UserI/Os
36 72 108 144 216
800 1600 2400 3200 4800
5 7.5 7.5 7.5 10
36 72 108 144216
34 72 108 133166
Packages 44VQ44PC
48CSP
44PC84PC100TQ100PQ
84PC100TQ100PQ160PQ
100TQ100PQ160PQ
288
6400
15
288
192
208HQ352BG
160PQ208HQ352BG
XC9572 XC95108 XC95144 XC95216 XC95288
Introduction to CPLDs 28
XC9500 5V FamilyXC9536
Macrocells
UsableGates
TPD (ns)
Registers
Max. UserI/Os
36 72 108 144 216
800 1600 2400 3200 4800
5 7.5 7.5 7.5 10
36 72 108 144 216
34 72 108 133 166
Packages 44VQ44PC
48CS
44PC84PC100TQ100PQ
84PC100TQ100PQ160PQ
100TQ100PQ160PQ
288
6400
15
288
192
208HQ352BG
160PQ208HQ352BG
XC9572 XC95108 XC95144 XC95216 XC95288
Introduction to CPLDs 29
XC9500XL 3.3V FamilyXC9536XL
Macrocells
Usable Gates
tPD (ns)
Registers
Max. User I/Os
36 72 144
800 1600 3200
5 5 5
36 72 144
36 72 117
Packages PC44VQ44CS48VQ64
PC44VQ44CS48VQ64TQ100 TQ100
CS144TQ144
288
6400
6
288
192
TQ144PQ208BG256FG256CS280
XC9572XL XC95144XL XC95288XL
Introduction to CPLDs 30
XC9500XV 2.5V FamilyXC9536XV
Macrocells
Usable Gates
tPD (ns)
Registers
Max. User I/Os
36 72 144
800 1600 3200
5 5 5
36 72 144
36 72 117
Packages PC44VQ44CS48
PC44VQ44CS48TQ100
TQ100CS144TQ144
288
6400
6
288
192
TQ144PQ208FG256CS280
XC9572XV XC95144XV XC95288XV
Introduction to CPLDs 31
• Complete support of ISP designer’s Product Life Cycle
• Provides industry’s best pin-locking CPLD at lowest price
• Complete “state-of-the-art” software support
• CPLDs key part of the Xilinx “total logic solution”
• Benefits of ISP:– No need for costly device programmers, fewer board re-spins, less scrap
and re-work, reduces design and development time scales, enables field upgrades, eliminates unnecessary package handling,
XC9500/XL/XV Family Features Driving the ISP Revolution
xProgram the whole board not each chip!
CPLDCPLD
CPLDCPLD
Introduction to CPLDs 32
XC9500/XL/XV Family Features Most Complete JTAG Testability
• IEEE Std 1149.1 boundary-scan – Testability & advanced system debug/diagnosis– 8 instructions supported (incl. CLAMP)
• Full support on all family members
• 1532 Industry-standard ISP interface
• Complete 3rd party support
• Benefits of JTAG: Improved testability, higher system reliability, cheaper test
equipment, shorter test time, reduced spare board inventories, reduces device
handling.
Introduction to CPLDs 33
• New 48-pin Chip Scale Package (CSP)– 1/3 size VQFP-44, 82% smaller than PLCC-44– Big board space benefits
• New 144-pin CSP (117 user I/Os)• Uses standard IR surface mounting process• Supports industry’s high growth market segments
– Communications, Computers, Consumer
PC445.6X
XC9500/XL/XV Family Features Innovative CSP Packaging
Introduction to CPLDs 34
• Motherboards for PCs and servers
• PC peripherals and add-on cards– DVD players/controller cards– Graphics cards
• Automotive– Engine control– Automotive navigation systems (GPS)
• Consumer– LAN / DSLAM – Video Games/Toys
XC9500/XL/XV Family FeaturesNew price points open up new apps
Introduction to CPLDs 35
CPLD Software Improvements in 6.1• Ease of use
– Improved CPLD process flow • Single process (Implement Design) will pull
the design through the entire fitting process• Granular control still possible for power
users by expanding individual processes– New design creation aids
• New project wizard leads the user through the project creation process
• Add existing source / Create new source processes - assist in getting started faster
– Centralized process properties menu
• Web Update– Built in utility checks for service packs and
supplemental CPLD updates– Downloads and installs update in single step
CoolRunner XPLA3 Product
Overview
File Number Here
Introduction to CPLDs 36
XCR3000XL Family FeaturesOverview
• High fMAX = 200MHz
• Fast TPD = 5nS
• Instant productivity software tools• Best ISP/JTAG support
• World’s Smallest BGAs (CP56)• Industry’s 1st & most efficient architecture - PLA• Ultra low power operation • No power/performance tradeoffs• Low Power = High Reliability
High Performance
Time to Market
Package offering
Low power
CPLD Designer Needs
THESE PARTS ARE FOR LOW POWER APPLICATIONS!
Introduction to CPLDs 37
CoolRunner XPLA3 FamilyXCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL XCR3512XL
Macrocells 32 64 128 256 384 512
Usable Gates 800 1600 3200 6400 9600 12800
tPD (ns) 5 6 6 7.5 7.5 7.5
fSYS (MHz) 175 145 145 140 127 127
Packages
(max user I/O)
VQ44 (36)
PC44 (36)
CS48 (36)
VQ44 (36)
PC44 (36)
CS48 (40)
CP56 (48)
VQ100 (68) VQ100 (84)
CS144 (108)
TQ144 (108) TQ144 (120)
PQ208 (164)
FT256 (164)
CS280 (164)
PQ208 (172)
FT256 (212)
FG234(220)
PQ208 (172)
FT256 (212)
FG234 (260)
Introduction to CPLDs 38
XCR3000XL Family Features Low Power
• Dynamic Battery Life– Populated with 16 bit counters @ 20MHz– 2 AA batteries– Non CoolRunner devices in low power mode
020406080
100120140160180200
Hours of operation
CY37128M4A3M4LV7000A
3000AISPLSI2128VEXC95144XLXCR3128XL
CompetitiveDevice Families
3.3V CPLD Low Power Leadership!
Introduction to CPLDs 39
XCR3000XL Family Features Extra ‘Hidden’ Benefits of Low Power• Eliminates Expensive Heat Sinks & Cooling
Fans– Heat Sinks: $ 0.50 - $ 12.00– Fans: $ 3.50 and up
• Decreases Power supply component size for:– High Performance– Small Portable Form Factors
• Computing Lap & Palm Enclosures• Higher product density
Less Heat = Higher Performance,Cost Savings & Reliability!
Introduction to CPLDs 40
Thermal Emissions Comparison
• Devices programmed with 16 bit counters with the MSB brought out to an LED and operated at 50MHz
• Where applicable, competitive devices were in non-turbo mode• Note the MACH4 device is 128 macrocells, Lattice is 192 macrocells (largest
in the family)
25 30 35 40 45 50 55 60
Degrees Centigrade
Ambient
Xilinx XCR3256XL-7TC144
Cypress CY37256VP160-100AC
Lattice M4LV-128/64-10YC
Altera EPM7256AETC144-7
Altera EPM3256ATC144-7
Lattice ispLSI2192VE-100LT128
Introduction to CPLDs 41
Thermal CharacteristicsAltera 3K Test
IR00004.ISI
The Altera MAX3000A 256 macrocell device was powered up in low power mode and loaded with a 16 bit counter and clocked at 50MHz. A thermal imaging camera measured the Altera device (P1) to be @ 40.23ºC, (P2) was a CoolRunner XCR3256XL device @ 30.03ºC, the back ground temperature was 22.88ºC (P3)
Introduction to CPLDs 42
Higher System Reliability
Activation Energy EA Aggravated by Temperature! Increased Temperature = Decreased Reliability
FITS
Time
Infant Mortality
Constant Failure Wear out
Temperature
Introduction to CPLDs 43
Lower Power = Smaller Packages
• XPLA3 supports small industry standard packages
• New Chip Scale Packaging– CS48– CP56
44 PLCC
44 VQ
17.6 mm
48 CS
56 CP
12 mm
6 mm
7 mm 12 mm
17.6 mm
7 mm6 m
m
The RealDigital CPLDA New Class of CPLD with
High Performance and Ultra Low Powerwithout Compromise!
Introduction to CPLDs 45
CPLD Sense amp Designs Have Migration Limits
Sense amp based CPLD technologies don’t scale effectively beyond 0.18µ
3.3 VoltDevices
3.3 VoltDevices
2.5 VoltDevices
2.5 VoltDevices
0.18µ
0.25µ
0.35µ
0.50µ
0.60µ
1.8 Volt, 0.18µDevices
1.8 Volt, 0.18µDevices
5.0 VoltDevices
5.0 VoltDevices
High speed andlow power barrier
Sense amps don’t scale well
CR-II FZP
Introduction to CPLDs 46
High Level Architecture
Clock and Control Signals
I/O Blocks
I/O
I/O
I/O
FunctionBlock 1
AIM
Function Block n
I/O
I/O
I/O
I/O Blocks
16 16
16 16
4040
16 FB 16 FB
Fast Inputs Fast Inputs
MC1MC2
MC16
MC1MC2
MC16
PLA PLA
Introduction to CPLDs 47
Function Block Architecture
PLA Array40x56
From AIM40
56 Product Terms
MC 1
MC 16
Global Clocks
Global Set/Reset
16
3
To I/O Block
Feedback to AIM
Introduction to CPLDs 48
Logic Allocation Advantage
Common logic may be shared in CoolRunner-II
X = A & B # CY = A & B # !C
PLA: Requires only 3 product terms!B CA
X Y
B CA
X Y
Can NOT share common logic
PAL: Requires 4 product terms!
Indicates ‘unused’ junctionIndicates ‘fixed’ junction
Indicates ‘used’ junction
Introduction to CPLDs 49
Macrocell Architecture
to I/O
FB Inputsfrom AIM
40
VCC
GNDS
R
D/T Q
CEPTC
from I/O Block (Fast Input) Feedback to AIM
PTACTRGSRGND
PTACTSGSRGND
PTC
PTA
PTB
4 Control Terms
49 P terms
CTCPTC
GCK0GCK1GCK2
LatchDualEDGE
FIF
PLA Array
Macrocell
CK
application notes:http://www.xilinx.com/apps/epld.htm
Introduction to CPLDs 50
I/O Block Characteristics
I/O Pin
VREF
VCCIO
3.3V - 1.5V Input
EnabledControl Term
PTBGTS[0:3]
CGNDOpen DrainDisabled
from Macrocell
VCCIOSlewrate
Input Hysteresis
HSTL & SSTL
to Macrocell(Fast Input)
to AIM I/O Pin
VREF for Local Bank
Weak Pullup/Bus Hold
/4
128 macrocell
and larger devices
Introduction to CPLDs 51
I/O FlexibilityXC2C32 XC2C64 XC2C128 XC2C256 XC2C384 XC2C512
I/O Banks 1 1 2 2 4 4LVTTL33, LVCMOS18, 25, 33 & 15*I/O
SSTL3-1(3.3v), SSTL2-1 (2.5v), HSTL1 (1.5v)
Input hysteresis control
Slew rate control
CoolCLOCK
DataGATE
Clock doubler
Clock divider
Bus hold output
Hot pluggable
Note: 1.5v inputs need hysteresis
Introduction to CPLDs 52
• Traditional CPLDs - bipolar sense amp product terms– Always consumes power
– Even at standby– Performance is traded for
power consumption as devices get larger
• CoolRunner-II RealDigital design uses 100% CMOS for product terms– Virtually no standby current– Combines high performance &
ultra low power– No power limits on device size
RealDigital Design Advantage
RealDigital: CMOS Everywhere - Zero Static Power
C
BA
D
Sense amplifier 0.25mA each - Standby Higher ICC at Fmax
A B C
Turbo vs Non TurboLarger R = slower response
& less powerVcc
Introduction to CPLDs 53
Reducing Power• Icc = C x V x f• To reduce power:
– Lower capacitance– Lower voltage – Lower frequency
0.18 lowers capacitanceLow VCC @ 1.8VHow can we reduce the frequency?
TraditionalSense Amp
Designs
Frequency
1.8 Volt (est)
2.5 Volt
3.3 Volt
~ 200MHz
~ 200mA
Note: 128 MC device estimate
~ 100mA
Icc
Introduction to CPLDs 54
Low Power CPLDs• CoolRunner XPLA3
– Low power– 3.3V core with 5V
tolerance
• CoolRunner II– Ultra Low Power– Lowest Cost– Feature Rich– 1.8V core with 1.5v to
3.3V compatibility
And our parts still run on GRAPEFRUIT!GRAPEFRUIT!
Introduction to CPLDs 55
Beware! Not all ‘Low Power’ Logic is Created Equal!
• Some logic devices have ‘power down’ modes– Complicates timing models (non-deterministic) – Power down modes slow timing (TPD / Fmax) when used
• Some logic devices ‘shut down’ when not active– Latency periods apply for wakeup (typ. 50ns)– No power savings when operating
• Choose Logic to simplify design process– No speed / power tradeoffs– Simple timing models
Introduction to CPLDs 56
500mV Input Hysteresis• Supports simple oscillation schemes • Ideal for slow edge rate, noisy signals
– Analog comparators & sensors– Hall effect switches– IR inputs– R/C oscillators
• Eliminate external Schmitt trigger buffers• Reduces power consumption with slow
signals
CoolRunner-II
+
_In
V
CoolRunner-II
Introduction to CPLDs 57
Solving Signal Integrity Challenges• Noisy, slow analog signals
– Hall Sensor– R/C Oscillator– XTAL input– RFI, EMI effects
Inputhysteresis
• With input hysteresis– Analog signals function as digital inputs– Saves power by non-linear operation– Added noise immunity
Introduction to CPLDs 58
DualEDGE:Performance Enhancing
• In all CoolRunner-II devices• Edge detect doubles clock up to 500MHz• Selectable on a per macrocell basis • Ideal for Double Data Rate (DDR) memory devices
Doubler
Introduction to CPLDs 59
Divide by 4
Clock Divider: Power Efficient
• 128, 256, 384 & 512 macrocell• 2,4,6,8,10,12,14 or 16 digital clock divide• Reduce external oscillators• 50% duty cycle• Reduces cross talkD
ivider
System Clock
Sync Reset
Div_clock Phase bit = 0
Div_clock Phase bit = 1
Introduction to CPLDs 60
CoolCLOCK• Further power reduction plus performance
– Combination of clock divider & DualEDGE (clock doubler)– Divide incoming clock by two (lowing total power), then double at
macrocell for high speed requirements
CPLD
Macrocell
Global
Divider
Doubler
Divideby 2
Originalfrequency
Input
Output
Introduction to CPLDs 61
DataGATE• Another low power enhancement
– Control DataGATE signal externally or internally– User programmable on/off switch for specific inputs
• Only enable inputs when necessary• Great for power reduction on wide logic interfaces
– Latch data when valid, reduces unnecessary signal toggling
DataGATE Diagram
DataGATE control signal
Input pin Gated internal signal
Introduction to CPLDs 62
Xilinx WebPACK™or Foundation ISE Software
Multiple levels of security Affect different mechanisms
Interconnects are buried Multiple security signals
Scattered and layered
Multiple levels of security Affect different mechanisms
Interconnects are buried Multiple security signals
Scattered and layered
1532 in system programming 1149.1 JTAG boundary scan
Fast Programming times
1532 in system programming 1149.1 JTAG boundary scan
Fast Programming times
The Best Design SecurityEasy To Use New Capabilities
Introduction to CPLDs 63
RealDigital CPLD AdvantageRealDigital Features Customer Benefits
0.18 designwith 100% digital core
High performance up to 385MHz, TPD = 3.0ns (32mc) Ultra low power, 16A typ. standby with no price premium
Advanced I/O’s
500mV input hysteresis for improved noise immunity LVTTL, LVCMOS, SSTL, HSTL (1.5v to 3.3v capable) DataGATE for lower power consumption I/O banking for voltage integration (up to 4 banks)
Superior clockmanagement
DualEDGE increased performance > 500MHz toggle rate Reduced power consumption Clock divide & CoolCLOCK
Enhanced security Multiple levels of security for ultimate design protection
Advanced packaging Smallest footprint chip scale High performance BGA with higher I/O per macrocell Lowest cost quad flat pack
Singleworld class software
environment
One software system for all Xilinx products - ISE Free web download or CD - WebPACK Design fit optimizing - WebFITTER Power estimator - XPower
Introduction to CPLDs 64
Supports high-growth market segments: Communications,
Computers, Consumer, especially wireless
Uses standard IR techniques for mounting to PC board
Chip Scale Packaging Leadership
44 PLCC
44 VQFP
17.6 mm
12 mm
6 mm
12 mm
17.6 mm
6 mm
132 CP
56 CP
8 mm
8 mm
Introduction to CPLDs 65
Lower Power = Smaller Packages
• 56-Ball 0.5mm CSP• Provides 44 I/O’s
– 0.5mm pitch• 36 mm2 footprint• Ideal for handheld & portable
applications– PDAs– Portable PCs– Cellular Phones– Telecom & Networking
Equipment– Network Appliances
Introduction to CPLDs 66
Best Package Offering for High Volume Applications
Package widths drawn to scale.
CP132 (8 x 8mm)CP56 (6 x 6mm)
VQ44 (10 x 10mm)VQ100 (14 x 14mm)
FT256 (17 x 17mm)
TQ144 (20 x 20mm)
FG324 (23 x 23mm)
PQ208 (28 x 28mm)
PC44 (16.5 x 16.5mm)
Smallest form factorchip scale packages
Small form factor, highest performance,
BGA packages
Optimized packaging • Smallest size chip scale• Highest performance BGA
• Highest I/O count • Small size
• Lowest cost flat pack
Introduction to CPLDs 67
Features XC2C32 XC2C64 XC2C128 XC2C256 XC2C384 XC2C512Macrocells 32 64 128 256 384 512FToggle (MHz) 500 454 416 416 416 416
FSYSTEM (MHz) 385 270 263 238 217 217Max I/O 33 64 100 184 240 270
I/O Banks 1 1 2 2 4 4LVCMOS, LVTTL 1.5, 1.8, 2.5, 3.3 Yes Yes Yes Yes Yes Yes
HSTL, SSTL No No Yes Yes Yes YesDualEDGE Yes Yes Yes Yes Yes Yes
DataGATE, CoolCLOCK No No Yes Yes Yes YesStandby Power (uW) 28.8 30.6 34.2 37.8 41.4 45.0
Multiple Levels of Security Yes Yes Yes Yes Yes Yes
Packages (size, type) VQ44 (10 x 10mm, leaded) 33 33 PC44 (16.5 x 16.5mm, leaded) 33 33 CP56 (6 x 6mm, chip scale) 33 45 VQ100 (14 x 14mm, leaded) 64 80 80 CP132 (8 x 8mm, chip scale) 100 106 TQ144 (20 x 20mm, leaded) 100 118 118 PQ208 (28 x 28mm, leaded) 173 173 173 FT256 (17 x 17mm, BGA) 184 212 212 FG324 (23 x 23mm, BGA) 240 270
Maxium User I/O
CoolRunner-II Family Overview
Introduction to CPLDs 68
PDA: CoolRunner Reference Design Example
Indicates a CoolCORE
SPI
SMBus
Battery
IrDALED
UART Docking Cradle
P
LCD
Flash
Microprocessor
Keypad
SRAMCompact
Flash
Docking Cradle
LED
LCD
Touch Screen
Battery
Introduction to CPLDs 69
Exploiting Our Technology LeadFe
atur
e Si
ze (m
icro
n)
0.35
0.25
0.18
0.13
0.09
0.07
2000 2001 2002 2003 2004 2005
CPLDs
FPGAs
Clipper
Schooner
Introduction to CPLDs 70
XCR3000XL & XC2C Low Power Features Open Up New Applications
Telecom“Neighborhood” MultiplexorsBay StationsRoutersMultiplexorsPBXsWLANCentral office switchesSpeech recognition systems
PC PeripheralPCMCIA cardsPortable computer displaysWhite board scannersMemory cards
High PerformanceWorkstations and serversVideo graphics cardsStorage Systems
Portable / ConsumerPDAsCell phonesMP3 playersLaptopsDocking stationsBattery powered scannersPDA add-on modulesDigital camerasPortable dictation systems Gas metersHandheld metersSmart Card ReadersPayphones
MedicalPortable syringe pumpHome monitoring systemBlood analyzer
Introduction to CPLDs 71
High Performance3.0ns TPD, FMAX 385Mhz
Improved features
One Ultimate CPLD Solution for All Designs
Low Cost0.18µ = small die size
Lowest cost packaging
Lowest Power9.9mW
16µA typical stand-by
Storage Systems, Routers Set-Top Box, Cell phone Handheld, Portable Equipment
IQ CPLDs for Industrial and
Automotive Applications
Introduction to CPLDs 73
Introducing IQTM Products• Why IQ?
– New range of devices with an extended Industrial Temperature option
– Consists of CPLD and FPGA families already available in I Grade - and the addition of selected devices with an extended
temperature ‘Q’ grade option– IQ - it’s the intelligent choice for Automotive designers!!
• For FPGAs Q grade means:– -40°C to +125°C Junction Temperature
• For CPLDs Q Grade means:– -40°C to +125°C Ambient Temperature
Ambient = the temperature of the air surrounding the deviceJunction = is the temperature of the die in the package
Introduction to CPLDs 74
Industrial and Automotive CPLDs
Core Voltage3.3V
2.5V
Density
1.8V2.5V
288mc
512mc
• Lowest power• Highest speed • Advanced features• Additional security• Smallest packages• Lowest cost• 3.3V tolerant• 1.5V compatible• Up to 4 I/O banks
• Low power• 5V tolerant• Small packaging
• Lowest cost 3.3V• 5V tolerant• Small packaging
• 3.3V tolerant• Small packaging• Up to 4 I/O banks
Introduction to CPLDs 75
CPLD Software Improvements in 6.1• Ease of use
– Improved CPLD process flow • Single process (Implement Design) will pull
the design through the entire fitting process• Granular control still possible for power
users by expanding individual processes– New design creation aids
• New project wizard leads the user through the project creation process
• Add existing source / Create new source processes - assist in getting started faster
– Centralized process properties menu
• Web Update– Built in utility checks for service packs and
supplemental CPLD updates– Downloads and installs update in single step
CPLD Software Update and
Online Support
File Number Here
Introduction to CPLDs 76
Xilinx Online Software Solutions
• Web-deliverable desktop and online design solutions for new, high volume markets
• Industry’s broadest PLD product offering in a single downloadable solution
• Enables fastest time-to-market– Easy to use design tools– Easy to obtain via the web– No license required
• Software upgrades available for online purchase
Introduction to CPLDs 77
ISE 6.1i Software ImprovementsEase of Use
• Improved CPLD process flow – Single process (Implement Design) will
pull the design through the entire fitting process
– Detailed control still possible for power users by expanding individual processes
• New design creation aids– New project wizard leads the user
through the project creation process– Add existing source / create new source
processes - assist in getting started faster
• Centralized process properties menu
Introduction to CPLDs 78
ISE 6.1i Software Improvements
• Web updates– Built in utility checks for service packs and
supplemental CPLD updates– Downloads and installs update in single step
Introduction to CPLDs 79
ISE 6.1i Software Improvements
• HTML report improvements– Integrated browser in the
project navigator environment– Addition of the timing report to
HTML format– Improved graphical presentation
and equation representation
• CPLD support in PACE Pin Assignment and Constraint Editor
Introduction to CPLDs 80
What’s New in ISE 6.1i• CoolRunner-II
– Supported in XPower
• Saturn support– All devices in all ISE
configurations– Supported in XPower
• ISE WebPACK availability– Web release on Sept 22– Free CDs available from
the Xilinx Online Store• Shipping charges apply
– 3,400 downloads per month and growing!
Introduction to CPLDs 81
From WebFITTER
From WebPACK
Buy Products Online• Links to the Xilinx eCommerce page
Introduction to CPLDs 82
Additional Web Based Information
• For additional CoolRunner-II product information
http://www.xilinx.com/products/coolrunner2
• For other Xilinx CPLD related product information
http://www.xilinx.com/products/cpldsolutions
• For CoolRunner-II resource CD
http://www.xilinx.com/forms/coolrunner_literature
Introduction to CPLDs 83
CPLD Software Improvements in 6.1• Ease of use
– Improved CPLD process flow • Single process (Implement Design) will pull
the design through the entire fitting process• Granular control still possible for power
users by expanding individual processes– New design creation aids
• New project wizard leads the user through the project creation process
• Add existing source / Create new source processes - assist in getting started faster
– Centralized process properties menu
• Web Update– Built in utility checks for service packs and
supplemental CPLD updates– Downloads and installs update in single step
Customer Success Stories
File Number Here
Introduction to CPLDs 84
CPLD Success StoriesCustomer 1Market: Automotive
Application: Digital Audio Broadcast Car
Radio
Device: XC9572XL-10TQ100I
Competition: Lattice
Reasons: Pin Locking
Pricing
Easy to use software
Design Win Factors
High Performance
Time to Market
Fit in Existing Flow
Package offering
5v & 3.3v
Low cost
Low power
Introduction to CPLDs 85
CPLD Success StoriesCustomer 2
Market: Datacom
Application: Switching Host Board
Processor
Devices: XC95144XL-10TQ100C
Competition: ASIC
Reasons: High performance
Pin-locking
Flexible interface I/Os
Design Win Factors
High Performance
Time to Market
Fit in Existing Flow
Package offering
5v & 3.3v
Low cost
Low power
Introduction to CPLDs 86
CPLD Success StoriesCustomer 3
Market: Consumer
Application: MP3 Player
Device: XCR3032A-VQ44C
Competition: None, no one could
meet low power
Reasons: Low power
Low Cost, small package
Web-based software
Design Win Factors
High Performance
Time to Market
Fit in Existing Flow
Package offering
5v & 3.3v
Low cost
Low power
Introduction to CPLDs 87
CPLD Success StoriesCustomer 4
Market: Consumer
Application: Fingerprint Point-of-Sale
Terminal
Device: XC95216
Competition: None
Reasons: On-the-fly changes
133 MHz performance
Pin-locking
Superior technical support
Design Win Factors
High Performance
Time to Market
Fit in Existing Flow
Package offering
5v & 3.3v
Low cost
Low power
Introduction to CPLDs 88
CPLD Success StoriesCustomer 5
Market: Commercial
Application: Hand-held Cable TV
Tester
Device: XC95288XL
Competition: Quicklogic
Reasons: Design Flexibility
Price
Performance
Design Win Factors
High Performance
Time to Market
Fit in Existing Flow
Package offering
5v & 3.3v
Low cost
Low power
Introduction to CPLDs 89
CPLD Success StoriesCustomer 6
Market: Telecom
Application: Voice Synthesis
Server Module
Device: XCR3128
Competition: Lattice
Reasons: Power!
Design Win Factors
High Performance
Time to Market
Fit in Existing Flow
Package offering
5v & 3.3v
Low cost
Low power
Introduction to CPLDs 90
CPLD Success StoriesCustomer 7
Market: Instrumentation
Application: Microcontroller
Emulator
Device: XCR3128VQ100C
Competition: Altera
Reasons: Power
Performance
ISP Capabilities
High Performance
Time to Market
Fit in Existing Flow
Package offering
5v & 3.3v
Low cost
Low power
Design Win Factors
Introduction to CPLDs 91
XC9500
• 5v, 36-288 macrocells• Low Cost• 5ns / 200MHz• Best Pin Locking• JTAG• High Endurance(10,000 program cycles)
• 3.3v, 36-288 macrocells• Low Cost• Best Pin Locking• JTAG• High Performance• High Endurance• 5ns / 200MHz
• 2.5v, 36 - 288 macrocells• Low Cost• Best Pin Locking• JTAG• High Performance• High Endurance• 20 year data retention• 4ns / 250 MHz
• 3.3v, 32-512 macrocells• Low Power• JTAG• Logic Flexibility• 5ns / 200MHz• Static power <100uA• 20 year data retention• 5V tolerant I/Os
Motor ControlTest Equipment
Security SystemsCable Modems
Car Nav. SystemsCash Registers
Surveillance cameras
Set Top BoxesAccess ControlsFax Machines
Gaming MachinesIndustrial Control
Remote ControlsDigital Cameras
PDAsSmart Phones
Test EquipmentWeb Pads
Medical EquipmentLabel Printers
Mobile phone add-onsMP3 Players
Web padsPayphones
Smart Card ReadersHand Held GamesUSB Applications
Utility MetersData Logger
Tape DrivesPower Supplies
ModemsAccess ControlsFax Machines
Gaming MachinesIndustrial ControlDAB Car Radios
TFT LCD InterfaceRadio CommsTrain Controller
Slot MachineDigital Printer
Telecomm
Base Stations
Encoders
Decoders
DECT Phones
Line Cards
Industrial Control
LOWPOWER
3.3V2.5V3.3V5V
LOWPOWER
1.8VPortable
PDAsRemote ControlsTest Equipment
Medical
ConsumerCell PhonesMP3 PlayersSet Top Box
Hand Held Games
High SpeedTelecom Switches
Routers
• 1.8v, 32-512 macrocells• Ultra Low Power• Schmitt Trigger Inputs• CoolCLOCK, DataGate• 3.5ns / 303MHz• Static power <100uA• I/Os - LVTTL, LVCMOSSSTL & HSTL
Introduction to CPLDs 92
Xilinx CPLD Summary• XC9500/XL/XV fast, higher voltage, low-cost
– For mainstream 5v, 3.3v & 2.5v designs– Great architectural features (ISP, JTAG, pin-locking)
• Coolrunner XPLA3 low power– Pioneering low power 3.3v product with 5v tolerant I/O– Lowest power 3.3v CPLD - 3x better than nearest 3.3v competitor
• CoolRunner-II High Performance and Low Power – Higher Performance & High Speed (385MHz) at 1.8V– Enhanced clocking & I/O feature set– Lowest power consumption
• DataGATE for even lower power operation– Higher system reliability & system security