CoolRunner XPLA3 CPLD Overview - August 2000

File Number Here

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Industry’s lowest power, highest performance CPLD— <100uA standby power at tPD=5ns— 1/3 the total power of other CPLDs— Uses Fast Zero Power technology— 1149.1 full JTAG compliance— Industrial temp grade operates from 2.7V

Ultra-small chip scale packaging— Perfect for portable applications

Robust architecture delivers great ISP— Full PLA and VFM for utilization and flexibility— Superior pin-locking— Fast input registers

WebPOWERED Software

XPLA3 - The Lowest Power CPLD Solution

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XPLA3 Shatters The Power Limits of Other CPLDs

10.0

CoolRunner Other CPLDs

1X

1000X

0.1

1.0

100.0

Icc StandbyIcc Standby

CoolRunner Other CPLDs

Icc Total*Icc Total*

* average versus comparable densities

1.0

0.5

Nor

mal

ized

mA

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Longer lasting battery life— Longer system operation— Smaller battery packs— More functionality

Lower overall system cost— Smaller power supplies; fans & cooling requirements; sealed systems

Increased system reliability

Fits into hand-held size applications— Chip scale packaging provides optimum functionality in the smallest footprint

Enables products to become “field upgradable”— Accommodates last minute design changes via ISP

XPLA3 Customer Value

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Zero PowerInterconnect

Array

Logic BlockLogic Block

I/O 15

I/O Logic(Mcells)

PLALogic

I/O 0 I/O 1I/O 2

I/O 15

I/O Logic(Mcells)

PLALogic

I/O 0I/O 1I/O 2

3.3v ISP Architecture

ZIA - virtual crosspoint switch 16 macrocells per logic block Full PLA for best connectivity 36 inputs to each logic block

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PLA BenefitMaximum Flexibility

Industry’s first and most efficient PLD architecture

Shared common logic— Allows higher density logic packing

Any and all product terms can be shared by any macrocell— No stranded product terms

Wide logic runs at full speed— Continued deterministic timing with additional product

terms

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Low Power, No Effort

Competitive CPLDs use sense amp product terms— Always consumes power--

even at standby— Performance is traded for

power consumption as devices get larger

CoolRunner FZP design uses TotalCMOS product terms— Virtually no standby current — Total currents @ 1/3 the

competition— Combines high performance

and low power— No power limits on device size

Sense Amplifier .25mA each - Standby Higher ICC at Fmax

FZP: CMOS Everywhere - Zero Static Power

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Head to Head Results

0

20

40

60

80

100

120

140

160

0 1 5 10 20 50 100 150

128 Macrocell Power Comparison XCR3128XL vs Vendor A

Vendor A (Turbo)

Zero standby current(22 uA)

Faster in low powerapplications

Lower power in fastapplications

Vendor A(Non-Turbo)

XCR3128XLReq

uire

d C

urre

nt (m

A)

Frequency (MHz.)

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Lower Power = Higher System Reliability

Activation Energy EA Aggravated by Temperature!Increased Temperature = Decreased Reliability

FITS

Time

Infant Mortality

Constant Failure Wearout

Temperature

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Lower Power = Lower Heat Dissipation

Eliminates Expensive Heat Sinks & Fans— Heat Sinks: $ 0.50 - $ 12.00— Fans: $ 3.50 and up

Decrease Power supply component size Necessary for:

— High Performance— Small Portable Form Factors

– Computing Lap & Palm Enclosures– Higher product density

Less Heat = Higher Performance & Cost Savings & Reliability!

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Lower Power = Lower Thermal Emissions

θJA = Junction-to-Ambient Thermal Resistance

Die

Package

TJ = Junction (Die) Temperature

TC = Case TemperatureθJC = Junction-to-Case Thermal Resistance

TA = Ambient or Still Air Temperature

Board

TC = (Pd X θJA ) + TA

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Thermal Emissions Comparison

Devices programmed with 16 bit counters with the MSB brought out to an LED and operated at 50MHz

Where applicable, competitive devices were in non-turbo mode

Note the MACH4 device is 128 macrocells (no availability), and the Lattice part is 192 macrocells (largest in the family)

25 30 35 40 45 50 55 60

Degrees Centigrade

Ambient

Xilinx XCR3256XL-7TC144

Cypress CY37256VP160-100AC

Lattice M4LV-128/64-10YC

Altera EPM7256AETC144-7

Altera EPM3256ATC144-7

Lattice ispLSI2192VE-100LT128

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Lower Power = Smaller Packages

XPLA3 supports small industry standard packages

New Chip Scale Packaging— CS48— CP56

6x6mm, 0.5mm pitch 7x7mm,

0.8mm pitch 16x16mm, 1.27 pitch

44 PLCC

CS48

CP56

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Lower Power = Smaller Packages

56-Ball 0.5mm CSP Provides 44 I/O’s

— 0.5mm pitch

36 mm2 footprint Ideal for handheld &

portable applications— PDAs— Portable PCs— Cellular Phones— Telecom & Networking

Equipment— Network Appliances

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CoolRunner DeliversLowest Power @ Any Speed

Reduce Icc requirements while increasing system reliability

— Smaller power supply— Eliminate fans— Smaller equipment

Smaller device packaging

— Less board area & more logic packing density

Competitive CPLDs@ 0 MHz

CoolRunner... System Speed

For Free!!

Frequency

Idd

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CoolRunner XPLA3 Family

32 64

800 1600

5 6

Packages(Max. User I/Os)

44VQ (36)44PC (36)48CS (36)

44VQ (36)44PC (36)48CS (40)56CP (48)

100VQ (68)

128

3200

100VQ (84)144CS (108)

144TQ (108)

133 (166*)

XCR3032XL

XCR3064XL XCR3128XL XCR3256XL

Macrocells

Usable Gates

tPD (ns)

fSYS (MHz)

256

6400

133166200

144TQ (120)208PQ (164)

280CS (164)

7.57.5 (6*)

XCR3384XL

384

9600

7.5

133

208PQ (164)

256FG (tbd)280CS(220)

*Available 12/00

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XPLA3 - Sets New Standard in CPLDs

Industry’s lowest power CPLD

Provides real benefits to portable, handheld markets

Free WebPOWERED software solution

Expands Xilinx suite of “high volume” programmable solutions