coolrunner™ cpld overview steve prokosch. ® the coolrunner advantage industry’s lowest power...
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The CoolRunner Advantage
Industry’s lowest power CPLDs— Fast Zero PowerTM means best performance and power
– High speed Tpd 6 ns– Standby current < 0.1 mA– Improved system reliability
— Revolutionary XPLA architecture– Exceptional routability & pin-locking– Fast deterministic timing
— 3.3 and 5.0 volt devices available— Small form factor packaging— Full software support
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XPLATM XPLA2 XPLA3XPLAEnhanced
AdvancedFeature!
Coming Soon
• 3.3 V• 0.5um EECMOS• 32, 64, 128 MCs
• 22V10
• 3.3 Volt Zero Power
• 0.35um EECMOS• 32, 64, 128 MCs
• 3.3 Volt Zero Power• 0.35 um SRAM• 320 - 960 MCs
• 3.3 Volt Zero Power• 0.35u EECMOS
• Up to 2000+ MCs
• 5.0 V•0.5um EECMOS•32, 64, 128 MCs
•22V10
• 5.0 Volt Zero Power• 0.5um EECMOS• 32, 64, 128 MCs
CoolRunner Families
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ZIA
Logic Block
MC15
MC0
MC2I/O
36
16
16
Logic Block
MC15
MC0
MC1I/O
36
16
16
Logic Block
MC15
MC0
MC1I/O
36
16
16
Logic Block
MC15
MC0
MC2I/O
36
16
16
XPLATM Architecture
Central ZIA is Virtual Crosspoint Switch
Patented combination of PAL and PLA structures Flexible routing Deterministic timing
64 macrocell block diagram
36 ZIA Inputs
Control
PLAArray
PALArray
( 32 )
5
6To 16 Macrocells
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The XPLATM Difference A Better Architecture
5
5
5
...
( 32 )
PLAArray
PALArray Easy design changes
— Pin-outs maintained— Deterministic timing— Great ISP
Logic resources allocated with efficiency— Complex logic in the PLA— Up to 37 wide p-terms in 1
macrocell— Common feedback terms shared
CoolRunner CPLDs combine PAL and PLA arrays allowing product terms to be shared
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D / T Q
INIT(P or R)
To ZIA
GND
GTS
CT3CT2
CT4CT5
GNDVcc
CT0CT1GND
CLK0CLK0CLK1CLK1CLK2CLK2CLK3CLK3
Original XPLA Macrocell XPLA Enhanced Macrocell
D / T Q
INIT(P or R)
To ZIA
GND
GTS
CT3CT2
CT4CT5
GNDVcc
CT0CT1GND
CLK0CLK1CLK2CLK3
Enhanced devices have extra product term clock resources 32 macrocell devices have two global clocks
Programmable clock polarity at every macrocell D/T configurable flip-flops Asynchronous preset, reset, and output enable controls
XPLATM CPLD Macrocell
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XPLA Enhanced Architecture Enhanced Clocking
— Adds 2 p-term clocks per logic block— Up to 6, 12 & 20 clocks on 32, 64 & 128 macrocell devices
In System Programmability in all devices— JTAG port for programming— Supports BYPASS and IDCODE commands
3 volt devices on 0.35u process— Fast as 5 volt parts— 5 volt tolerant I/Os
Introducing microBGAs— 64 macrocell Enhanced architecture — 44 I/O in 56 LFBGA package
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XPLA2 Overview
320 macrocell CPLD! 80 macrocell Fast Modules ZIA’s are Virtual Crosspoint Switches
Deterministic Timing Delays 2.0ns GZIA delay
LocalZIA
Fast Module
Lo
ca
l Z
IA
2L
oc
al
ZIA
2
Global ZIA
Lo
ca
l Z
IA
2
Lo
ca
l Z
IA
2
Logic Block
MC19
MC0
MC2I/O
36
16
16
Logic Block
MC19
MC0
MC1I/O
36
16
16
Logic Block
MC19
MC0
MC1I/O
36
16
16
Logic Block
MC19
MC0
MC2I/O
36
16
16
64 64
Global ZIA
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80 macrocells per module 20 mcs per logic block 4 logic blocks per module
LZIA/GZIA are virtual crosspoints
128 connections (64 in / 64 out) between GZIA and LZIA
36 signal fan-in per logic block
2 Global clocks per module
8 async clocks per module (2 control term clocks per logic block)
7.5 ns Tpd in module
4.0 ns fixed delay through GZIA
XPLA2 Fast Module
64 64
36
36
36
36
LocalZIA
Global ZIA
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20 mcs per logic block
4 dedicated PAL p- terms per macrocell
32 PLA p-terms per logic block
Fast Tpds 7.5 ns Tpd through PALs 1.5 ns delay adder for PLA
8 control terms / logic block
Hardwired XOR option / each macrocell XOR between PAL and PLA
sum of product terms
XPLA2 Logic Block
( 32 )
4
8
MC0
4
MC1
4
MC2
4
MC19
PALArray
PLAArray
Control
36 LZIAInputsI
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D / T Q
INIT(P or R)
To ZIA
CT3GND
GTS
CT2
CT4
CT5
GND
Vcc
CT0
CT1
GND
Clk0
Clk1
CT6
CT7
XPLA2 CPLD Macrocell
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36 ZIA Inputs
Control
PLAArray
PALArray
( 32 )
5
6To 16 Macrocells
Reduced routability - no pin locking
Complex logic burns macrocells
Indeterminate timing
Reduced logic density
Flexible routing allows 100% pin locking
No macrocells sacrificed for complex logic
Deterministic timing model
Efficient architecture increases density
Macrocell
Product Term Steering/Stealing Product Term Sharing
Macrocell
Macrocell
Macrocell
The XPLA? Difference - A Better Architecture
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37 Sum of Product Comparison( Logic width vs. Speed and Utilization )
8
9.6 1011
13.2
17
0
6
98
7
2
0
2
4
6
8
10
12
14
16
18
Philips
PZ5032
Altera
7032
AMD
Mach111
Xilinx
XC9536
Lattice
2032
Cypress
CY7C371
ns
Macrocells Lost
XPLA Architecture: Superior for Complex Logic
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CoolRunner Timing Model
Tpd_pal = Combinatorial PALTpd_pla = Combinatorial PAL + PLA
Input Pin Output PinRegistered
Tsu_pal = PAL onlyTsu_pla = PAL + PLA
RegisteredTco
D Q
clock
Output PinInput Pin
clock
Tpd_pal = Combinatorial PAL+ GZDTpd_pla = Combinatorial PAL + PLA + GZD
Input Pin Output PinRegistered
Tsu_pal = PAL + GZDTsu_pla = PAL + PLA + GZD
RegisteredTco
D Q Output PinInput Pin
XPLA Devices and XPLA2 within a Fast Module:XPLA Devices and XPLA2 within a Fast Module:
XPLA2 using the Global ZIA:XPLA2 using the Global ZIA:
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The FZP Difference
All other CPLD’s use CMOS sense amplifiers for p-terms- Always consumes power--even in standby
- Designers must choose between high speed and low power
- Limits maximum device size due to power consumption
CoolRunner FZPTM p- term implementation chains CMOS gates- NO standby current consumption - Fempto Amps leakage
- High speed and low power together
- No power limits on device size
FZPTM: CMOS Everywhere - Zero Static Power
Sense Amplifier.25mA each - StandbyHigher ICC at Fmax
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The FZP Power Advantage32 Macrocell Power Comparison PZ5032 vs Vendor A
Frequency (MHz.)
Req
uire
d C
urre
nt (m
A)
0
20
40
60
80
100
120
140
160
180
0 20 40 60 80 100 120 140 160 180
Vendor A (Turbo)
Vendor A(Non-Turbo)
PZ5032
73.5 MHz.
Zero standby current
Faster in low powerapplications
Lower power in fastapplications
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CPLD ‘MPG’ Comparison: Mhz / mA
2.2E+12
3.3E+09 2.4E+09 1.9E+09 5.3E+08 1.1E+09 3.3E+09 4.0E+090.0E+00
5.0E+11
1.0E+12
1.5E+12
2.0E+12
2.5E+12
PZ5032 Altera7032
AMDMach111
AtmelATF1500
Cypress371
Lattice1016E
Lattice2032
XilinxXC9536
Power efficiency calculated from vendors datasheet values
(1/Tpd) / mA Icc
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Introducing the Micro BGA
Enhanced Clocking Architecture w/ ISP
3 volt devices on 0.35u process (5 Volt tolerant)— Tpd of 7.5 ns— Static current of < 100uA
56 ball LFBGA package provides 44 I/O’s— 0.058 square inch footprint!
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Customer Part Competitor’sPowerConsumption
CoolRunnerPowerConsumption
Power SavingsUsingCoolRunner
Standard 23” x 78”Cabinet
11.25 A 2.4 A 79%
Real Life CoolRunner Story…..More than just battery
life Wireless spread spectrum transmitter
— Customer wanted lower power for noise reduction.— Previous solution was two competing 64 macrocell devices per card— Cabinet contained several cards
Switching to CoolRunner saved customer power and money— Efficient XPLA architecture replaced competitive 64 macrocell devices
with 32 macrocell devices, cutting cost by almost half— Power savings reported by customer (from replacing only the CPLDs!):
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XPLA Software Tools
XPLA Professional— Schematic, PHDL, Verilog and VHDL design entry
– Combine entry modes in single project— Supports all CoolRunner Devices
Features Include:— Graphical simulator included
– Functional and AC timing simulation
Dynamic current consumption estimator— Based on simulation
Support EDIF flows through popular 3rd party tools
FZP Exclusive !
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Conversion of Altera Designs…..
Design Conversion— Import *.tdo file into Pro— Compile and fit design— Use pin editor to create .paf— Refit to new pin out
ISP Tool Can Interface to Altera Byte Blaster!— ISP tool auto detects cable type— Preserve customer hardware while stealing socket!
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22V10 Part Number Cross Reference
P3Z22V10(t)speed,package > XCR22LV10-speed,package(t)
P5Z22V10(t)speed,package >XCR22V10-speed,package(t)
Speed SpeedD 10nsB 15nsPackage PackageA (28 PLCC) PCD (24 SO Low profile) SODH (24 TSSOP) VO
Speed Speed7 7nsD 10nsPackage PackageA (28 PLCC) PCD (24 SO Low profile) SODH (24 TSSOP) VO
Note t : Temp range-> Philips uses a dash for commercial, I for industrial Xilinx uses a C for commercial, I for industrial
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PZ = Coolrunner Zero Power
x = Supply Voltage3 = 3.3 volts5 = 5.0 volts
k = Operating Temperature - = Commercial
I = Industrial
z = Speed Grade (tPD) 7 = 7.5 ns D = 10 ns B = 15 ns
YY = Package DesignatorA = 28 PLCCD = 24 SOL
DH = 24 TSSOP
PxZ22V10kzYY
CoolRunner 22V10 Part Numbering
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PZ5064t,speed,package => XCR5064q-speed,package,t
Note q: Process -> C for 0.50u Enhanced, A for 0.35u EnhancedNote t : Temp range-> Philips uses a dash for commercial, I for industrial Original parts
Philips uses a C for commercial, N for industrial Enhanced (.5u) and XPLA2 parts Philips uses a A for commercial, D for industrial Enhanced (.35u) parts Xilinx uses a C for commercial, I for industrial
Speed => SpeedSpeeds match 1 for 1 (i.e. 10ns = 10ns)
Package PackageA44 PC44A68 PC68A84 PC84BB1 PQ100BB2 PQ160BC VQ44BE TQ128BP VQ100
XPLA Original/Enhanced Part Number Cross Reference
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CoolRunner CPLD Part Numbering
PZ = CoolRunner Zero Power
x = Supply Voltage 3 = 3.3 volts 5 = 5.0 volts
yyy = Macrocell Count
k = Temp / Architecture / Process Tech. - = Comm. / XPLA / 0.5u I = Ind. / XPLA / 0.5u C = Comm. / XPLAEnhanced / 0.5u N = Ind. / XPLAEnhanced / 0.5u A = Comm. / XPLAEnhanced / 0.35u D = Ind. / XPLAEnhanced / 0.35u
S = ISP Device (if S is present)
zz = Speed Grade (tPD) 6 = 6 ns 7 = 7.5 ns 8 = 8 ns 10 = 10 ns12 = 12 ns 15 = 15 ns
YYY = Package DesignatorA44 = 44 PLCC A68 = 68 PLCCA84 = 84 PLCC BB1 = 100 PQFPBB2 = 160 PQFP BC = 44 TQFPBE = 128 LQFP BP = 100 TQFPBE = 160 LQFP EB = 492 PBGAEB = 256 PBGA EC = 56 LFBGA
PZxyyykSzzYYY
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How to contact us
Phone: 1-888-CoolPLD or 1-505-858-2996
FAX: 1-505-822-7804
Email: [email protected]
Website: www.coolpld.com
Address: Philips CPLD Applications Group
9201 Pan American Freeway NE
M/S- 08
Albuquerque, NM 87113
CoolPLD Technical Support