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  • Introduction of AMBA Bus System - VLSI Signal …twins.ee.nctu.edu.tw/courses/embedlab_11/lecture/AMBA.pdfPage 7 AHB system AHB system Bus上傳輸的訊號，可以分成clock，arbitration，address，control
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WWW.ANDESTECH.COM Introduction of AMBA Bus System Introduction of AMBA Bus System

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  • WWW.ANDESTECH.COM

    Introduction of AMBA Bus SystemIntroduction of AMBA Bus System

  • Page 2

    AMBAAMBA

    Advanced Micro-controller Bus ArchitectureAMBA open free AMBA

    AHBAPBASBTest Methodology

  • Page 3

    AMBAAMBA

    AMBA SoC high-performance system bus - AHB low-power peripheral bus APB

    System busAndesembedded processorDMA controlleron-chip memoryinterfacehigh bandwidthperipheral bus protocol AHBAHB Bridge system bus loading

  • Page 4

    AMBAAMBA

    single-clock edge operationnon-tristate implementationburst transferssplit transactionmultiple bus master

  • Page 5

    AHB systemAHB system

    AHB SystemMasterSlaveInfrastructure AHB bus(transfer) master slave infrastructure arbitermaster to slave multiplexorslave to master multiplexordecoderdummy slavedummy master

    AHB arbitermultiple masterarbiter decoder multiple slavetransfer slavemultiplexor bus routing(tristate bus)busmaster slave

  • Page 6

    AHB systemAHB system

  • Page 7

    AHB systemAHB system

    Busclockarbitrationaddresscontrol signalwrite dataread dataresponse signal clock arbitration multiplexormaster to slave multiplexor address, control signal, write dataslave to master multiplexor read data response signal

  • Page 8

    AHB systemAHB system

  • Page 9

    AHB systemAHB system

  • Page 10

    AHB systemAHB system

    AHBbus interconnectioncontrol signal (HBURST, HTRANS )HADDRMaster Arbiter Request/Grant Decoder Slave Selection Control mux output control Slave Arbiter (HTRANS/HBURST)Response signal (HREADY, HRESP)muxArbiter HMASTER master-to-slave multiplexorselection signal

  • Page 11

    AHBbus interconnectionAHBbus interconnection

  • Page 12

    AHB systemAHB system

    Basic transferaddress phase

    address control signal

    data phase write/read data response signal

  • Page 13

    Basic transferBasic transfer

    transferdata phase 1clock cycle slaveHREADY(extend) transferHREADYLOWtransferHIGHtransferstatus SlaveHRESP (OKAY, ERROR )

  • Page 14

    Basic transferBasic transfer

  • Page 15

    Basic transferBasic transfer

    transferphasebusperformanceAHBmultiple transferpipelinetransferaddress phase data phaseoverlap

  • Page 16

    Basic transferBasic transfer

    transfer data phasetransfer address phase overlap transferdata phaseextend address phase

  • Page 17

    Control signalControl signal

    HTRANS[1:0] Transfer TypeHBURST[2:0] : Burst TypeHPROT[3:0] : Protection ControlHSIZE[2:0] : Transfer SizeHWRITE :Transfer Direction

  • Page 18

    Transfer TypeTransfer Type

    AHBtransfer typeIDLEslavetransfermaster slavetransfer data phase zero wait cycleOKAY responseBUSY : burst transfer mastertransfer slavemaster transfer type slaveslave responseIDLE transfer zero wait cycleOKAY responseNONSEQ (Non-sequential) :transfer address controltransferSEQ (Sequential)):address transfercontrol transferburst transfer

  • Page 19

    Transfer Type ExampleTransfer Type Example

    burst transfertypeNONSEQmaster cycleBUSY typetransfer

  • Page 20

    Burst TypeBurst Type

    Burst typeAHB masteraddresstransfer (control)AHBburst typeburst (transferAHB Spec.beat)address incrementingbursttransfer addresstransferaddress transfer sizewrapping burstmemory (transfer size X transfer beat)memory boundarytransfer address boundarytransfer addressboundary 4wrapping bursttransfer sizeword (4 byte)transferaddress0x34(4 byte x 4 transfer)transfer16-byte boundary4 transferaddress0x34, 0x38,0x3C, 0x30

  • Page 21

    Burst TypeBurst Type

    AHB transfer type

  • Page 22

    Burst TypeBurst Type

    4-beat wrapping bursttransfer sizewordaddress16-byte boundary0x3C0x30

  • Page 23

    Burst TypeBurst Type

    INCR typeaddress 0x3C16-byte boundary0x40

  • Page 24

    Burst TypeBurst Type

    8-beat wrapping burstmemory boundary32-byte0x3C0x20

  • Page 25

    Burst TypeBurst Type

    8-beat incrementing bursttransfer size Halfword

  • Page 26

    Burst TypeBurst Type

    undefined length bursttransfer sizeHalfwordword

  • Page 27

    Transfer DirectionTransfer Direction

    HWRITEHIGHmasterdata phasewrite data bus HWDATA[31:0]slavesampleHWRITELOWslave data phaseread data bus HRDATA[31:0]master

  • Page 28

    Transfer SizeTransfer Size

  • Page 29

    Slave ResponseSlave Response

    AHBslave HREADY extend transfer(wait cycle)transfer(HREADY data phasehigh)SlaveHRESP[1:0]master transferstatusAHBtransferstatusOKAY, ERROR, RETRY, SPLIT

  • Page 30

    Slave ResponseSlave Response

    OKAYtransferERRORtransferread-onlymemory locationmemory locationRETRYSPLITslavetransferbus cycletransferbus lockRETRY/SPLIT responsemastertransfermastertransferarbiterbus releasemaster RetrySplitarbitermaster(Priority Scheme)

  • Page 31

    Slave ResponseSlave Response

    RETREY response : arbitermastermasterrequestbus accessmasterRETRY response master request bus masterbusreleasemasterSPLIT response : arbitermasterSPLIT responsemastermaskmaskmasterbus accessmasterarbiterrequestmasterSPLIT responsearbiterbus access dummy master (IDLE transfer master)SPLITslavetransferHSPLITarbiterarbitermasterunmaskmasteraccess bus

  • Page 32

    ArbitrationArbitration

    AHB Multi-Mastermasteraccess busarbiterArbitrationAHB Arbitration

    masteraccess busmasterHBUSREQ signaldrive high(masterHBUSREQ)masteraccess busarbiterHCLKrising edgesamplemaster HBUSREQrequestmaster priority( AHBpriority algorithm)masterHGRANTdrive highaccess bus(master access busarbitermasterHGRANT drive LOWaccess)

  • Page 33

    ArbitrationArbitration

    mastertransfer(access shared memory)masterrequestHLOCKdrive higharbitertransfermasteraccess busarbiterbus releasemastermasterHLOCKdrive LOWarbiterarbitration

  • Page 34

    APBAPB

    APBlow-bandwidth UART1284BusAHBMulti-MasterAPBmasterAPB Bridge(AHB Bus )arbiterrequest/grant APBpipeline operationAPB

    always two-cycle transferno wait cycle & response signal

  • Page 35

    APBAPB

    APB

  • Page 36

    APBAPB

    APBtransferstate diagram

  • Page 37

    APBAPB

    IDLE statetransferslave(PSELx=0)transferPSELx=1, PENABLE=0SETUP stateSETUP stateone-cyclePCLKrising edgeENABLE stateENABLE stateSETUP statePADDR, PSEL, PWRITEPENABLEasserttransferENABLE stateone-cycletransferSETUPENABLE state transferIDLE statetransferSETUP state

  • Page 38

    Write TransferWrite Transfer

    write transferT2->T4 APBwrite transfer(APB transfer always two-cycle)cycle : T2->T3 SETUP Cyclecycle:T3->T4 ENABLE cycletransferaddress/control/datatransferPENABLEdeasserted ( go LOW)PSELxtransferslave(HIGH)dirve Lowpowertransferaddress/writetransfer

  • Page 39

    Write TransferWrite Transfer

  • Page 40

    Read TransferRead Transfer

    Read transfer PWRITELOWaddress/select/strobewrite transfer read transferslaveENABLE cycledataAPB Bridge T4sample

  • Page 41

    APB Slave APB bridgeAPB Slave APB bridge

    APB slavelatch write data :

    PSELHighcyclePSELHIGH PENABLE rising edge

    read dataslavePWRITELOWPSELPENABLEHIGHdrive read data bus

  • WWW.ANDESTECH.COM

    Thank YouThank You

    Introduction of AMBA Bus System AMBAAMBAAMBAAHB systemAHB systemAHB systemAHB systemAHB systemAHB systemAHBbus interconnectionAHB systemBasic transferBasic transferBasic transferBasic transferControl signalTransfer TypeTransfer Type ExampleBurst TypeBurst TypeBurst TypeBurst TypeBurst TypeBurst TypeBurst TypeTransfer DirectionTransfer SizeSlave ResponseSlave ResponseSlave ResponseArbitrationArbitrationAPBAPBAPBAPBWrite TransferWrite TransferRead TransferAPB Slave APB bridgeThank You


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