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AHB-LiteMultilayerInterconnectIP

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AHB-LiteMultilayerInterconnectIPUserGuide



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IntroductionTheRoaLogicAHB-LiteMulti-layerInterconnectisafullyparameterizedsoftIPHigh Performance, Low Latency Interconnect Fabric for AHB-Lite. It allows avirtuallyunlimitednumberofAHB-LiteBusMastersandSlavestobeconnectedwithout the need of bus arbitration to be implemented by the Bus Masters.Instead, Slave Side Arbitration is implemented for each Slave Port within thecore.

The Multi-layer Interconnect supports priority based and Round-Robin basedarbitrationwhenmultiple BusMasters request access to the same Slave Port.Typicallyarbitrationcompleteswithin1clockcycle.

Features

• AMBAAHB-LiteCompatible• Fullyparameterized• UnlimitednumberofBusMastersandSlaves1• Slavesidearbitration• PriorityandRound-Robinbasedarbitration• SlavePortaddressdecoding

1The number of Bus Masters and Slaves is physically limited by the timingrequirements.

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Figure1:Multi-layerInterconnectUsageExample



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1 TableofContentsIntroduction...........................................................................................................2Features..................................................................................................................................................................2

1 TableofContents..............................................................................................3

2 GettingStarted.................................................................................................52.1 Deliverables..............................................................................................................................................52.2 Runningthetestbench.........................................................................................................................62.2.1 Self-checkingtestbench...................................................................................................................62.2.2 Makefilesetup......................................................................................................................................62.2.3 Makefilebackup..................................................................................................................................62.2.4 NoMakefile...........................................................................................................................................6

3 Specifications....................................................................................................73.1 FunctionalDescription.........................................................................................................................73.2 MasterPort................................................................................................................................................83.2.1 MasterPriority....................................................................................................................................83.2.2 BusLockingSupport.........................................................................................................................93.2.3 SpecifyingthenumberofMasterPorts.....................................................................................9

3.3 SlavePort...................................................................................................................................................93.3.1 AddressSpaceConfiguration......................................................................................................103.3.2 SlavePortHREADYOUTandHREADYRouting...................................................................113.3.3 SpecifyingthenumberofSlavePorts......................................................................................12

4 Configurations................................................................................................134.1 Introduction...........................................................................................................................................134.2 CoreParameters..................................................................................................................................134.2.1 HADDR_SIZE.......................................................................................................................................134.2.2 HDATA_SIZE.......................................................................................................................................134.2.3 MASTERS..............................................................................................................................................134.2.4 SLAVES..................................................................................................................................................13

5 Interfaces........................................................................................................145.1 GlobalSignals........................................................................................................................................145.1.1 HRESETn..............................................................................................................................................145.1.2 HCLK......................................................................................................................................................14

5.2 MasterInterfaces.................................................................................................................................145.2.1 mst_HSEL.............................................................................................................................................155.2.2 mst_HTRANS.......................................................................................................................................155.2.3 mst_HADDR.........................................................................................................................................155.2.4 mst_HWDATA.....................................................................................................................................155.2.5 mst_HRDATA......................................................................................................................................155.2.6 mst_HWRITE......................................................................................................................................155.2.7 mst_HSIZE............................................................................................................................................165.2.8 mst_HBURST.......................................................................................................................................165.2.9 mst_HPROT..........................................................................................................................................165.2.10 mst_HREADYOUT...........................................................................................................................175.2.11 ins_HMASTLOCK.............................................................................................................................175.2.12 ins_HREADY......................................................................................................................................175.2.13 ins_HRESP.........................................................................................................................................17

5.3 SlaveInterface.......................................................................................................................................185.3.1 slv_HSEL...............................................................................................................................................18



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5.3.2 slv_HADDR...........................................................................................................................................185.3.3 slv _HRDATA.......................................................................................................................................185.3.4 slv _HWDATA......................................................................................................................................185.3.5 slv _HWRITE.......................................................................................................................................185.3.6 slv_HSIZE..............................................................................................................................................195.3.7 slv_HBURST.........................................................................................................................................195.3.8 slv_HPROT............................................................................................................................................195.3.9 slv_HTRANS.........................................................................................................................................205.3.10 slv_HMASTLOCK.............................................................................................................................205.3.11 slv_HREADYOUT.............................................................................................................................205.3.12 slv_HREADY......................................................................................................................................205.3.13 slv_HRESP..........................................................................................................................................20

6 Resources.......................................................................................................21

7 RevisionHistory..............................................................................................22



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2 GettingStarted2.1 Deliverables

All IP isdeliveredasazipped tarball,whichcanbeunzippedwithall commoncompressiontools(likeunzip,winrar,tar,…).

Thetarballcontainsadirectorystructureasoutlinedbelow.

Figure2-1:IPDirectoryStructure

The doc directory contains relevant documents like user guides, applicationnotes,anddatasheets.

The rtl directory contains the actual IP design files. Depending on the licenseagreement the AHB3Lite Multi-layer Interconnect is delivered as eitherencrypted Verilog-HDL or as plain SystemVerilog source files. Encrypted fileshavetheextension“.enc.sv”,plainsourcefileshavetheextension“.sv”.Thefilesare encryption according to the IEEE-P1735 encryption standard. EncryptionkeysforMentorGraphics(Modelsim,Questasim,Precision),Synplicity(Synplify,Synplify-Pro), andAldec (Active-HDL,Riviera-Pro) areprovided.As such thereshouldbenoissuetargetinganyexistingFPGAtechnology.

Ifanyothersynthesisoranalysis tool isused thenaplainsourceRTLdeliverymay be needed. A separate license agreement andNDA is required for such adelivery.

Thebenchdirectorycontainsthe(encrypted)sourcefilesforthetestbench.

doc

rtl

verilog

sim

rtlsim

bin

run

bench

verilog



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Thesimdirectorycontainsthefiles/structuretorunthesimulations.Section2.2‘Runningthetestbench’providesforinstructionsonhowtousethemakefile.

2.2 Runningthetestbench

TheAHB-LiteMulti-layerInterconnectIPcomeswithadedicatedtestbenchthattestsallfeaturesofthedesignandfinallyrunsafullrandomtest.ThetestbenchisstartedfromaMakefilethatisprovidedwiththeIP.

The Makefile is located in the <install_dir>/sim/rtlsim/run directory. TheMakefile supports most commonly used simulators; Modelsim/Questasim,Cadencencsim,AldecRiviera,andSynopsysVCS.

To start the simulation, enter the <install_dir>/sim/rtlsim/run directory andtype: make <simulator>. Where simulator is any of: msim (formodelsim/questasim), ncsim (for Cadence ncsim), riviera (for Aldec Riviera-Pro), or vcs (for Synopsys VCS). For example typemake msim to start thetestbenchinModelsim/Questasim.

2.2.1 Self-checkingtestbench

The testbenches is a self-checking testbench intended tobe executed from thecommand line. There is no need for a GUI or a waveform viewer. Once thetestbenchcompletesitdisplaysasummaryandclosesthesimulator.

2.2.2 Makefilesetup

The simulator is executed in its associated directory. Inside this directory isanotherMakefilethatcontainssimulatorspecificcommandstostartandexecutethe simulation. The <install_dir>/sim/rtlsim/run/Makefile enters the correctdirectoryandcallsthesimulatorspecificMakefile.

For example modelsim is executed in the <install_dir>/sim/rtlsim/run/msimdirectory. Typingmakemsim loads themainMakefile,which then enters themsimsub-directoryandcallsitsMakefile. ThisMakefilecontainscommandstocompile the RTL and testbench sources with Modelsim, start the Modelsimsimulator,andrunthesimulation.

2.2.3 Makefilebackup

The <install_dir>/sim/rtlsim/bin directory contains backups of the originalMakefiles.ItmaybedesirabletomodifyorextendtheMakefilesortocompletelycleantherundirectory.Usethebackupstorestoretheoriginalsetup.

2.2.4 NoMakefile

For users unfamiliar with Makefiles or those on systems that do not nativelysupport make (e.g. Windows) a run.do file is provided that can be used withModelsim/QuestasimandRiviera-Pro.



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3 Specifications3.1 FunctionalDescription

The Roa Logic AHB-Lite Multi-layer Interconnect is a highly configurableInterconnect Fabric for AMBA AHB-Lite based systems, enabling multipleMasterstobeconnectedtomultipleSlaves.

Connections are dynamically created based on which Slave a Master isaddressing,andoncecreatedenabledirectcommunicationbetweenMasterandSlavewithoutotherMastersbeingawareorinterfering.

A new connection is typically created within one clock cycle, providing highbandwidthandlowlatencycommunicationbetweenMasterandSlave.

Figure3-1:ExampleMaster/SlaveCommunicationSetup

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3.2 MasterPort

An AHB-Lite Bus Master connects to a Master port of the Multi-layerInterconnect. The Master port is implemented as a regular AHB-Lite SlaveInterfacetherebyallowingsupportforcomplexbusstructures.

Figure3-2showsanexamplebusstructurewhereaBusMaster–Master-1–hastwodirectlyconnectedSlaves;theInterconnect-Master-Port1andSlave-4

Figure3-2:ConnectivityExamplefor2BusMasters,4Slaves

To access a Slave, the Interconnect first checks if the designated Slave Port isavailable.IfitisavailabletheSlavePortimmediatelyswitchestotherequestingMaster. If theSlavePort isoccupiedduetoanotherMasteraccessingtheSlave,the Master Port generates wait states until the requested Slave becomesavailable.NotethepipelinednatureoftheAHB-LitebusmaycauseasinglewaitstatetobeinsertedwhentheSlaveswitchestoanewMaster.

TheSlavePortalwaysretainstheconnectiontotheMasteruntilanotherMasterrequests access to that Slave Port; this enables the originalMaster to requestfurtheraccesstotheSlavewithoutincurringanydelayduetoarbitration.

3.2.1 MasterPriority

EachMasterPorthasa3-bitprioritylevelport(mst_priority[2:0]).

WhenmultipleMasterswithdifferentprioritylevelsrequestaccesstothesameSlavePort,accessisalwaysgrantedtotheMasterwiththehighestprioritylevel.IfanewMasterrequestsaccesswhileatransactionisalreadyinprogress,accesswill be granted according to its priority, ahead of any waiting lower priorityMasters.IfMastershavethesameprioritylevel,thenaccessisgrantedbasedonaRound-Robinscheme.

Master priority may be set dynamically, however assigning a static priorityresults in a smaller Interconnect and reduces timing paths. The priority value

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mayonlybechangedwhiletheMasterPortisidle;i.e.mst_HSELisnegated(‘0’)and/orwhenmst_HTRANSisIDLE.

3.2.2 BusLockingSupport

Thepriority levelsdeterminetheorder inwhichMastersaregrantedaccesstothe Slave Port. The Slave Port switches between masters when the currentaccessingmasterisidle(mst_HSELisnegatedand/ormst_HTRANS = IDLE)orwhenthecurrentburstcompletes.

However the current Master may lock the bus by asserting HMASTLOCK; thispreventstheSlaveportswitching.

3.2.3 SpecifyingthenumberofMasterPorts

ThenumberofMasterPortsisspecifiedbytheMASTERSparameter.

3.3 SlavePort

AnAHB-LiteBusSlaveconnectstoaSlavePortof theMulti-layerInterconnect.TheSlavePort is implementedasa regularAHB3LiteMaster Interface therebyallowingsupportforcomplexbusstructuressuchasshowninFigure3-3

Figure3-3:ConnectivityExamplefor2BusMasters,6Slaves

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3.3.1 AddressSpaceConfiguration

Each Slave Port has an Address Base (slv_addr_base) and Address Mask(slv_addr_mask) port. Together these set the address range coveredby theSlavePort.

TheAddressBaseportspecifiesthebaseaddressfortheaddressrangecoveredbytheSlavePortandtheAddressMaskportdefinestheaddressrangecoveredbytheSlavePort.Theinternalportselectsignalisspecifiedasslv_addr_baseANDslv_addr_mask.

The Address Base and Address Mask values may be changed dynamically,however assigning static values results in a smaller Interconnect and reducestiming paths. AddressBase andAddressMaskmay only be changedwhen theslave port(s) are idle. Sincemultiple masters may be active at the same timetrying to access the Interconnect, special care must be taken to ensure NOmasteraccessestheInterconnectwhileupdatingtheAddressBaseandAddressMaskvalues.

TheSlavePortassertsHSELwhenaccessesarewithintheport’saddressrange.WhentheportisnotbeingaccessedHSELisnegated(‘0’),butHTRANSandotherAMBAsignalswillstillprovidedata.ThesesignalsmustbeignoredwhileHSELisnegated(‘0’).

The slave port will output the full address, i.e. all HADDR_SIZE bits, on itsaddressbus(slv_HADDR).ConnectedAMBAslavesshouldusetherelevantleastsignificantbits(LSBs)only.

Example1

slave_addr_base = 32’h1000_0000

slave_addr_mask = 32’hF000_0000

Address-range = 32’h1000_0000 to 32’h1FFF_FFFF

Example2

slave_addr_base = 32’h4000_0000

slave_addr_mask = 32’hE000_0000

Address-range = 32’h4000_0000 to 32’h5FFF_FFFF



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3.3.2 SlavePortHREADYOUTandHREADYRouting

The Slave Port has an HREADYOUT port, which is not part of the AHB-Litespecification. It is required to support slaves on the master’s local bus. TheHREADYsignal,generatedbythemultiplexor,isdriventotheaddressedslave’sHREADYOUTport.

Figure3-4:HREADYOUTandHREADYRouting

ThesimplecaseofwhereonlyonemasterisconnectedtoaMasterPortorwhereonlyasingleslaveisconnectedtoaSlavePortisillustratedbelow.

TherearenomultiplexorsoneithertheMasterBusortheSlaveBus.Sincethereis no other slave on the Master Bus, itsHREADY signal is only driven by theMaster Port’s HREADYOUT signal. Thus the Master Port’s HREADYOUT drivesboththeMaster’sHREADYinputandtheMasterPort’sHREADYinput.

Similarly since there is no other slave on the Slave Bus, the Slave Port’sHREADYOUTsignalsdrivestheslave’sHREADYinputandtheslave’sHREADYOUTsignaldrivestheSlavePort’sHREADYinput.

MasterPort

SlavePort

Mul

tiple

xor

AHB3Lite Slave

AHB3Lite Slave

AHB3Lite Master

HREADYOUT

HREADYOUT

HREADYOUT

HREADY

Mul

tiple

xor

AHB3Lite Slave

AHB3Lite Slave

HREADYOUT

HREADYOUT

HREADY

HREADYOUT

Multi-Layer Interconnect



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Figure3-5:SingleMaster/SlaveRouting

3.3.3 SpecifyingthenumberofSlavePorts

ThenumberofSlavePortsisspecifiedbytheSLAVESparameter.

MasterPort

SlavePort

AHB3Lite Master

HREADYOUT

HREADY

AHB3Lite Slave

HREADYHREADYOUT

Multi-Layer Interconnect

HREADY

HREADYOUT

HREADY



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4 Configurations4.1 Introduction

The Roa Logic AHB-Lite Multi-layer Interconnect is a highly configurableInterconnectFabricforAMBAAHB-Litebasedsystems.Thecoreparametersandconfigurationoptionsaredescribedinthissection.

4.2 CoreParameters

Parameter Type Default DescriptionHADDR_SIZE Integer 32 AddressBusSizeHDATA_SIZE Integer 32 DataBusSizeMASTERS Integer 3 NumberofMasterPortsSLAVES Integer 8 NumberofSlavePorts

Table4-1:CoreParameters

4.2.1 HADDR_SIZE

The HADDR_SIZE parameter specifies the width of the address bus for allMasterandSlaveports.

4.2.2 HDATA_SIZE

TheHDATA_SIZEparameter specifies thewidthof thedatabus forallMasterandSlaveports.

4.2.3 MASTERS

The MASTERS parameter specifies the number of Master Ports on theInterconnectfabric.

4.2.4 SLAVES

TheSLAVESparameterspecifiesthenumberofSlavePortsontheInterconnectFabric.



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5 Interfaces5.1 GlobalSignals

ThecommonsignalsaresharedbetweenalldevicesontheAHBbus.TheAHB-LiteInterconnecthasMasterandSlaveAHB-Litebusesandtheyallusetheglobalsignals.

Port Size Direction DescriptionHRESETn 1 Input AsynchronousactivelowresetHCLK 1 Input Systemclockinput

Table5-1:AMBA3GlobalSignals

5.1.1 HRESETn

Whentheactive lowasynchronousHRESETn input isasserted(‘0’), thecore isputintoitsinitialresetstate.

5.1.2 HCLK

HCLK is the system clock. All internal logic operates at the rising edge of thesystem clock. All AHB bus timings are related to the rising edge ofHCLK. AllMasterandSlaveportsmustoperateatthesameHCLKclock.

5.2 MasterInterfaces

The Master Ports are regular AMB3-Lite slave interfaces. All signals aresupported. See the AHB-Lite specifications for a complete description of thesignals.

Port Size Direction Descriptionmst_HSEL 1 Input BusSelectmst_HTRANS 2 Input TransferTypemst_HADDR HADDR_SIZE Input AddressBusmst_HWDATA HDATA_SIZE Input WriteDataBusmst_HRDATA HDATA_SIZE Output ReadDataBusmst_HWRITE 1 Input WriteSelectmst_HSIZE 3 Input TransferSizemst_HBURST 3 Input TransferBurstSizemst_HPROT 4 Input TransferProtectionLevelmst_HMASTLOCK 1 Input TransferMasterLockmst_HREADYOUT 1 Output TransferReadyOutputmst_HREADY 1 Input TransferReadyInputmst_HRESP 1 Input TransferResponse

Table5-2:MasterPortInterface



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5.2.1 mst_HSEL

TheMasterPortonlyrespondstoothersignalsonitsbuswhenHSELisasserted(‘1’).Whenmst_HSEL isnegated(‘0’) theMasterPortconsidersthebusIDLEandnegatesmst_HREADYOUT(‘0’).

5.2.2 mst_HTRANS

mst_HTRANS indicates the type of the current transfer. It is driven to theconnectedslave.

HTRANS Type Description00 IDLE Notransferrequired

01 BUSY Connectedmasterisnotreadytoacceptdata,butintentstocontinuethecurrentburst.

10 NONSEQ Firsttransferofaburstorasingletransfer11 SEQ Remainingtransfersofaburst

Table5-3:TransferType(HTRANS)

5.2.3 mst_HADDR

HADDRistheaddressbus.ItssizeisdeterminedbytheHADDR_SIZEparameter.Itisdriventotheconnectedslave.

5.2.4 mst_HWDATA

mst_HWDATA isthewritedatabus. ItssizeisdeterminedbytheHDATA_SIZEparameter.Itisdriventotheconnectedslave.

5.2.5 mst_HRDATA

mst_HRDATA is the read data bus. Its size is determined by HDATA_SIZEparameter.Theconnectedslavedrivesit.

5.2.6 mst_HWRITE

mst_HWRITE is the read/write signal.HWRITE asserted (‘1’) indicatesawritetransfer.Itisdriventotheconnectedslave.



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5.2.7 mst_HSIZE

mst_HSIZE indicates the size of the current transfer. It is driven to theconnectedslave.

HSIZE Size Description000 8bit Byte001 16bit HalfWord010 32bit Word011 64bits DoubleWord100 128bit 101 256bit 110 512bit 111 1024bit

Table5-4:TransferSizeValues(HSIZE)

5.2.8 mst_HBURST

Thebursttypeindicatesifthetransferisasingletransferorpartofaburst.Itisdriventotheconnectedslave.

HBURST Type Description000 SINGLE Singleaccess001 INCR Continuousincrementalburst010 WRAP4 4-beatwrappingburst011 INCR4 4-beatincrementingburst100 WRAP8 8-beatwrappingburst101 INCR8 8-beatincrementingburst110 WRAP16 16-beatwrappingburst111 INCR16 16-beatincrementingburst

Table5-5:BurstTypes(HBURST)

5.2.9 mst_HPROT

The protection signals provide information about the bus transfer. They areintended to implement some level of protection. It is driven to the connectedslave.

Bit# Value Description3 1 Cacheableregionaddressed 0 Non-cacheableregionaddressed2 1 Bufferable 0 Non-bufferable1 1 PrivilegedAccess 0 UserAccess0 1 DataAccess 0 Opcodefetch

Table5-6:ProtectionSignals(HPROT)



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5.2.10 mst_HREADYOUT

When a slave is addressed, themst_HREADYOUT indicates that the addressedslave finished the current transfer. The Interconnect IP routes the addressedslave’sHREADYsignaltothemaster.

When no slave is address, the mst_HREADYOUT signal is generated locally,insidetheInterconnect.

5.2.11 mst_HMASTLOCK

The master lock signal indicates if the current transfer is part of a lockedsequence, commonly used for Read-Modify-Write cycles. While themst_HMASTLOCK isasserted, the Interconnect IPcannotswitch theaddressedslave to anothermaster, even if thatmaster has a higher priority. Instead thecurrentmasterretainsaccesstoslaveuntilitreleasesmst_HMASTLOCK.

5.2.12 mst_HREADY

mst_HREADYindicatesthestatusofthelocalHREADYonthemaster’slocalbus.ItisroutedtotheHREADYOUTportoftheaddressedslave.

5.2.13 mst_HRESP

mst_HRESP is thetransferresponse fromtheaddressedslave, itcaneitherbeOKAY (‘0’) or ERROR (‘1’). The Interconnect IP routes the addressed slave’sHRESPporttomst_HRESP.



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5.3 SlaveInterface

The Slave Ports are regular AHB-Lite master interfaces.. All signals aresupported. In addition each Slave Port has a non-standard slv_HREADYOUT.SeetheAHB-Litespecificationsforacompletedescriptionofthesignals.

Port Size Direction Descriptionslv_HSEL 1 Output BusSelectslv_HADDR HADDR_SIZE Output Addressslv_HWDATA HDATA_SIZE Output WriteDataBusslv_HRDATA HDATA_SIZE Input ReadDataBusslv_HWRITE 1 Output WriteSelectslv_HSIZE 3 Output Transfersizeslv_HBURST 3 Output TransferBurstSizeslv_HPROT 4 Output TransferProtectionLevelslv_HTRANS 2 Input TransferTypeslv_HMASTLOCK 1 Output TransferMasterLockslv_HREADY 1 Input TransferReadyInputslv_HRESP 1 Input TransferResponse

Table5-7:DataInterfaceSignals

5.3.1 slv_HSEL

TheMasterPortonlyrespondstoothersignalsonitsbuswhenHSELisasserted(‘1’).Whenslv_HSEL isnegated (‘0’) theMasterPort considers thebus IDLEandnegatesmst_HREADYOUT(‘0’).

5.3.2 slv_HADDR

slv_HADDRisthedataaddressbus.ItssizeisdeterminedbytheHADDR_SIZEparameter.Theconnectedmasterdrivesslv_HADDR.

5.3.3 slv _HRDATA

slv_HRDATA is the readdatabus. Its size isdeterminedby theHDATA_SIZEparameter.Itisdriventotheconnectedmaster.

5.3.4 slv _HWDATA

slv_HWDATA isthewritedatabus. ItssizeisdeterminedbytheHDATA_SIZEparameter.Theconnectedmasterdrivesslv_HADDR.

5.3.5 slv _HWRITE

slv_HWRITE is the read/write signal.HWRITE asserted (‘1’) indicatesawritetransfer.Theconnectedmasterdrivesslv_HWRITE.



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5.3.6 slv_HSIZE

slv_HSIZE indicates the size of the current transfer. The connected masterdrivesslv_HSIZE.

HSIZE Size Description000 8bit Byte001 16bit HalfWord010 32bit Word011 64bits DoubleWord100 128bit 101 256bit 110 512bit 111 1024bit

Table5-8:DataTransferSizes

5.3.7 slv_HBURST

Thebursttypeindicatesifthetransferisasingletransferorpartofaburst.Theconnectedmasterdrivesit.

HBURST Type Description000 Single Singleaccess001 INCR Continuousincrementalburst010 WRAP4 4-beatwrappingburst011 INCR4 4-beatincrementingburst100 WRAP8 8-beatwrappingburst101 INCR8 8-beatincrementingburst110 WRAP16 16-beatwrappingburst111 INCR16 16-beatincrementingburst

Table5-9:BurstTypes(HBURST)

5.3.8 slv_HPROT

Thedataprotectionsignalsprovideinformationaboutthebustransfer.Theyareintended to implement some levelofprotection. The connectedmasterdrivesslv_HPROT.

Bit# Value Description3 1 Cacheableregionaddressed 0 Non-cacheableregionaddressed2 1 Bufferable 0 Non-bufferable1 1 Privilegedaccess.CPUisnotinUserMode 0 Useraccess.CPUisinUserMode0 1 Datatransfer,always‘1’

Table5-10:DataProtectionSignals



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5.3.9 slv_HTRANS

slv_HTRANS indicatesthetypeofthecurrentdatatransfer.

slv_HTRANS Type Description00 IDLE Notransferrequired01 BUSY Notused10 NONSEQ Firsttransferofandataburst11 SEQ Remainingtransfersofandataburst

Table5-11:DataTransferType

5.3.10 slv_HMASTLOCK

The master lock signal indicates if the current transfer is part of a lockedsequence,commonlyused forRead-Modify-Writecycles.Theconnectedmasterdrivesslv_MASTLOCK.

5.3.11 slv_HREADYOUT

Theslv_HREADYOUT signal reflects the state of the connectedMaster Port’sHREADY port. It is provided to support local slaves connected directly to theMaster’sAHB-Litebus.Itisdrivenbytheconnectedmaster’sHREADYport.

5.3.12 slv_HREADY

slv_HREADYindicateswhethertheaddressedslaveisreadytotransferdataornot. When slv_HREADY is negated (‘0’) the slave is not ready, forcing waitstates.Whenslv_HREADY is asserted (‘0’) the slave is readyand the transfercompleted.Itisdriventotheconnectedmaster’sHREADYOUTport.

5.3.13 slv_HRESP

slv_HRESPisthedatatransferresponse,itcaneitherbeOKAY(‘0’)orERROR(‘1’).Itisdriventotheconnectedmaster.

Note: slv_HREADYOUTisnotanAHB-LiteMasterSignal



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6 ResourcesBelowaresomeexampleimplementationsforvariousplatforms.

All implementations arepushbutton, no efforthasbeenundertaken to reduceareaorimproveperformance.

Platform DFF LogicCells

Memory Performance(MHz)

lfxp3c-5 34 103 0 226MHz

Table6-1:ResourceUtilisationExamples



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7 RevisionHistoryDate Rev. Comments1-Sep-2016 1.0 Officialrelease

Table7-1:RevisionHistory

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