ahb-lite apb4 bridge - roa logic · pdf fileinterconnect bridge between the amba 3 ahb-lite...

AHB-LiteAPB4Bridge

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AHB-LiteAPB4BridgeDatasheet

AHB-LiteAPB4Bridge


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IntroductionThe Roa Logic AHB-Lite APB4 Bridge is a fully parameterized soft IPinterconnectbridgebetweentheAMBA3AHB-Litev1.0andAMBAAPBv2.0busprotocols.

The AHB-Lite APB4 Bridge natively supports a single peripheral, howevermultiple APB4 peripherals may be connected to a single bridge by includingsupportingmultiplexerlogic–SeetheAMBAAPBv2.0Protocolspecification.AnAPB4MultiplexerIPimplementingthiscapabilityisavailablefromRoaLogic

APB4BridgewithMultiplePeripherals

Features

• FullsupportforAMBA3AHB-LiteandAPBversion2.0(APB4)protocol• Fullyparameterized• UnlimitedAPB4addressanddatawidthssupported• Configurable number of peripheral-side byte lanes with automatic

handlingofbursttransfers• Supportforseparateclockdomainperinterfacewithautomatichandling

ofcross-domaintiming.

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TableofContentsIntroduction...........................................................................................................2Features..................................................................................................................................................................21 GettingStarted.................................................................................................51.1 Deliverables..............................................................................................................................................51.2 Runningthetestbench.........................................................................................................................61.2.1 Self-checkingtestbench...................................................................................................................61.2.2 Makefilesetup......................................................................................................................................61.2.3 Makefilebackup..................................................................................................................................61.2.4 NoMakefile...........................................................................................................................................6

2 Specifications....................................................................................................72.1 FunctionalDescription.........................................................................................................................72.2 AHB-LiteInterface..................................................................................................................................82.3 APB4Interface.........................................................................................................................................8

3 Configurations..................................................................................................93.1 Introduction..............................................................................................................................................93.1 CoreParameters.....................................................................................................................................93.1.1 HADDR_SIZE.........................................................................................................................................93.1.2 HDATA_SIZE.........................................................................................................................................93.1.3 PADDR_SIZE..........................................................................................................................................93.1.4 PDATA_SIZE..........................................................................................................................................93.1.5 SYNC_DEPTH......................................................................................................................................103.1.6 LimitstoAPB4Address&DataSizes.......................................................................................10

4 Interfaces........................................................................................................114.1 AHB-LiteInterface...............................................................................................................................114.1.1 HRESETn..............................................................................................................................................114.1.2 HCLK......................................................................................................................................................114.1.3 HSEL.......................................................................................................................................................114.1.4 HTRANS................................................................................................................................................124.1.5 HADDR..................................................................................................................................................124.1.6 HWDATA..............................................................................................................................................124.1.7 HRDATA................................................................................................................................................124.1.8 HWRITE................................................................................................................................................124.1.9 HSIZE.....................................................................................................................................................124.1.10 HBURST..............................................................................................................................................134.1.11 HPROT................................................................................................................................................134.1.12 HREADYOUT....................................................................................................................................134.1.13 HMASTLOCK....................................................................................................................................134.1.14 HREADY.............................................................................................................................................134.1.15 HRESP.................................................................................................................................................14

4.2 APB4(Peripheral)Interface...........................................................................................................144.2.1 PRESETn...............................................................................................................................................144.2.2 PCLK.......................................................................................................................................................144.2.3 PSEL.......................................................................................................................................................144.2.4 PENABLE..............................................................................................................................................154.2.5 PPROT....................................................................................................................................................154.2.6 PWRITE.................................................................................................................................................154.2.7 PSTRB....................................................................................................................................................15

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Paul Hardy� 26/4/2017 10:45Deleted: 13

AHB-LiteAPB4Bridge


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4.2.8 PADDR...................................................................................................................................................154.2.9 PWDATA...............................................................................................................................................154.2.10 PRDATA..............................................................................................................................................154.2.11 PREADY..............................................................................................................................................164.2.12 PSLVERR............................................................................................................................................16

5 Resources.......................................................................................................17

6 RevisionHistory..............................................................................................18

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1 GettingStarted1.1 DeliverablesAll IP isdeliveredasazipped tarball,whichcanbeunzippedwithall commoncompressiontools(likeunzip,winrar,tar,…).

Thetarballcontainsadirectorystructureasoutlinedbelow.

Figure1-1:IPDirectoryStructure

The doc directory contains relevant documents like user guides, applicationnotes,anddatasheets.

The rtl directory contains the actual IP design files. Depending on the licenseagreement theAHB-LiteAPB4Bridge is delivered as either encryptedVerilog-HDLor as plain SystemVerilog source files. Encrypted files have the extension“.enc.sv”, plain source files have the extension “.sv”. The files are encryptionaccording to the IEEE-P1735 encryption standard. Encryption keys forMentorGraphics (Modelsim, Questasim, Precision), Synplicity (Synplify, Synplify-Pro),andAldec (Active-HDL, Riviera-Pro) are provided. As such there should be noissuetargetinganyexistingFPGAtechnology.

Ifanyothersynthesisoranalysis tool isused thenaplainsourceRTLdeliverymay be needed. A separate license agreement andNDA is required for such adelivery.

Thebenchdirectorycontainsthe(encrypted)sourcefilesforthetestbench.

doc

rtl

verilog

sim

rtlsim

bin

run

bench

verilog

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Thesimdirectorycontainsthefiles/structuretorunthesimulations.Section1.2‘Runningthetestbench’providesforinstructionsonhowtousethemakefile.

1.2 Runningthetestbench

The AHB-Lite APB4 Bridge IP comes with a dedicated testbench that tests allfeaturesofthedesignandfinallyrunsafullrandomtest.ThetestbenchisstartedfromaMakefilethatisprovidedwiththeIP.

The Makefile is located in the <install_dir>/sim/rtlsim/run directory. TheMakefile supports most commonly used simulators; Modelsim/Questasim,Cadencencsim,AldecRiviera,andSynopsysVCS.

To start the simulation, enter the <install_dir>/sim/rtlsim/run directory andtype: make <simulator>. Where simulator is any of: msim (formodelsim/questasim), ncsim (for Cadence ncsim), riviera (for Aldec Riviera-Pro), or vcs (for Synopsys VCS). For example typemake msim to start thetestbenchinModelsim/Questasim.

1.2.1 Self-checkingtestbench

The testbenches is a self-checking testbench intended tobe executed from thecommand line. There is no need for a GUI or a waveform viewer. Once thetestbenchcompletesitdisplaysasummaryandclosesthesimulator.

1.2.2 Makefilesetup

The simulator is executed in its associated directory. Inside this directory isanotherMakefilethatcontainssimulatorspecificcommandstostartandexecutethe simulation. The <install_dir>/sim/rtlsim/run/Makefile enters the correctdirectoryandcallsthesimulatorspecificMakefile.

For example modelsim is executed in the <install_dir>/sim/rtlsim/run/msimdirectory. Typingmakemsim loads themainMakefile,which then enters themsimsub-directoryandcallsitsMakefile. ThisMakefilecontainscommandstocompile the RTL and testbench sources with Modelsim, start the Modelsimsimulator,andrunthesimulation.

1.2.3 Makefilebackup

The <install_dir>/sim/rtlsim/bin directory contains backups of the originalMakefiles.ItmaybedesirabletomodifyorextendtheMakefilesortocompletelycleantherundirectory.Usethebackupstorestoretheoriginalsetup.

1.2.4 NoMakefile

For users unfamiliar with Makefiles or those on systems that do not nativelysupport make (e.g. Windows) a run.do file is provided that can be used withModelsim/QuestasimandRiviera-Pro.

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2 Specifications2.1 FunctionalDescriptionThe Roa Logic AHB-Lite APB4 Bridge is a highly configurable, fullyparameterized soft IP interconnect bridge between the AMBA 3 AHB-Lite v1.0andAMBAAPBv2.0busprotocols.

TheseprotocolsarecommonlyreferredtoasAHB-LiteandAPB4respectively–these terms will be used throughout this datasheet. All signals defined in theAHB-LiteandAPB4specificationsarefullysupported.

The IP contains 2 interfaces; an AHB-Lite Slave Interface and anAPB4MasterInterface.Transactions receivedon theAHB-Lite Slave Interface are translatedinto APB4 transactions on the APB4 Master Interface. The IP automaticallygeneratesAPB4bursttransactionsiftheAPB4datawidthislessthantheAHB-Litedatawidth.

EachinterfacecanoperateonaseparateclockdomainandtheIPautomaticallyhandlesallcrossclockdomainsynchronizationrequirements.

Figure2-1:BridgeSignaling

Notes: 1. TheAPB4InterfaceclockfrequencymustbelessthanorequaltotheAHB-Liteinterfaceclockfrequency

2. TheAPB4InterfacedatawidthmustbelessthanorequaltothedatawidthoftheAHB-Liteinterface

3. AHB-LiteandAPB4Interfacedatawidthsmustbeanintegermultipleofbytes.

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2.2 AHB-LiteInterfaceAn AHB-Lite Bus Master connects to the AHB interface of the AHB-Lite APB4Bridge.TheAHBinterfaceisimplementedasaregularAHB-LiteSlaveInterface,supportingallsignalsintheAMBA3AHB-Litev1.0protocolspecification

2.3 APB4Interface

AnAPB4BusSlaveconnectstotheAPBinterfaceoftheBridgeIP.TheAPBportisimplementedasaregularAPB4MasterInterfacesupportingallsignalsoftheAMBAAPBv2.0protocolspecification.ThisallowsasingleAPB4PeripheraltobeconnecteddirectlytotheInterfacewithoutfurtherlogicrequirements.

MultipleperipheralscansharetheAPB4Interfacethroughappropriatedecodingandmultiplexingoftheinterfacesignals.RoaLogicprovidesanadditionalAPB4MultiplexerIPtoimplementthiscapability.

Figure2-2:APB4MultiplexingPeripherals

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AHB-LiteAPB4Bridge


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3 Configurations3.1 IntroductionTheRoaLogicAHB-LiteAPB4Bridge isa fullyconfigurablebridgeIPtoenableAHB-Lite based hosts to communicatewith APB4 based peripherals. The coreparametersandconfigurationoptionsaredescribedinthissection.

3.1 CoreParameters

Parameter Type Default DescriptionHADDR_SIZE Integer 32 AHB-LiteAddressBusSizeHDATA_SIZE Integer 32 AHB-LiteDataBusSizePADDR_SIZE Integer 10 APB4AddressBusSizePDATA_SIZE Integer 8 APB4DataBusSizeSYNC_DEPTH Integer 3 ClockDomainCrossingSyncStages

Table3-1:CoreParameters

3.1.1 HADDR_SIZE

TheHADDR_SIZEparameterspecifiesthewidthoftheaddressbusfortheAHB-Liteinterface.

3.1.2 HDATA_SIZE

TheHDATA_SIZEparameterspecifiesthewidthofthedatabusfortheAHB-Liteinterface. This parametermust equal an integermultiple of bytes and also begreaterorequaltoPDATA_SIZE:

Conditions: (HDATA_SIZE ≥ PDATA_SIZE) (HDATA_SIZE MOD 8 = 0)

3.1.3 PADDR_SIZE

ThePADDR_SIZEparameterspecifiesthewidthoftheaddressbusfortheAPB4(i.e.peripheral)interface.

3.1.4 PDATA_SIZE

ThePDATA_SIZE parameter specifies thewidthof thedatabus forAPB4 (i.e.peripheral) interface. This parameter must equal an integer multiple of bytesandalsobelessthanorequaltoHDATA_SIZE.

Conditions:(PDATA_SIZE ≤ HDATA_SIZE) (PDATA_SIZE MOD 8 = 0)

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3.1.5 SYNC_DEPTH

The APB4 Bridge IP supports operating the AHB-Lite and APB4 interfaces inseparate, unrelated clock domains. The IP automatically handles cross-domainsynchronization and the SYNC_DEPTH parameter determines the number ofsynchronizationstagesbetweentheseclockdomains.

Increasing this parameter reduces the possibility of metastability for signalscrossingbetweenthetwodomains,butatthecostofincreasedlatency.

TheminimumanddefaultvalueoftheSYNC_DEPTHparameteris3.

3.1.6 LimitstoAPB4Address&DataSizes

The AMBA APB v2.0 Protocol specification limits the widths of both Address(PADDR_SIZE) andData (PDATA_SIZE)buses to32bits. However theAHB-LiteAPB4BridgeIPAddressandDatasizesarenotsimilarlyconstrained–anyAddresswidthandanybyte-alignedDatawidthissupportedbytheIP.

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4 Interfaces4.1 AHB-LiteInterfaceThe AHB-Lite interface is a regular AHB-Lite Slave Interface. All signals aresupported.See theAMBA3AHB-LiteSpecification foracompletedescriptionofthesignals.

Port Size Direction DescriptionHRESETn 1 Input AsynchronousactivelowresetHCLK 1 Input ClockInputHSEL 1 Input BusSelectHTRANS 2 Input TransferTypeHADDR HADDR_SIZE Input AddressBusHWDATA HDATA_SIZE Input WriteDataBusHRDATA HDATA_SIZE Output ReadDataBusHWRITE 1 Input WriteSelectHSIZE 3 Input TransferSizeHBURST 3 Input TransferBurstSizeHPROT 4 Input TransferProtectionLevelHMASTLOCK 1 Input TransferMasterLockHREADYOUT 1 Output TransferReadyOutputHREADY 1 Input TransferReadyInputHRESP 1 Input TransferResponse

Table4-1:AHB-LiteInterfacePorts

4.1.1 HRESETn

WhentheactivelowasynchronousHRESETninputisasserted(‘0’),theinterfaceisputintoitsinitialresetstate.

4.1.2 HCLK

HCLKistheinterfacesystemclock.AllinternallogicfortheAMB3-LiteinterfaceoperatesattherisingedgeofthissystemclockandAHBbustimingsarerelatedtotherisingedgeofHCLK.

The frequency of HCLK must be greater than or equal to that of the APB4(Peripheral)InterfaceclockPCLK:

Conditions: Freq(HCLK)≥Freq(PCLK)

4.1.3 HSEL

The AHB-Lite interface only responds to other signals on its bus – with theexception of the global asynchronous reset signal HRESETn – when HSEL is

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asserted(‘1’).WhenHSEL isnegated(‘0’)theinterfaceconsidersthebusIDLEandnegatesHREADYOUT(‘0’).

4.1.4 HTRANS

HTRANSindicatesthetypeofthecurrenttransfer.

HTRANS Type Description00 IDLE Notransferrequired01 BUSY Connectedmasterisnotreadytoacceptdata,but

intentstocontinuethecurrentburst.10 NONSEQ Firsttransferofaburstorasingletransfer11 SEQ Remainingtransfersofaburst

Table4-2:AHB-LiteTransferType(HTRANS)

4.1.5 HADDR

HADDRistheaddressbus.ItssizeisdeterminedbytheHADDR_SIZEparameterandisdriventotheconnectedperipheral.

4.1.6 HWDATA

HWDATA is the write data bus. Its size is determined by the HDATA_SIZEparameterandisdriventotheconnectedperipheral.

4.1.7 HRDATA

HRDATAisthereaddatabus.ItssizeisdeterminedbyHDATA_SIZEparameterandissourcedbytheAPB4peripheral.

4.1.8 HWRITE

HWRITE is the read/write signal. HWRITE asserted (‘1’) indicates a writetransfer.

4.1.9 HSIZE

HSIZEindicatesthesizeofthecurrenttransfer.

HSIZE Size Description000 8bit Byte001 16bit HalfWord010 32bit Word011 64bits DoubleWord100 128bit 101 256bit 110 512bit 111 1024bit

Table4-3:TransferSizeValues(HSIZE)

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4.1.10 HBURST

HBURSTindicatesthetransactionbursttype–asingletransferorpartofaburst.

HBURST Type Description000 SINGLE Singleaccess001 INCR Continuousincrementalburst010 WRAP4 4-beatwrappingburst011 INCR4 4-beatincrementingburst100 WRAP8 8-beatwrappingburst101 INCR8 8-beatincrementingburst110 WRAP16 16-beatwrappingburst111 INCR16 16-beatincrementingburst

Table4-4:AHB-LiteBurstTypes(HBURST)

4.1.11 HPROT

TheHPROTsignalsprovideadditionalinformationaboutthebustransferandareintendedtoimplementalevelofprotection.

Bit# Value Description3 1 Cacheableregionaddressed 0 Non-cacheableregionaddressed2 1 Bufferable 0 Non-bufferable1 1 PrivilegedAccess 0 UserAccess0 1 DataAccess 0 Opcodefetch

Table4-5:AHB-LiteTransactionProtectionSignals(HPROT)

4.1.12 HREADYOUT

HREADYOUTindicatesthatthecurrenttransferhasfinished.

4.1.13 HMASTLOCK

HMASTLOCK, the instruction master lock signal, indicates if the currenttransfer is part of a locked sequence, commonly used for Read-Modify-Writecycles.

4.1.14 HREADY

HREADY indicateswhetherornottheaddressedperipheral isreadytotransferdata. When HREADY is negated (‘0’) the peripheral is not ready, forcing waitstates.WhenHREADY is asserted (‘1’) theperipheral is ready and the transfercompleted.

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4.1.15 HRESP

HRESP is the instruction transfer response and indicatesOKAY (‘0’) orERROR(‘1’).AnerrorresponsecausesanInstructionBusErrorInterrupt.

4.2 APB4(Peripheral)Interface

TheAPB4InterfaceisaregularAPB4MasterInterface.Allsignalsdefinedintheprotocol are supported as described below. See the AMBA APB Protocol v2.0Specificationsforacompletedescriptionofthesignals.

Port Size Direction DescriptionPRESETn 1 Input AsynchronousactivelowresetPCLK 1 Input ClockInputPSEL 1 Output PeripheralSelectPENABLE 1 Output PeripheralEnableControlPPROT 3 Output TransferProtectionLevelPWRITE 1 Output WriteSelectPSTRB PDATA_SIZE/8 Output ByteLaneIndicatorPADDR PADDR_SIZE Output AddressBusPWDATA PDATA_SIZE Output WriteDataBusPRDATA PDATA_SIZE Input ReadDataBusPREADY 1 Input TransferReadyInputPSLVERR 1 Input TransferErrorIndicator

Table4-6:APB4PeripheralInterfacePorts

4.2.1 PRESETn

When the active low asynchronousPRESETn input is asserted (‘0’), the APB4interfaceisputintoitsinitialresetstate.

4.2.2 PCLK

PCLKistheAPB4interfacesystemclock.AllinternallogicfortheAPB4interfaceoperatesattherisingedgeofthissystemclockandAPB4bustimingsarerelatedtotherisingedgeofPCLK.

The frequency of PCLK must be less than or equal to that of the AHB-LiteInterfaceclockHCLK:

Conditions: Freq(PCLK)≤Freq(HCLK)

4.2.3 PSEL

TheAPB4BridgegeneratesPSEL, signaling toanattachedperipheral that it isselectedandadatatransferispending.

Note: To support multiple APB4 peripherals, individual PSEL signalsmust be generated per peripheral – Roa Logic provides an

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additionalAPB4MultiplexerIPtosupportthisrequirement

4.2.4 PENABLE

TheAPB4BridgeassertsPENABLEduring the2ndandsubsequentcyclesofanAPB4datatransfer.

4.2.5 PPROT

PPROT[2:0]indicatestheprotectiontypeofthedatatransfer,with3levelsofprotectionsupportedasfollows:

Bit# Value Description2 1 InstructionAccess 0 DataAccess1 1 Non-SecureAccess 0 SecureAccess0 1 PrivilegedAccess 0 NormalAccess

Table4-7:APB4TransactionProtectionTypes

4.2.6 PWRITE

PWRITE indicatesadatawriteaccesswhenassertedhigh(‘1’)andareaddataaccesswhende-asserted(‘0’)

4.2.7 PSTRB

ThereisonePSTRBsignalperbytelaneoftheAPB4writedatabus(PWDATA).These signals indicatewhich byte lane to update during awrite transfer suchthatPSTRB[n]correspondstoPWDATA[(8n+7):8n].

4.2.8 PADDR

PADDR istheAPB4addressbus.ThebuswidthisdefinedbythePADDR_SIZEparameterandisdrivenbytheAPB4Bridgecore.

4.2.9 PWDATA

PWDATAistheAPB4writedatabusandisdrivenbytheAPB4Bridgecoreduringwrite cycles, indicatedwhenPWRITE is asserted (‘1’). The buswidthmust bebyte-alignedandisdefinedbythePDATA_SIZEparameter.

4.2.10 PRDATA

PRDATAistheAPB4readdatabus.Anattachedperipheraldrivesthisbusduringreadcycles,indicatedwhenPWRITEisde-asserted(‘0’).Thebuswidthmustbebyte-alignedandisdefinedbythePDATA_SIZEparameter.

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4.2.11 PREADY

PREADY is driven by the attached peripheral. It is used to extend an APB4transfer.

4.2.12 PSLVERR

PSLVERR indicates a failed data transfer when asserted (‘1’). As APB4peripherals are not required to support this signal it must be tied LOW (‘0’)whenunused.

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5 ResourcesBelowaresomeexampleimplementationsforvariousplatforms.

All implementations arepushbutton, no efforthasbeenundertaken to reduceareaorimproveperformance.

Platform DFF LogicCells

Memory Performance(MHz)

Table5-1:ResourceUtilizationExamples

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6 RevisionHistoryDate Rev. Comments01-Feb-2017 1.0 InitialRelease

Table6-1:RevisionHistory

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