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  • Yedukondalu * et al. ISSN: 2250-3676

    [IJESAT] [International Journal of Engineering Science & Advanced Technology] Volume-3, Issue-4, 176-193

    IJESAT | Aug-Sep 2013 176

    Available online @



    1.yedukondalu(vol-03,iss-04,2013 edition),2.Dr.shaik meeravali

    1. YEDUKONDALU.K ,M.Tech (Embedded Systems), ECE Department, RRS College of Engineering & Technology, Muttangi, AP


    2 Dr.shaik meeravali professor&hod department of ece, RRS College of Engineering & Technology, Muttangi, AP


    This paper proposes a multiresolution AHB on-chip bus tracer named SYS-HMRBT (AHB multiresolution

    bus tracer) for versatile system-on-chip (SoC) debugging and monitoring. The bus tracer is capable of capturing the bus trace with different resolutions, all with efficient built-in compression mechanisms, to meet a diverse range of needs. In addition, it allows users to switch the trace resolution dynamically so that appropriate resolution levels can be applied to different segments of the trace. On the other hand, SYS-HMRBT supports tracing after/before an event

    triggering, named post-triggering trace/pre-triggering trace, respectively. SYS-HMRBT runs at 500 MHz and costs 42 K gates in TSMC 0.13- m technology, indicating that it is capable of real time tracing and is very small in modern SoCs. Experiments show that the bus tracer achieves very good compression ratios of 79%96%, depending on the selected resolution mode. As a case study, it has been integrated into a 3-D graphics SoC to facilitate the debugging and

    monitoring of the system behaviors. The SoC has been successfully verified both in field-programmable gate array and a test chip.

    IndexTermsAHB,AMBA,compression,multiresolution, periodical triggering, post-T trace, pre-T trace, real

    time trace, system-on-chip (SoC) debugging.

  • Yedukondalu* et al. ISSN: 2250-3676

    [IJESAT] [International Journal of Engineering Science & Advanced Technology] Volume-3, Issue-4, 176-193

    IJESAT | Aug-Sep 2013 177

    Available online @



    he ON-CHIP bus is an important system-on-chip (So C)

    infrastructure that connects major hardware co m po n ents.

    Monitoring the on-chip bus signals is crucial to the SoC de-

    bugging and performance an alysis/o pt imi z at ion . U nf ort un at ely,

    such signals are difficult to observe since they are deeply em-

    bedded in a SoC and there are often no sufficient I/O pins to

    access these signals. Therefore, a straightforward approach is

    to embed a bus tracer in SoC to capture the bus signal trace and

    store the trace in an on-chip storage such as the trace me mo ry

    which could then be off loaded to outside world (the trace an a-

    lyzer software) for analysis.

    Unfortunately, the size of the bus trace grows rapidly. For ex-

    ample, to capture AMBA AHB 2.0 [1] bus signals running at

    200 MHz, the trace grows at 2 to 3 GB/s. Therefore, it is highly

    desirable to compress the trace on the fly in order to reduce the

    trace size. However, simply capturing/compressing bus signals

    is not sufficient for SoC debugging and analysis, since the de-

    bugging/analysis needs are versatile: some designers need all

    signals at cycle-level, while some others only care about the

    transactions. For the latter case, tracing all signals at cycle-level

    wastes a lot of trace memory. Thus, there must be a way to cap-

    ture traces at different abstraction levels based on the specific

    debugging/analysis need.

    This paper presents a real-t ime multi-resolution AHB

    on-chip bus tracer, named SYS-HMRBT (aHb mult iresolution

    bus tracer). The bus tracer adopts three trace compression

    mechanis ms to achieve high trace compression ratio. It sup-

    ports multiresolution tracing by capturing traces at different

    timing and signal abstraction levels. In addition, it provides

    the dynamic mode change feature to allow users to switch the

    resolution on-the-fly for different portions of the trace to match

    specific debugging/analysis needs. Given a trace memory of

    fixed size, the user can trade off between the granularity and

    trace length to make the most use of the trace memory. In

    addition, the bus tracer is capable o f tracing signals before/after

    the event triggering, named pre-T/post-T tracing, respectively.

    This feature provides a more flexible tracing to focus on the

    interesting points.

    The rest of this paper is organized as fo llows. Section II sur-

    veys the related work. Section III discusses the features in trace

    gr an ul ari ty and t rac e di r e ct io n. S e ct ion IV p r es ents the hardware

    architecture of our bus tracer. Section V provides experiments

    to analyze the compression ratio, trace depth, and cost of our

    bus tracer. A case study is also conducted to integrate the bus

    tracer with a 3-D graphics SoC. Finally, Section VI concludes

    this paper and gives directions for future research.


    Since the huge trace size limits the trace depth in a trace

    memory, there are hardware approaches to compress the traces.

    The app ro a ch es can be divide d into loss y and lossl ess t race com-


    The lossy trace compression approach achieves high com-

    pression ratio by sacrificing the accuracy; the original signals

    cannot be reconstructed from the trace. The purpose of this ap-

    proach is to identify if a problem occurs. Anis and Nicolici

    [2] use the multiple input signature register (MISR) to perform

    lossy compression. The results are stored in a trace memory

    and compared with the golden patterns to locate the range of

    the erroneous signals. The locating needs rerunning the system

    several t imes with finer and finer resolution until the size of

    the search range can fit in the trace memory. Such approach

    is suitable for deterministic and repeatable system behaviors.

    However, for a complex SoC with multiple independent IPs, the

    on-chip bus activities are usually not deterministic and repeat-

    able. Therefore, lossless compression approaches are more ap-

    propriate for realt ime on-chip bus tracing.

    Existing on-chip bus tracers mostly adopt lossless compres-

    sion approaches. ARM provides the AMBA AHB trace macro-

    cell (HTM) [3] that is capable of tracing AHB bus signals, in-

    clu din g th e inst r u ct ion a d dr ess, d at a ad dr ess , an d co ntr ol signals.

    The instruction address and control signals are compressed with

    a slice compression approach (to be explained shortly). On the

    other hand, the data address is recorded by simply removing the

    lea din g z er os. T h e H T M su p po rts a l imi te d le vel o f t ra c e abstrac-

    tion b y r e mo vin g bus si gn als th at ar e in I D L E or B U S Y stat e. The

    AMBA navig ator [ 4] t r a ce s al l A H B b us sign als wi th out compres-

    sion. In the bus transfer mode, it also has a limited level o f trace

    abstraction by re m o vin g bus sig n als whi ch ar e in I D L E , B US Y, or

    non-ready state. The AHBTRACE in GRLIB IP library [5] cap-

    tures the AMBA AHB signals in the uncompressed form. In ad-

    dition, it does not have trace abstraction ability.

    There are many research works related to the bus signal com-

    pression. We characterize the bus signals into three categories:

    program address, data address/data and control signals. We then

    review appropriate compression techniques for each category.

    For program addresses , since they are mostly sequential, a

    straightforward way is to discard the continuous instruction ad-

    dresses and retain only the disc o nt inu ous ones, so called branch/

    target filtering. This approach has been used in some commer-

    cial tracers, such as the TC1775 trace module in TriCore [6]

    and ARMs Embedded Trace Macrocell (ETM) [7]. The hard-

    ware overhead of these works is usually small since the filtering

    m e c ha nis m is simple to be impl e m e nte d in hardware. The effec-

    tiveness of these techniques, however, is mainly limited by the

    average basic block size, which is roughly around four or five

    instructions per basic block [7], [8]. Other technique such as the

    slice compression approach [3] targets at the spatial locality of

    the program address. This approach partitions a binary data into

    several slices and then records all the slices of the first data and

    then only part of the slices of the succeedin