intel process technology gaps june 2003 intel confidential paula goldschmidt ie- sbd mgr

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Intel Intel Process Technology Process Technology Gaps Gaps June 2003 June 2003 Intel Confidential Paula Paula Goldschmidt Goldschmidt IE- SBD Mgr. IE- SBD Mgr.

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Page 1: Intel Process Technology Gaps June 2003 Intel Confidential Paula Goldschmidt IE- SBD Mgr

Intel Intel Process Technology Process Technology

GapsGapsJune 2003June 2003

Intel Confidential

Paula GoldschmidtPaula GoldschmidtIE- SBD Mgr.IE- SBD Mgr.

Page 2: Intel Process Technology Gaps June 2003 Intel Confidential Paula Goldschmidt IE- SBD Mgr

Process Manufacturing -Technology Process Manufacturing -Technology Development Key IssuesDevelopment Key Issues

•Technology scaling difficulty increasing• New materials/architectures required vs. optional • More complex core technologies (ie trigate

transistors)• Maintain 2 year process development cycle • Increasing levels of process and device integration

•External constraints and competition increasing

• Declining ASP’s even though capital costs are increasing

• Growing competition • Keep One Generation Ahead Leadership

Page 3: Intel Process Technology Gaps June 2003 Intel Confidential Paula Goldschmidt IE- SBD Mgr

LITHOGRAPHYLITHOGRAPHY

IS THE MAJOR CHALLENGEIS THE MAJOR CHALLENGE

Page 4: Intel Process Technology Gaps June 2003 Intel Confidential Paula Goldschmidt IE- SBD Mgr

Litho Taxonomy

Lenses manufacturer

Lenses manufacturer

MaskRET,

Inspection,Software

Light Sources

Scanners

Optics/LensElements

Optical Materials

ChemicalsResists

Tracks

EUV capabilityEUV capability

Materials for lenses Manufacturing

Materials for lenses Manufacturing

Track Manuf.

Track Manuf.

Mask manuf.Mask RepairInspection capab.Mask writing SW

Mask manuf.Mask RepairInspection capab.Mask writing SW

Source – VLSI Research Feb 2003, First Call, Company websites

New resistsNew resists

EUV light sources manufacturers

EUV light sources manufacturers

Page 5: Intel Process Technology Gaps June 2003 Intel Confidential Paula Goldschmidt IE- SBD Mgr

IntelIntelFocused on Silicon Focused on Silicon

TechnologyTechnology

Merging Merging

Computing and CommunicationsComputing and Communications

Page 6: Intel Process Technology Gaps June 2003 Intel Confidential Paula Goldschmidt IE- SBD Mgr

Realizing The VisionRealizing The Vision

WirelessWireless

ExcellenceExcellencein in

Silicon ResearchSilicon ResearchLogicLogic

OpticalOptical

BiologicalBiological SensorsSensors

FluidicsFluidics

MechanicalMechanical

MemoryMemory

Page 7: Intel Process Technology Gaps June 2003 Intel Confidential Paula Goldschmidt IE- SBD Mgr

Intel I/E-SBD Collaboration Objectives:: • Enable One Generation Ahead (OGA) through

Collaboration:• Collaborate with Academic Research For Early engagement

in Process/Tech development.• Time and IP advantage.• Improved supplier execution.• Limited financial downside risk.• Price and royalty benefits of supply.

• Collaborate with Start-up/Spin-off companies:• Demonstrate enabling technology to fill Next technologies

roadmap gaps• Disruptive technologies to create roadmap options

Intel Capital TeamIntel Investment body to enable technologies availability

Page 8: Intel Process Technology Gaps June 2003 Intel Confidential Paula Goldschmidt IE- SBD Mgr

Silicon Technology Gaps

– Extend Moore’s Law. Silicon base, varied toppings with new materials and devicesExtend Moore’s Law. Silicon base, varied toppings with new materials and devices

– Develop more productive technologyDevelop more productive technology

– Low power/high speed devicesLow power/high speed devices

– Continue to introduce a new technology generation every two yearsContinue to introduce a new technology generation every two years

Page 9: Intel Process Technology Gaps June 2003 Intel Confidential Paula Goldschmidt IE- SBD Mgr

I/E-SBD areas of interestI/E-SBD areas of interest

Alternatives to Silicon

Nanotechnology

Process & FabTechnology

Assembly/TestSupply, Capacity& Components

Start Materials

TMG Process technology collaboration taxonomy

MEMS+

Page 10: Intel Process Technology Gaps June 2003 Intel Confidential Paula Goldschmidt IE- SBD Mgr

Potential Areas of InterestPotential Areas of Interest

In Si Technologies : 3-5 yrs to MarketIn Si Technologies : 3-5 yrs to Market Transistor PerformanceTransistor Performance

– High KHigh K– Low KLow K– InterconnectsInterconnects– StructuresStructures

Litho EUVLitho EUV– Masks: manufacturing, cleaning, inspectionMasks: manufacturing, cleaning, inspection

MemoriesMemories– New MaterialsNew Materials– New StructuresNew Structures

NanotechnologiesNanotechnologies– Application Technologies/Integration into productsApplication Technologies/Integration into products

Page 11: Intel Process Technology Gaps June 2003 Intel Confidential Paula Goldschmidt IE- SBD Mgr

MEMSMEMSPotential Areas of InterestPotential Areas of Interest

Communication DevicesCommunication Devices– Performance Performance – ReliabilityReliability

MEMS packaging MEMS packaging – Hermetic packagingHermetic packaging

Page 12: Intel Process Technology Gaps June 2003 Intel Confidential Paula Goldschmidt IE- SBD Mgr

How to contact usHow to contact us Send a Abstract of relevant projects to:Send a Abstract of relevant projects to:

– for Assembly/Test & MEMS for Assembly/Test & MEMS [email protected]@Intel.com

– for Litho/Yield/Defects & Clean roomfor Litho/Yield/Defects & Clean room [email protected]@Intel.com

– for Fab & Nanotechnologiesfor Fab & Nanotechnologies [email protected]@Intel.com

–For InvestmentsFor Investments [email protected]@Intel.com

Page 13: Intel Process Technology Gaps June 2003 Intel Confidential Paula Goldschmidt IE- SBD Mgr

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