ieee transactions on power electronics, vol. 33, no. 5...

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 33, NO. 5, MAY 2018 3791

A PWM LLC Type Resonant Converter Adapted toWide Output Range in PEV Charging Applications

Haoyu Wang , Member, IEEE, and Zhiqing Li, Student Member, IEEE

Abstract—In conventional LLC-based plug-in electric vehicle(PEV) onboard chargers, the battery pack voltage varies in a widerange with the change of state of charge. This makes it difficultto optimally design the pulse frequency modulated LLC resonantconverter. Besides, the voltage regulation of the LLC converter ishighly dependent on the load conditions. In this paper, a modi-fied pulse width modulated (PWM) LLC type resonant topology(PWM-LLC) is proposed and investigated in PEV charging appli-cations. The switching frequency of the primary LLC network isconstant and equal to the resonant frequency. The voltage regula-tion is achieved by modulating the duty cycle of the secondary sideauxiliary MOSFET. Compared with the conventional LLC topology,the proposed topology shrinks the magnetic component size andachieves a wide and fixed voltage gain range independent of loadconditions. Meanwhile, zero-voltage-switching and zero-current-switching are realized among all MOSFETs and diodes, respec-tively. A 100-kHz, 1-kW converter prototype, generating 250–420 Voutput from the 390-V dc link, is designed and tested to verify theproof of concept. The prototype demonstrates 96.7% peak effi-ciency and robust performance over wide voltage and load ranges.

Index Terms—Fixed frequency, LLC, onboard charging, pulsewidth modulated (PWM), zero-current-switching (ZCS), zero-voltage-switching (ZVS).

I. INTRODUCTION

A TYPICAL plug-in electric vehicle (PEV) onboard chargerconsists of two stages: 1) the first stage ac/dc converter

for rectification and power factor correction (PFC), and 2) thesecond stage dc/dc converter for voltage/current regulation andgalvanic isolation [1]–[5]. Fig. 1 shows the diagram of a typicaltwo stage LLC based PEV onboard charger. An LLC resonanttopology has some attractive features, such as: 1) simple struc-ture, 2) wide zero-voltage-switching (ZVS) range for MOSFETsand zero-current-switching (ZCS) range for power diodes, and3) reduced electromagnetic interferences [6]–[12]. Therefore, itis considered as a good candidate to be deployed in the secondstage dc/dc converter of the PEV onboard chargers [13]–[17].

Manuscript received January 23, 2017; revised April 21, 2017; accepted June2, 2017. Date of publication June 8, 2017; date of current version February 1,2018. This work was supported in part by the National Natural Science Foun-dation of China under Grant 51607113, and in part by the Shanghai SailingProgram under Grant 16YF1407600. Recommended for publication by Asso-ciate Editor Mehdi Ferdowsi. (Corresponding Author: Haoyu Wang.)

The authors are with the Chinese Academy of Sciences, Shanghai In-stitute of Microsystem and Information Technology, University of ChineseAcademy of Sciences, Shanghai 200050, China, and also with the Power Elec-tronics and Renewable Energies Laboratory, School of Information Scienceand Technology, ShanghaiTech University, Shanghai 201210, China (e-mail:[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2017.2713815

Fig. 1. Diagram of a typical two stage LLC based PEV onboard charger.

Fig. 2. DC voltage characteristics of LLC topology adapted to a wide outputvoltage range.

However, in order to be adapted to the wide voltage variationrange and various load conditions, the switching frequency (fs)of LLC converter must swing in a wide range and deviates fromresonant frequency (fr ). Fig. 2 illustrates the dc voltage gainof an LLC converter adapted to the wide output voltage range.As shown, the desired output voltage window [Vmin , Vmax] onthe gain axis is mapped to a wide switching frequency range[fmin , fmax] in the frequency axis.

Generally, when fs deviates from fr , the conversion effi-ciency degrades fast with the increase of this deviation [12],[13], [18]. Moreover, to achieve a low voltage gain, fs needs tobe tuned to be considerably higher than fr . This is demandingfor both the gate drivers and the power devices. Additionally,to achieve a high voltage gain, fs needs to be lower than fr .The lower bound of fs is the critical parameter in designingthe transformer. Low fs corresponds to large core size and lowpower density. Therefore, it is very difficult to optimally de-sign the LLC converter adapted to wide voltage gain range withfrequency modulation.

Different alternative techniques to narrow down the switchingfrequency range of the LLC topology were investigated in [8],[16], and [19]–[27]. In [8], the LLC topology is integrated witha two-phase interleaved boost circuit. Fixed-frequency pulse

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3792 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 33, NO. 5, MAY 2018

width modulation (PWM) control is adopted on the primaryfull-bridge inverter to achieve output voltage regulation; fs

is constant and equal to fr . However, the added two bulkyinductors and the electrolytic capacitor degrade the systempower density. In [19], one leg of the full-bridge rectifyingdiodes in the conventional LLC converter is replaced withsynchronous rectifier (SR). When the input voltage is lowerthan the preset boundary, the SR switches are controlled withphase-shifted gate signals to obtain a higher voltage conversionratio. However, large phase shift (PS) corresponds to longtime interval when the secondary side of the LLC converteris shorted. Therefore, the PS is strictly constrained and thisphenomenon increases the circuit instability. In [20], the firststage ac/dc PFC converter of the LLC based PEV charger isdesigned with a variable output dc link voltage. This dc linkvoltage linearly follows the battery pack voltage. Therefore, thefs variation of the LLC converter is remarkably narrowed down.However, the PFC stage must have a wide output voltage range,where the boost topology is no longer a suitable solution. Thisincreases the circuit and control complexity in the PFC stage. In[21]–[23], burst mode (BM) strategy is employed in light andno-load conditions to achieve a wide output range. However,a high-frequency oscillation exists during the OFF state andintroduces electromagnetic interference (EMI) issues. Toalleviate this problem, pulse frequency modulated (PFM) andPS control are integrated in [16]. However, with the increase ofPS angle, the circulating current increases. Moreover, the ratiobetween the resonant inductor (Lr ) and magnetizing inductor(Lm ) is set as unity. This means integrated magnetic componentis infeasible and the power density degrades. Additionally,the circulating current and conduction losses increase. In [24],hold-up compensation mode (HCM) is proposed. The LLC con-verter achieves a higher gain using the auxiliary compensationcircuit. However, the additional winding and semiconductorsdo not operate in the nominal state. Hence, their utilization rateis relatively low. In [25], asymmetric pulse width modulation(APWM) of the primary switching network is adopted to boostthe conversion ratio. While, its upper bound voltage gain is stilllimited and highly dependent on both the load and the resonanttank parameters. Besides, the utilization rate of the secondarydiodes is rather low. This means high current stresses in circuitcomponents. In [26] and [27], symmetric pulse width modula-tion (SPWM) of the primary switching network is proposed toextend the output range. However, its voltage conversion ratiois constrained by duty ratio D. The upper boundary of D is 0.5and its lower boundary is defined by the full ZVS requirements.

Generally, in [16], [19], and [21]–[27], different extra oper-ation modes like SR, BM, PS, HCM, APWM, and SPWM areproposed to corporate with PFM control. These extra operationmodes extend the voltage regulation range with narrow switch-ing frequency. While, among them, BM introduces serious EMIproblem; the conversion ratio of SR, APWM, and SPWM arestill limited and affected by the load conditions; auxiliary com-ponents in HCM are inefficient; PS requires an external resonantinductor and a small Lm , which leads to high conduction losses.Usually, these extra operation modes are suitable for just fewphases in the battery charging profile. Hence, PFM control is

Fig. 3. Schematic of the proposed PWM LLC topology.

still unavoidable. This means certain switching frequency rangestill exists. Meanwhile, the control and design complexity areincreased. Moreover, the transition between different controlmodes slows down the dynamic response.

In this paper, a novel pulse width controlled LLC topol-ogy is proposed. The proposed converter adopts a modifiedvoltage doubler architecture on the secondary-side rectifica-tion stage. The output voltage of the converter is regulated bythe duty cycle of the auxiliary MOSFET on the secondary side.Therefore, the main LLC topology can operate at its resonantfrequency. This proposed converter demonstrates benefits in-cluding: 1) optimum operation of the primary LLC network;2) soft switching of all semiconductor devices; 3) wide andfixed voltage gain range independent of load conditions; and 4)reduced transformer size. In comparison with [28], the improve-ments mainly lie in these four aspects: 1) the secondary sideinductor is eliminated; 2) the switch pattern of S5 is modified toensure better ZVS performance; 3) experiments are conductedand experimental results are added; and 4) a more accuratemodeling and analysis methodology are proposed.

This paper is organized as follows. Section II gives a gen-eral introduction to the proposed PWM-LLC dc/dc converter;a detailed circuit modeling and analysis are also presented. InSection III, the converter features and performances are dis-cussed. Additionally, the comparisons with the conventionalLLC converter are demonstrated. The controller design is pro-vided in Section IV. Section V presents the experimental resultsand conclusions are drawn in Section VI.

II. PROPOSED PWM LLC TYPE DC/DC CONVERTER

A. Topology Description

The schematic of the proposed PWM-LLC resonant converteris illustrated in Fig. 3. Co2 and Co1 are two large filter capaci-tors with ignorable ripple voltage. This topology is derived fromthe full-bridge LLC topology with voltage doubler rectificationstage. Compared with the conventional voltage doubler rectifi-cation circuit, an auxiliary diode-MOSFET bridge (D3 and S5)is added on the secondary side. The primary switching networkalways operates at fr . By actively controlling the duty ratio (D)of S5 , the output voltage changes accordingly.

B. Operation Principle

In the proposed converter, the primary side full-bridge func-tions as a constant frequency square wave generator. The upperand lower power MOSFETs are turned ON and OFF complemen-tarily with certain deadband (tdead ). The switching frequency is

WANG AND LI: PWM LLC TYPE RESONANT CONVERTER ADAPTED TO WIDE OUTPUT RANGE IN PEV CHARGING APPLICATIONS 3793

Fig. 4. The switch pattern of the actively controlled MOSFETs.

Fig. 5. Converter steady state waveforms.

fixed and equal to fr ,

fr =1

2π√

LrCr

. (1)

The switching pattern of MOSFETs S1 − S5 , is plotted inFig. 4. The switching frequency of S5 is also equal to fr . On thesecondary side, a slight PS (tdelay ) is added between the turningON of S5 and the deadband. This ensures that the body diode ofS5 conducts prior to the turning-ON of MOSFET channel.

Typically, the duty cycle of vgs5 , D, should be constrainedwithin (0.5, 1]. This is mainly due to two facts associated withD < = 0.5: 1) the charge balance of Co1 cannot be satisfied;and 2) the output will be a constant voltage.

The critical steady state waveforms of the proposed converterare explicated in Fig. 5. The steady state operation during eachswitching period can be divided into eight operation modes ineach switching period (Ts). The equivalent circuits in thoseoperation modes are illustrated in Fig. 6.

Mode I [t0 , t1): Before t0 , S1,4 are ON and the secondaryside of the transformer is open-circuited. Mode I begins at t0when S1,4 are turned OFF. It should be noted that Mode I iswithin the deadband of S1−4 . During this short transition, thevoltage across Cr (vC r ) can be seen as constant. vab decreasesfrom VDC and the voltage across the transformer primary side(vtx ) decreases simultaneously. ir charges the output capacitors

Fig. 6. Converter equivalent circuits. (a) Mode I, t0 ≤ t < t1 . (b) Mode II,t1 ≤ t < t2 . (c) Mode III, t2 ≤ t < t3 . (d) Mode IV, t3 ≤ t < t4 .(e) Mode V, t4 ≤ t < t5 . (f) Mode VI, t5 ≤ t < t6 . (g) Mode VII,t6 ≤ t < t7 . (h) Mode VIII, t7 ≤ t < t8 .

(Coss) of S2,3 and discharges Coss of S1,4 . Since Coss is rela-tively small, ir can be seen as constant and, vab and vtx decreaselinearly

vab(t) = VDC − (t − t0) ir (t0)Coss

(2)

vtx(t) =[vab(t) − VC r (t0)

] Lm

Lm + Lr. (3)


At t1 , vtx decreases to zero, which marks the end of thismode.

Mode II [t1 , t2): As Mode II begins, vab and vtx continue todecrease. Hence, vtx becomes negative. Here the small junctioncapacitor of D2 is ignored. According to Kirchhoff’s VoltageLaw, the decreasing and negative vtx forces D2 to be forwardbiased; the output capacitor of S5 (Cs5) is discharged. In thistime interval, Lm can be considered as a current source; Cr andCo2 are regarded as voltage sources. Thus, ir , is , vab , and vds5are given as follows:

KC = n2 Coss

Cs5(4)

ωsw =1√(

Lr Co s sKC +1

) (5)

ir (t) =ILm

(t1)KC +1

[KC + sin

(ωsw (t − t1) +

π

2

)](6)

is(t) =nILm

(t1)KC + 1

[−1 + sin

(ωsw (t − t1) +

π

2

)](7)

vab(t) = VCr(t1) −

∫ t

t1ir (t) dt

Coss(8)

vds5(t) = VC o2 +

∫ t

t1is (t)dt

Cs5. (9)

The polarities of the circuit currents and voltages are markedon Fig. 3. In Mode II, vab decreases to –VDC , and vds5 decreasesto zero. Then, S2,3 are turned ON with ZVS and the body diodeof S5 conducts.

Mode III [t2 , t3): At t2 , S5 is turned ON. The conduction ofS ′

5 body diode in the previous mode creates the ZVS conditionfor the turning ON of S5 . On the secondary side, D2 and S5both conduct. Cr and Lr resonate and the resonant frequency isequal to fr . Hence, vC r and ir can be expressed as follows:

ωr =1√

LrCr

Zr =√

Lr

Cr(10)

vCr(t) = nVCo2 − VDC + VCr 3 sin [ωr (t − t2) + α3 ] (11)

ir (t) =VCr 3

Zrcos [ωr (t − t2) + α3 ] (12)

iLm(t) = ILm 3 − nVCo2

Lm(t − t2) (13)

where VC r3 is the magnitude of the sinusoidal part of vcr , α3 isthe initial phase, and ILm3 is the initial current through Lm . Att3 , is crosses zero, which marks the end of this mode.

Mode IV [t3 , t4): is stays zero after t3 and the circuit operationenters into Mode IV. Thus, the transformer secondary side isopen-circuited. Lm joins the resonance with Lr and Cr . irequals to iLm and varies sinusoidally. vC r and ir are derived as

follows:

vCr(t) = − VDC + VCr 4 sin

[ωr (t − t3)/

√KL + α4

](14)

ir (t) = iLm(t) =

VCr 4

Zr

√KL

cos[ωr (t − t3)/

√KL + α4

]

(15)

where KL is the inductance ratio and is defined as (Lm +Lr )/Lr ; VC r4 is the magnitude of the sinusoidal part of vcr ; α4is the initial phase.

Mode V [t4 , t5): Mode V is within the deadband of S1−4 andthis circuit operation is similar to that in Mode I. In this mode,vab increases linearly as

vab(t) = −VDC − (t − t4) ir (t4)Coss

. (16)

At t5 , the deadband is over and vab increases to VDC . Thedrain to source voltages of S1,4 are discharged to zero beforechannels are turned on in the next mode. Therefore, the turningon of S1,4 are ZVS.

Mode VI [t5 , t6): At t5 , S1,4 are turned ON and Mode VIbegins. In this mode, vab equal to VDC . is is positive and D1conducts as illustrated in Fig. 6(f). vC r , ir , and iLm can beobtained as follows:

vCr(t)= − nVCo1 +VDC + VCr 6 sin

[ωr (t − t5) +α6

](17)

ir (t) =VCr 6

Zrcos

[ωr (t − t5) + α6

](18)

iLm(t) = ILm 6 +

nVCo1

Lm(t − t5) (19)

where VC r6 is the magnitude of the sinusoidal part of vcr , andα6 is the initial phase.

Mode VII [t6 , t7): S5 is turned OFF at t6 and Mode VII starts.Since the inductor current is continuous, the current path isswitched from S5 to D3 . Hence, Vbat is directly connected tothe secondary side of the transformer. Since Vbat is much largerthan VC o1 , it induces is to decrease. Mode VII ends when isreaches zero. vC r , ir , and iLm are expressed as follows:

vCr(t) = − nVbat + VDC + VCr 7 sin

[ωr (t − t6) + α7

]

(20)

ir (t) =VCr 7

Zrcos

[ωr (t − t6) + α7

](21)

iLm(t) = ILm 7 +

nVbat

Lm(t − t6) (22)

where VC r7 is the magnitude of the sinusoidal part of vcr , andα7 is the initial phase. It should be noted that the large voltagedecrease on the transformer secondary side (nVbat − nVC o1)is dropped on Lr . This forces ir to decrease fast.

Mode VIII [t7 , t8): At t7 , is reaches zero. Since S1,4 arestill ON, is remains zero. Thus, all the semiconductors on thesecondary side are OFF. Mode VIII ends when S1,4 are turnedOFF, which marks the start of next switching period. vC r and ir


are expressed as follows:

vCr(t) = VDC + VCr 8 sin

[ωr (t − t7)/

√KL + α8

](23)

ir (t) = iLm(t) =

VCr 8

Zr

√KL

cos[ωr (t − t7)/

√KL + α8

]

(24)

where VC r8 is the magnitude of the sinusoidal part of vcr , andα8 is the initial phase.

III. CHARACTERISTICS OF THE PROPOSED CONVERTER

A. Voltage Gain and Capacitor (Co2) Voltage

There are total eight operation modes in each switching pe-riod. The time durations of modes I, II, and V (tdead , tdelay ) aremuch smaller than Ts and ignored to simplify the analysis. Thenormalized voltage gain is defined as

G =nVbat

VDC. (25)

The capacitor voltages and inductor currents are always con-tinuous between any adjacent stages. Here X and Y denote twoadjacent stages, while s and e denote the beginning and end ofthe specific stage. Thus

vCr(Xe) = vCr

(Ys) (26)

ir (Xe) = ir (Ys) (27)

iLm(Xe) = iLm

(Ys) (28)

ir and iLm are equal at the end of modes III and VII. Thisprovides additional constraints, which are defined as follows:

ir (IIIe) = iLm(IIIe) (29)

ir (VIIe) = iLm(VIIe) (30)

where IIIe denotes the end of Mode III, and VIIIe denotes theend of Mode VIII. Besides, in steady state, the final and initialvalues of ir , iLm , and vC r are equal over one switching period.Therefore

vCr(IIIs) = vCr

(VIIIe) (31)

ir (IIIs) = ir (VIIIe) (32)

iLm(IIIs) = iLm

(VIIIe) (33)

where IIIs denotes the beginning of Mode III, while VIIIedenotes the end of Mode VIII.

Since the output current is zero in modes IV and VIII, onlymodes III, VI, and VII are involved in the energy delivery.Ignoring the power losses and applying Kirchhoff’s Circuit Law,The relationship between circuit parameters and output powercan be derived as follows:

TsPo

GVDC=

∫ VIe

VIs

[ir (t) − iLm

(t)]dt

+∫ VIIe

VIIs

[ir (t) − iLm

(t)]dt. (34)

Fig. 7. Voltage gain versus equivalent RL and D.

Additionally, according to the charge balance of Co1 and Co2 ,the averages of is in modes III and VI should be equal

∫ IIIe

IIIs

[ir (t) − iLm

(t)]dt =

∫ VIe

VIs

[ir (t) − iLm

(t)]dt. (35)

Combing (10)–(15), and (17)–(35), the relationship betweenD and the normalized voltage gain can be derived. These equa-tions are transcendental, and the numerical solutions can besolved in MATLAB. Fig. 7 plots the curves of the normalizedvoltage gain versus the duty cycle under different effective loadresistances (RL ).

It is worth mentioning that the voltage across Co2 , VCo2 is aweak function of both the effective load resistance and the dutycycle. Indeed, VCo2 is always close to the normalized voltageVnorm , which is defined as

Vnorm =VDC

n. (36)

This can be clearly observed from Fig. 8, which provides thecurves of VCo2/Vnorm versus the duty cycle under different loadconditions. According to Fig. 8, VCo2 always stays in the vicin-ity of Vnorm and demonstrates very good load independencefeature. Thus, VCo2 can be approximated as a constant (Vnorm ).This means that the voltage stresses of auxiliary diode-MOSFET

bridge (D3 and S5) are both Vnorm , which is much lower thanthe output voltage. Therefore, D3 and S5 with low voltage ratingcan be selected to reduce conduction losses.

The voltage regulation of the PWM-LLC converter isachieved by varying D. When D is unity, the PWM-LLC con-verter is equivalent to the conventional LLC topology with volt-age doubler rectifier. Hence, the maximum normalized voltagegain is

Gmax = 2. (37)

When D decreases, the current through S5 decreases. WhenD is less than 0.5, only S ′

5 body diode conducts and the positive


Fig. 8. VCo2 /Vnorm versus D under different effective load conditions.

part of is5 is eliminated. While (35) should be satisfied to ensurethe charge balance of Co1 and Co2 . This requires the drain tosource channel conduction of S5 . Hence, D should always belarger than 0.5. The output voltage is equal to the sum of VCo2and VCo1 . VCo1 decreases to zero when D is very close to 0.5.Hence, the minimum output voltage is equal to VCo2

Gmin =nVnorm

VDC≈ 1. (38)

In summary, D should be constrained in the range of(0.5, 1], while the normalized voltage gain ranges from 1 to2 independent on the load conditions. This demonstrates goodPWM feature.

B. MOSFET ZVS

During the deadband, ir is equal to iLm . This current is evenlysplit among S1−4 to charge or discharge their output capacitors.According to (7), the current to discharge Cs5 before the turningON of S5 is also determined by iLm . Therefore, sufficiently largeiLm during S1−5

′s turning ON transitions is required to ensurethe ZVS of all the power MOSFETs.

Typically, the MOSFETs are prone to lose the ZVS featureat light load conditions. Thus, zero load ZVS is most critical toensure the ZVS over the full load range. Zero load condition cor-responds to the case when the secondary side of transformer isopen-circuited. The switching network directly drives the reso-nant tank (Cr , Lr , and Lm ). The square-wave output generatedfrom the switching network can be expressed by its Fourierseries

vab (t) =4π

VDC

∑k=1,3,5,...

1k

sin (kωst) . (39)

The input impendence of the resonant tank network is

Z (jω) = jω (Lm + Lr ) +1

jωCr. (40)

Fig. 9. ZVS waveforms during the turning ON transition of S2 ,3 ,5 .

Accordingly, iLm can be obtained as

iLm (t) =4π

VDC

∑k=1,3,5,...

1k|Z (jkωs) | sin (kωst − ϕk )

(41)ϕk is defined as

ϕk = arg[Z (jkωs)

]≈ π

2. (42)

Hence, iLm at t0 , t1 , and t4 can be derived as follows:

iLm (t0) = iLm (t1) =4π

VDC

∑k=1,3,5,...

1k|Z (jkωs) | (43)

iLm (t4) =4π

VDC

∑k=1,3,5,...

−1k|Z (jkωs) | . (44)

When k � 3, the impendence of Cr is much smaller than thatof Lr + Lm and can be neglected. Hence

|Z (jω) | ≈ ωsLm +∑

k=3,5,...

kωs (Lm + Lr ) . (45)

Substituting (45) to (43) and (44)

|iLm

(t0 ,1,4

) | =4VDC

πωs

[1

Lm+

(π2

8− 1

)1

(Lm + Lr )

].

(46)Modes I and II in Fig. 5 describe the turning ON transients of

S2,3,5 and are zoomed in and replotted in Fig. 9. As shown, at t1 ,vtx decreases to zero; and vab decreases to vC r (t1). After t1 andbefore t2 , vab decreases to −VDC ; and vds5 decreases to zero.Based on (42), vC r (t1) is equal to zero at zero load condition.Accordingly, the duration of Mode I (denoted as 0.5tdead ) canbe derived as

tdead =πωsCoss

2[

1Lm

+(

π 2

8 − 1)

1(Lm +Lr )

] . (47)

In Mode II, Coss of S2,3 and Cs5 of S5 are discharged simul-taneously. tab is the time required for vab (t) to be discharged to


–VDC ; while ts5 is the time required for vds5(t) be dischargedto zero. t2 – t1 is denoted as tdelay as shown in Fig. 4. tdelayshould be larger than both ts5 and tab . This ensures that thebody diodes of S2,3,5 conduct prior to the turning-ON of theMOSFET channels. Combining (4)–(9) and (36), ts5 and tab canbe solved via (48) and (49)

1KC + 1

|iLm (t1) |[KC tab − 1

ωswcos

(ωsw tab +

π

2

)]=VDC

(48)

n

KC + 1|iLm (t1) |

[ts5 +

1ωsw

cos(ωsw ts5 +

π

2

)]=

VDC

n.

(49)With the preset transformer turns ratio and fr , the practical

design procedures of Lm , Lr , tdead , tdealy are listed as followed.First, set tdead according to fr .Second, loose the transformer coupling to increase its leakage

inductance, Lr . The increased Lr leads to a smoother ir and areduced root-mean-square (RMS) value. It should also be notedwhen designing Lr , the standard capacitance value of Cr shouldalso be considered.

Third, select Lm according to (47).Fourth, calculate ts5 and tab by combining (46), (48), and

(49). tdealy is determined by the maximum of ts5 and tab .

C. Diode ZCS

In the proposed topology, three power diodes are employedon the secondary side. According to Section II-B, di/dt of D1−3during the turning OFF transitions can be expressed as follows:

di

dt

∣∣∣∣D1 , 3

= − n

[vCr

(t7) + nVbat − VDC

Lr+

nVbat

Lm

](50)

di

dt

∣∣∣∣D2

= n

[−vCr(t2)

Lr+

VDC

Lm

]. (51)

As shown, di/dt of D1−3 increases with the increase of boththe power level and the output voltage. To estimate the maximumdi/dt, the maximum output power is denoted as Pom , and themaximum output voltage is denoted as Vbatm . First harmonicapproximation is adopted to derive vC r , thus

max

∣∣∣∣∣di

dt

∣∣∣∣D1 , 3

∣∣∣∣∣≤n

(πPo m

2VD C

1ωCr

+ nVbatm − VDC

Lr+

nVbatm

Lm

)

(52)

max

∣∣∣∣∣di

dt

∣∣∣∣D2

∣∣∣∣∣ ≤ n

(πPo m

2VD C

1ωCr

Lr+

VDC

Lm

). (53)

It should be noted that the typical value of πPom /(2VDC ×ωCr ) is about one tenth of VDC . According to (52) and (53),all turning OFF di/dt are effectively mitigated by Lr and Lm .Hence, the turning OFF of D1−3 can be considered as ZCS, andthe diode reverse recovery losses are ignorable.

Fig. 10. Topology extension with PWM+PFM hybrid control. (a) D4 is addedon the secondary side. (b) Its equivalent circuit with PFM control.

D. Extended Voltage Regulation Range With PWM+PFMHybrid Control

In this paper, the PWM-LLC converter works at fixed resonantfrequency. This facilitates the optimal operation of the LLCtank. By actively controlling D, the normalized voltage gainchanges accordingly. As shown in Fig. 7, the voltage regulationrange of the proposed converter is large and independent of theload conditions. It can fulfill the working conditions of typicalonboard chargers. However, for ultrawide output applications,frequency modulation can be integrated with the PWM to furtherexpand the output range.

When PWM+PFM hybrid control is adopted, the topologystructure can be slightly modified to achieve a more stable andbalanced circuit operation. Fig. 10(a) illustrates this modifiedstructure, where D4 is added on the secondary side. When D> 0.5, D4 is reverse biased. It is equivalent to the secondaryside in Fig. 3. PWM control is enabled. When S5 is alwaysOFF, frequency modulation is activated. It should be noted thereis no current passing through D5 , which is the body diode ofS5 . This is due to the charge balance of Co1 , Co2 , and thecircuit symmetry feature. The equivalent circuit is plotted inFig. 10(b) and works as a full-bridge rectifier. Increasing fs canfurther lower the voltage gain. Based on fundamental harmonicapproximation analysis, the line to output transfer function isobtained

G (s) =∣∣∣∣

sLm //Rac

sLr + (sCr )−1 + sLm //Rac

∣∣∣∣ (54)

where Rac is the equivalent load resistance and defined as

Rac =8n2RL

π2 . (55)

E. Reduced Magnetic Component Size

In the proposed PWM-LLC converter, the magnetic com-ponent size can be reduced. This is mainly due to two rea-sons: 1) Lr and Lm can be integrated into one single magneticcore; 2) in comparison with conventional LLC converter, themagnetic core size and turns number are reduced.

The maximum core magnetic flux density variation (ΔB)is proportional to the maximum volt-second applied to thetransformer primary side. Regarding the conventional LLCtopology, ΔB reaches its peak value when fs is at its lowerboundary and the highest output voltage is achieved. There-fore, in an LLC converter with voltage doubler rectifier, to


TABLE IDESIGN PARAMETERS OF THE PROTOTYPES

Components PWM-LLC LLC

Resonant frequency (fr ) 100 kHz 100 kHzResonant inductor (Lr ) 28.1 μH 28.1 μHMagnetizing inductor (Lm ) 300 μH 150 μHResonant capacitor (Cr ) 90 nF 90 nFTurns ratio (np : ns ) 27:15 24:10Filter capacitors (Co1 , Co2 ) 120 μF 120 μFHigh voltage MOSFETs (S1−4 ) IRFP460 IRFP460High voltage diodes (D1−2 ) C3D10060A C3D10060ALow voltage MOSFETs (S5 ) FQP22N30Low voltage diode (D3 ) MBR40250G

avoid the magnetic saturation, the following equation shouldbe satisfied

BsnpAe >12

[nVbatm

2Tr + VDC (Ts − Tr )

](56)

where Bs is the core saturation flux density; np is the primaryturns numbers; Ae is the core cross-sectional area; Vbatm is themaximum output voltage; Tr and Ts are the resonance periodand switching period, respectively.

In the proposed PWM-LLC topology, the voltage acrossthe transformer is also clamped by the output voltage. WhenD = 1, ΔB reaches its peak value. Accordingly, the magneticsaturation restriction can be expressed as

BsnpAe >12

(nVbatm

2Tr

). (57)

Comparing (56) and (57), it can be concluded that the con-ventional LLC converter typically requires a larger Aenp thanthe proposed PWM-LLC converter. While large Ae and np cor-respond to a large magnetic component size.

F. Comparison With the Conventional LLC Converter

To evaluate the circuit performance, the losses and systemvolume comparisons between the proposed converter and theconventional LLC converter are conducted. The PWM-LLCconverter and the LLC converter are both designed with thesame voltage and power ranges. The dc link voltage is 390 V,and the output voltage varies from 250 to 420 V. The powerrating is selected to be 1 kW. The design parameters of the twoconverters are summarized in Table I.

In the LLC converter, the transformer turns ratio is 24:10.Hence, the output equals 325 V at its resonant frequency. Thetransformer turns ratio in the PWM-LLC converter is 27:15.Thus, the output voltage approximately is equal to 433 V atresonant frequency. In the conventional LLC converter, to ensurea full ZVS range from 50% load to 100% load, Lm is selectedto be 150 μF. While in the PWM-LLC converter, fs alwaysequal to fr . A much larger Lm (300 μF) can be used. Thishelps to further reduce the circulating currents. The voltageand current stresses of S1−4 and D1−2 in LLC and PWM-LLCconverter are similar, respectively. Hence, the same MOSFET

(IRFP460) and diode (C3D10060A) with identical on-resistance

TABLE IISIMULATION PERFORMANCE VERIFICATION

PWM-LLC Conventional LLC

Vo (V) 250 335 420 250 335 420Ir, rm s (A) 3.3 3.6 3.5 4.5 5.6 7.8Is, rm s (A) 7.6 7.1 5.6 8 7.2 6.8ΔB (T) 0.14 0.15 0.15 0.05 0.12 0.19Is5 , rm s (A) 3.2 5.6 5.7ID 3 , a v e (A) 3.3 1.3 0.1

Fig. 11. Power losses breakdown of two prototypes.

(Ron ) and diode forward voltage drop (VD ) are adopted. Thereverse voltages of D3 and S5 are clamped by VCo2 as definedin (36). Therefore, semiconductors with smaller Ron and VD

(FQP22N30, and MBR40250G) are used in the auxiliary switchleg in the proposed PWM-LLC converter.

1) Theoretical Loss Analysis: The full-load power losses ofthe LLC and PWM-LLC converters are compared at three im-portant benchmarks (Vo = 250 V, 335 V, and 420 V). In bothconverters, all the MOSFETs are turned ON with ZVS. Hence,the turning ON losses are zero. Also, there is neglectable switch-ing loss incurred during the MOSFET turn-OFF transition. Thisis because that substantial Coss holds the drain to source volt-age close to zero while the MOSFET turns OFF. Similarly, all thediodes are turned OFF with ZCS, the reverse recovery lossesare neglectable. In the theoretical loss estimation, driving lossesand conduction losses are calculated and the core losses areestimated based on ΔB, fs , core materials, and core volume.

The simulation results with different Vo at full load conditionare summarized in Table II, where Ir,rms is the RMS value ofir ; Is,rms is the RMS value of is ; Is5,rms is the RMS value ofis5 ; ID3 ,ave is the mean of iD3 ; and ΔB is the flux variation.

According to Table II, different power losses are analyzedand the data is plotted in Fig. 11. As shown, the conductionlosses of S1−4 , D1,2 and copper loss are smaller in the PWM-LLC converter than those in LLC converter, especially whenVo = 420 V. This is because that the PWM-LLC convertersalways operate at fr and a larger Lm can be used to ensure ZVSrange. In the PWM-LLC converter, ΔB is independent of outputvoltage. Accordingly, the core loss of the PWM-LLC converteris almost unchanged with the change of output voltage.

2) System Volume: In comparison with the conventionalLLC converter, an auxiliary (D3 , S5) bridge is added in the pro-posed topology. This slightly increases the system volume. Onthe other hand, according to the analysis in Part E, transformersize in the proposed topology is reduced. Fig. 12 describes the


Fig. 12. Critical volume differences in two prototypes.

Fig. 13. Digital control scheme in PEV battery charging applications.

volume comparison between two prototypes. It should be notedthat the volume of D3 − S5 bridge also includes the gate driverand heat sink. EE55 core is selected for the LLC converter,while EE42 core is selected in the PWM-LLC converter. Asshown, the total size of transformer and D3 − S5 bridge in thePWM-LLC converter is still smaller than the transformer vol-ume in the LLC converter. The other circuit components arethe same in both converters. Hence, the power density of theproposed PWM-LLC converter is higher than that of the con-ventional LLC converter.

IV. CONTROLLER DESIGN

The digital control scheme of the proposed converter is plot-ted in Fig. 13. As demonstrated, control of the circuit in PEVcharging applications can be implemented using a microcon-troller. On the primary side of the transformer, four MOSFETsare driven by two channel PWM signals issued by the micro-controller. No feedback is required to control the full-bridgeinverter. On the secondary side, the transducers sample the bat-tery charging current, charging voltage information and feed itto the microcontroller. While the Microcontroller Unit estimatesthe state of charge and selects the charging mode. In constantcurrent charging mode, the current loop controller is activated tomaintain a constant charging current. While in constant voltagecharging mode, a double closed-loop controller including innercurrent loop and outer voltage loop are activated to maintain aconstant charging voltage. In comparison with the conventionalfrequency modulated LLC topology, this adopted PWM control

Fig. 14. Waveforms of vds2 , vg s2 , ir , and is with D = 0.75, andRL = 175 Ω.

Fig. 15. Waveforms of vds1 , vg s1 , ir , and is with D = 0.75 andRL = 175 Ω.

Fig. 16. Waveforms of vds5 , vg s5 , is5 , and iD 3 with D = 0.75 andRL = 175 Ω.

scheme is much simpler. In the experiments, TMS320F28335from Texas Instruments, Dallas, TX, USA, is used as the digitalcontroller, to interface with the power board and to execute thedigital control algorithms.

V. EXPERIMENTAL RESULTS

Based on the proposed topology and the circuit analysis, a1-kW rated converter prototype is designed to charge a 250–420 V battery pack. This power level is close to typical Level Ionboard charging and is selected mainly to verify the proof ofconcept. The switching frequency is selected as 100 kHz. Theinput voltage is 390 VDC, which is the typical output voltage ofthe ac/dc PFC stage. In the experiments, the high voltage batterypack is emulated by resistive loads (RL ). The circuit parametersare shown in Table I.


Fig. 17. Waveforms of iD 1 and iD 2 with D = 0.75 and RL = 175 Ω.

Fig. 18. Closed-loop dynamic response (Vbat = 390 V, RL jumps from 300to 100 Ω).

Figs. 14–17 demonstrate the steady state voltage and currentwaveforms with D = 0.75 and RL = 175 Ω. As shown, thesewaveforms agree well with previous operation modes analysisgiven in Fig. 5. As illustrated in Figs. 14–16, S1,2,5 are all turnedON with ZVS. The operations of S3,4 are the same as that of S1,2 .Thus, it can be concluded that ZVS is achieved among all theMOSFETs.

Figs. 16 and 17 capture the current waveforms of D1−3 . Asshown, all the diodes are turned OFF with mitigated di/dt. Nodiode reverse recovery phenomenon can be observed. Thus,neglectable reverse recovery loss is associated with the diodeturning OFF. In Fig. 16, a small voltage oscillation exists in vds5right after the turn OFF of D3 . This is mainly due to the resonancebetween the semiconductor output capacitors and the inductors.This resonance is trivial and does not affect the normal circuitoperation. This trivial current oscillation can also be observedfrom the current waveforms in Figs. 14 and 15.

Fig. 18 illustrates the dynamic response of the prototype. Asshown, the converter responds fast with the step change of theload. The efficiency curves of the PWM-LLC converter andconventional LLC converter are plotted in Fig. 19. The systemefficiency is calculated by η = Po /(Pin + Paux). Where Po

is the output power, Pin is the input power, and Paux is thepower consumption of the auxiliary circuits. The experimentaldata is measured by a high-precision power analyzer (PPA4530from Newtons4th Ltd). It is shown that the PWM-LLC con-verter demonstrates higher efficiency than the LLC converter.In addition, the efficiency of the PWM-LLC converter decreasesmore slowly than that of the LLC converter with the decrease

Fig. 19. Measured efficiency versus the output power of with different outputvoltages.

of power level. The full load peak efficiency of the PWM-LLCconverter is 96.7%.

VI. CONCLUSION

In this paper, a PWM LLC type resonant converter is pro-posed for use in PEV onboard chargers. Voltage gain modula-tion is realized by the duty cycle of the secondary side auxiliaryMOSFET. The proposed converter demonstrates the benefits of1) wide voltage regulation range independent of load conditions;2) ZVS of all MOSFETs; 3) ZCS turning-OFF of the rectifica-tion diodes; 4) reduced circuit control complexity; 5) reducedtransformer size, and 6) high system efficiency. A 1-kW con-verter prototype, which corresponds to the power level of typicalLevel 1 charging, is built to verify its feasibility. The designedprototype demonstrates 96.7% peak efficiency at 100 kHz andgood voltage regulation performance. The proposed converteris not only useful for PEV battery charging application, but alsovalid for applications where a wide voltage gain range is desired.

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Haoyu Wang (S’12–M’14) received the bachelor’sdegree (Hons.) from Zhejiang University, Hangzhou,China, and the master’s and Ph.D. degrees both inelectrical engineering from the University of Mary-land, College Park, MD, USA.

He worked as a Design Engineer with GeneSiCSemiconductor Inc., Dulles, VA, USA, in summer2012. He is currently a Tenure Track Assistant Profes-sor in the School of Information Science and Technol-ogy, ShanghaiTech University, Shanghai, China. Hisresearch interests include power electronics, plug-in

electric, and hybrid electric vehicles, the applications of wide bandgap semi-conductors, renewable energy harvesting, and power management integratedcircuits.

Zhiqing Li (S’16) received the B.S. degree in Au-tomation from Southeast University, Nanjing, China,in 2015. He is currently pursuing the M.S. degreein electrical engineering in School of InformationScience & Technology, ShanghaiTech University,Shanghai, China.

Since 2015, he has been working as a GraduateResearch Assistant in the Power Electronics and Re-newable Energies Laboratory, School of InformationScience and Technology, ShanghaiTech University,Shanghai, China.

His research interests include resonant converters, dc/dc converters, and on-board chargers.

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