Coupled Inductor Based ZVS High Step-up DC/DC Converter in Photovoltaic Applications

Cheng Li, Student Member, IEEE, Haoyu Wang, Member, IEEE School of Information Science and Technology

ShanghaiTech University Shanghai, China

wanghy@shanghaitech.edu.cn

Abstract—In photovoltaic applications, a high step-up dc/dc converter is required to serve as the power electronic interface between the low voltage solar panel and the high voltage dc bus. In this paper, a novel high step-up dc/dc converter is proposed to enhance the performance of voltage converting. The proposed converter is based on a coupled inductor, and integrates synchronized boost topology and switch capacitor based flyback topology. This circuit demonstrates advantages including a) high voltage gain without extreme duty cycle, b) zero-voltage-switching (ZVS) and low voltage stresses on both MOSFETs, and c) switch diodes turned off at low di/dt. These features ensure its feasibility and high efficiency in high step-up applications. The operating principles and theoretical analysis have been presented, and verified by experiment. A 24 V to 380 V, 100 W, 90.95 % efficient prototype is designed to verity the proposed scheme.

Keywords—coupled inductor; dc/dc; photovoltaic; switch capacitor; zero-voltage-switching (ZVS)

I. INTRODUCTION

In recent years, research efforts on renewable energy, especially solar energy, have been kept on boosting. In distributed PV power generation systems, a high step-up dc/dc converter is essential to convert the low input voltage from the solar panel (20-40 V) to the standard dc bus voltage (380-400 V) [1].

Conventional boost converter is not a good candidate to be deployed in high step-up applications. This is mainly due to its extreme duty cycle, large power losses, and high switch voltage stresses [1]. To mitigate these issues, techniques such as cascade converters [2], multilevel converters [3], switch capacitor structures [4], as well as coupled inductors [5] have been investigated. Among them, the coupled inductor based architecture is considered as a promising candidate. This is mainly due to the fact that it can easily boost the step-up ratio without increasing the magnetic component count. Thus, a relatively high power density can be achieved.

Generally, there are two types of coupled inductor based circuit structures: parallel-connected structure [6] and series-connected structure [7]. Reference [6] is based on parallel-connected structure. In [6] an integrated boost-flyback

converter with low switch voltage stress is proposed. The converter achieves a high output voltage due to its series-charging and paralleled-discharging structure. However, its MOSFET switch operates in hard-switching condition which is harmful to the promotion of efficiency. Reference [7] is based on series-connected structure. In [7], one cascaded tapped-inductor based boost converter is proposed to achieve a high step-up ratio. However, its MOSFET switch’s voltage is close to the output voltage. To further promote the voltage gain and efficiency of coupled inductor based high step-up converters, methods such as clamped circuit [8]–[10], multi-voltage cells [11] and multi-switches strategy [12],[13], have been proposed. Also, interleaved topology is another attractive method utilized in coupled inductor converter [11],[14],[15]. In [15], a converter integrating interleaved topology and coupled inductor was proposed to boost the output voltage and mitigate the reverse recovery problem and voltage spike of switches. However, large number of components are bad for its efficiency and cost.

This paper proposes a unique topology to achieve better high step-up dc/dc conversion. This topology is derived from synchronized boost topology and flyback topology. As shown in Fig. 1, switch capacitor and coupled inductor are used to enhance its ultra-high step-up ratio. Furthermore, ZVS is achieved on both power MOSFETs while switch diodes are turned off with mitigated di/dt. Last but not least, very low voltage stresses on power MOSFETs are achieved.

This work was supported in part by the National Natural ScienceFoundation of China under Grant 51607113, and in part by the ShanghaiSailing Program under Grant 16YF1407600.

Fig. 1. Schematic of the proposed converter.

978-1-5090-5366-7/17/$31.00 ©2017 IEEE 1298

The topology and its operational principle are introduced in Section II. Then, the voltage gain analysis and design considerations are presented in Section III. Finally, the experimental results of the verification prototype are shown in Section IV. Section V summarizes the conclusion and future work.

II. PROPOSED TOPOLOGY AND OPERATIONAL PRINCIPLE

As shown in Fig. 1, a step-up switched capacitor network is added to the secondary side of the flyback structure. This switched capacitor is able to double the step-up ratio while maintaining low turning off di/dt on its diodes. Synchronized boost structure is adopted, where Q1 and Q2 turn on and off complementarily. It should be noted that both Q1 and Q2 are turned on with zero voltage.

To simplify the steady-state analysis, following assumptions are made: a) C1-4 are sufficiently large that their voltages are considered as constants (VC3 = VC4 = Vb); b) the magnetizing inductance, Lm, is sufficiently large that its current can be seen as a constant; and c) the voltage drop across the primary leakage inductor, Lk1, and secondary leakage inductor, Lk2, can be neglected while considering the voltage of output capacitors, C1, C2, and switch capacitors, C3, C4.

Fig. 2 shows the steady state waveforms. There are seven operating modes in each switching period. Their equivalent circuits are illustrated in Fig. 3. Each mode can be described briefly as follows:

Mode 1 (t0-t1]: At t = t0, Q2 turns off, the primary leakage current, ilk1, discharge Q1’s output capacitor, Coss1, to 0 V and

charge the output capacitor of Q2, Coss2 to Vc2. Then ilk1 flows through Q1’s body diode. This creates a zero voltage condition for the turning on of Q1’s channel. Since D2 and D3 are both forward-biased, ilk1 change linearly as,

1

1

/lk i b

k

di V V n

dt L

+= (1)

where, n is the turns ratio of coupled inductor.

Therefore, the current on the secondary side of the coupled inductor, ilk2, charges C3 and C4. Since ilk2 is negative, its amplitude is decaying.

Mode 2 (t1-t2]: At t = t1, Q1 is turned on. Because ilk1 has already flowed through body diode of Q1, the MOSFET Q1 turns on under zero voltage. The slope of ilk1 is the same as that in last interval. And ilk2 continues to charge C3 and C4.

Mode 3 (t2-t3]: At t = t2, ilk1 increase to the same value of iLm, and ilk2 decreases to zero. Hence, D2 and D3 turn off at zero current, which alleviates the reverse-recovery problems. After that, because of the change of the direction of ilk2, the junction capacitor of D1 is discharged until D1 turns on. Then energy stored in C3 and C4 is released to C1. Because of the changes in secondary side circuit, the slope of ilk1 in this interval is

1 1

1

(2 ) /lk i b c

k

di V V V n

dt L

+ −= (2)

Mode 4 (t3-t4]: At t = t3, Q1 is turned off. ilk1 charge Coss1 to Vc2 and discharge Coss2 to 0V and flows through the body diode of Q2. So the voltage of Q2 is maintained at zero. Because Vc2 is much smaller than output voltage and Vc1, the voltage stress of Q1 is very low and extra clamped circuit is unnecessary. In this interval, the slope of ilk1 is:

1 2 1

1

(2 ) /lk i C b C

k

di V V V V n

dt L

− + −= (3)

Mode 5 (t4-t5]: At t = t4, ilk1 decreases to the same value of iLm so that ilk2 reverses and charge the junction capacitor of D1 and discharge the junction capacitor of D2 and D3. D1 turns off at zero current. ilk2 charge capacitors C3 and C4. The slope of ilk1 in this interval is:

1 2

1

/lk i C b

k

di V V V n

dt L

− += (4)

Mode 6 (t5-t6]: At t = t5, Q2 is turned on. Because the voltage of Q2 is maintained at zero since t = t3. Hence, Q2 turns on under ZVS condition. ilk1 decreases at the slope the same as last interval.

Mode 7 (t6-t7]: At t = t6, ilk1 reverses. ilk2 continues to charge capacitors C3 and C4. Until the Q2 turns off at t = t7, ilk1 discharge Coss1 to 0 V and flows through the body diode of Q1, another period begins.

III. ANANLYSIS AND DESIGN CONSIDERATIONS

A. Voltage Gain

Fig. 2. Steady state waveforms.

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Based on the series-charging and parallel-discharging structure, the output voltage equals to the sum of both output capacitors’ voltages,

1 2o C CV V V= + (5) Some extremely narrow time intervals (t0-t2 and t3-t5) are

ignored without the compromise of the analysis accuracy. Applying voltage-second balance to Lm and Lk1 in Modes 3, 6 and 7, the corresponding voltages relationship between Vi, Vo, Vb, VC1 and VC2 can be expressed as,

2

1

1C iV VD

=−

(6)

11b C

DV V

D=

+ (7)

where, D is Q1’s duty cycle.

In one switching period, according to the charge balance of C1 and C2, the average output current Io is equal to the average current through D1. Thus, the peak current of D1 can be expressed as,

1_

2D PEAK oI I

D= (8)

During Mode 3, the slope of iLk1 is n times that of iD1,

1 12 2

22kL oD

o

di nV fdi nn I

dt dt D T D R= = = (9)

where, R is the load and f is the switching frequency. Combining equations (2), (5), (6), (7) and (9), the voltage gain can be expressed as,

21

2

1

2 ( )1

o

i k

V n nD

V fL n nDD

RD

+ +=+− +

(10)

From Eq. (10), voltage gain is dependent on Lk1. To obtain a high voltage gain, a very small Lk1 should be designed. Furthermore, given the condition that fLk1/R is sufficiently small, the voltage gain can be approximated as,

1

1o

i

V n nDM

V D

+ += =−

(11)

Combining equations (5), (6) and (11), the VC1 can be expressed as,

1 1C i

n nDV V

D

+=−

(12)

Fig. 3. Converter equivalent circuits during different operating modes: (a) Mode 1 (t0-t1], (b) Mode 2 (t1-t2], (c) Mode 3 (t2-t3], (d) Mode 4 (t3-t4], (e) Mode 5 (t4-t5], (f) Mode 6 (t5-t6], (g) Mode 7 (t6-t7].

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The voltage gain of the proposed converter is compared with counterparts proposed in [16] and [17] as shown in Fig. 4. It can be seen that the proposed converter demonstrates a higher step-up ratio. In comparison with [16], voltage gain has been improved remarkablely by adding only one capacitor and one diode.

B. Voltage Ripple

Based on the capacitor current voltage characteristics and the assumptions made Section III-A, the voltage ripple on Vb can be expressed as,

1b

o b

V

V RC f

Δ= (13)

where, Cb is switch capacitance, C3 and C4.

From Eq. (13), a large capacitance is needed to suppress the voltage ripple. Therefore, Cb can be determined according to the desired voltage ripple. Due to the similar charging and discharging process, this conclusion also applies to the output capacitors.

C. Voltage and Current Stresses

The voltage stress of both MOSFETs are clamped by VC2. Since VC2 is relatively low, the voltage stresses of both MOSFETs are low. The voltage stress of all diodes is determined by VC1 and Vb, which can be calculated based on equations (7) and (12).

According to Eq. (8), the current stress of D1 can be derived as,

1_

2 oD PEAK

VI

DR= (14)

Similarly, according the charge balance of two switch capacitors, the current stress of D2 and D3 can be derived as,

2 _ (1 )o

D PEAK

VI

D R=

− (15)

D. Design of the Coupled Inductor

In this topology, the coupled inductor is the crucial link between the boost structure and flyback structure. Besides, n,

Lk1 and Lk2 are important parameters that determine the circuit critical performances.

The minimal primary side turns number could be determined by the non-saturation constraint of the magnetic core:

0s e i nB n A E T> (16) where, Bs is the saturation flux density; n0 is the primary side turns number; Ae is the cross section area of the magnetic core; EiTn is the maximum volt-second applied to the primary side. Besides, considering the design requirements for Lm, Lk1 and winding losses, exact n0 could be determined.

Once no has been determined, a small turns ratio corresponds to a) relatively low winding and copper loss, b) reduced coupled inductor size. Therefore, a small n is preferred. However, according to the voltage gain expression in Eq. (10), to maintain a large voltage gain, a large n is preferred. Therefore, n should be designed based on the tradeoff between the desired winding length and voltage gain.

Lk1 and Lk2 are designed to mitigate the di/dt of all diodes in this converter. From equations (2) and (4), the di/dt of D1 and D2, D3 are inversely proportional to Lk1 and Lk2. Therefore, from the diodes’ perspective, Lk1 and Lk2 should be sufficiently large. However, according to Eq. (10), the increase of Lk1 leads to the decrease of voltage gain. Therefore, Lk1 should be designed based on the tradeoff between the desired diode di/dt and voltage gain.

IV. EXPERIMENTAL RESULTS

To verify the proposed topology, a 100 W prototype was implemented. Its design specifications and circuit parameters are listed in Table I.

To demonstrate the ultra-step-up features of this converter, a comparison between its experimental voltage gain while Lk1 = 3 μH and theoretical predicted voltage gain of converters in [16] and [17] are plotted in Fig. 5. As shown, under the same duty cycle, the experimental voltage gain is larger than the theoretical voltage gain in [16]. Voltage gain is boosted with minimized components count increase.

Fig. 4. Theoretical voltage gain versus duty cycle and its comparison with the state of the art.

TABLE I DESIGN PARAMETERS OF THE PROTOTYPE

Symbol Quantity Parameters

Vi input voltage 24 V Vo output voltage 380 V

C1 C2 output capacitor 47 μF / 450 V C3 C4 switch capacitor 47 μF / 450 V Q1 Q2 MOSFET switch IRF 540 PBF D1-3 power diode LXA03T600

n turns ratio 3.8 Lm magnetizing inductor 618 μH Lk1 primary leakage inductor 8.1 μH Lk2 secondary leakage inductor 17.2 μH f switching frequency 55 kHz D switch Q1 duty ratio 65%

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Steady state current and voltage waveforms of the MOSFETs are captured in Fig. 6 and 7. According to Fig. 6 and 7, the resonance between Coss and Lk1 facilitates the ZVS of both MOSFETs. It should be noted that this resonance also comes with a voltage spike on vds when the MOSFET turns on. Due to the low voltage of both MOSFETs, no extra clamped circuit are needed and relatively low voltage rating power MOSFETs with low on resistances can be selected. Therefore, the corresponding conduction loss can be reduced.

Also, ZVS for both MOSFETs can be observed according to Fig. 6 and 7. When both MOSFETs turn on, there is a negative current flowing through their body diodes. This

negative current discharges Coss of both MOSFETs and create a zero voltage condition before corresponding voltage begins to increase. Hence, the turn-on loss is much smaller than the hard switching condition. Therefore, the switching losses can be reduced.

Fig. 8 illustrates the waveforms of ilk1 and ilk2. Their experimental waveforms coincide with simulated waveforms and verified the assumptions about operating principles are correct. Also, according to the current and voltage of diodes illustrated in Fig. 9, the di/dt of all diodes are corresponded with ilk1 and ilk2 and can be regulated by Lk1 and Lk2.

Vol

tage

gai

n

Fig. 5. Experimental voltage gain versus duty cycle and its comparison with the state of the art (Lk1 = 3 μH).

ZVSvds1

iQ1

Fig. 6. current and voltage waveforms of MOSFET Q1 (Lk1 = 8.1 μH).

ZVS

vds2

iQ2

Fig. 7. current and voltage waveforms of MOSFET Q2 (Lk1 = 8.1 μH).

ilk1

ilk2

Fig. 8. current of coupled inductor waveforms (Lk1 = 8.1 μH).

vD2

vD1

iD1

iD2

Fig. 9. current and voltage waveforms of all diodes (Lk1 = 8.1 μH).

Fig. 10. detailed current and voltage waveforms of D2 (Lk1 = 8.1 μH).

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According to the detailed switch diode current and voltage waveforms of D2, as illustrated in Fig. 10, the turning off di/dt for D2 and D3 are 0.86A/μs. Also, no reverse recovery process for switch is observed. This low di/dt guarantees low diode turning off loss. Also this mitigates the diode di/dt requirement.

At 65% duty cycle, 55 kHz switching frequency, 100 W, 24 V input, and 380 V output, the efficiency of the designed prototype is measured to be 90.95%.

V. CONCLUSIONS

In this paper, a novel high step-up dc/dc converter using coupled inductor is proposed for photovoltaic applications. This high step-up converter can achieve low turning off di/dt for switch diodes, low switch voltage stresses, and ZVS for both MOSFETs. Experimental results are presented to verify its performance and theoretical analysis. It is proved that this topology is a competitive option in photovoltaic applications.

Future work will focus on loss analysis and efficiency improvement.

REFERENCES [1] H. Liu, H. Hu, H. Wu, Y. Xing, and I. Batarseh, “Overview of High-

Step-Up Coupled-Inductor Boost Converters,” IEEE J. Emerg. Sel. Top. Power Electron., vol. 4, no. 2, pp. 689–704, Feb. 2016.

[2] C.-M. Young, M.-H. Chen, T.-A. Chang, C.-C. Ko, and K.-K. Jen, “Cascade Cockcroft–Walton Voltage Multiplier Applied to Transformerless High Step-Up DC–DC Converter,” IEEE Trans. Ind. Electron., vol. 60, no. 2, pp. 523–537, Feb. 2013.

[3] R. Shalchi Alishah, S. H. Hosseini, E. Babaei, M. Sabahi, and A. Zare, “Extended high step-up structure for multilevel converter,” IET Power Electron., vol. 9, no. 9, pp. 1894–1902, Jul. 2016.

[4] A. Ajami, H. Ardi, and A. Farakhor, “A Novel High Step-up DC/DC Converter Based on Integrating Coupled Inductor and Switched-Capacitor Techniques for Renewable Energy Applications,” IEEE Trans. Power Electron., vol. 30, no. 8, pp. 4255–4263, Aug. 2015.

[5] J. Ai and M. Lin, “Ultra-Large Gain Step-Up Coupled Inductor DC-DC Converter With Asymmetric Voltage Multiplier Network for a Sustainable Energy System,” IEEE Trans. Power Electron., vol. PP, no. 99, pp. 1–1, Nov. 2016.

[6] Q. Zhao and F. C. Lee, “High Performance Coupled-Inductor DC-DC Converters,” in Proc. IEEE Applied Power Electronics Conference and Exposition, Miami, FL, vol. 1, pp. 109–113, Feb, 2003.

[7] N. Vazquez, L. Estrada, C. Hernandez, and E. Rodriguez, “The Tapped-Inductor Boost Converter,” in Proc. IEEE International Symposium on Industrial Electronics, Vigo, Spain, pp. 538–543, Jun. 2007.

[8] B. Gu, J. Dominic, J. S. Lai, Z. Zhao, and C. Liu, “High boost ratio hybrid transformer DC-DC converter for photovoltaic module applications,” in Proc. IEEE Applied Power Electronics Conference and Exposition, Orlando, FL, pp. 598–606, Feb, 2012.

[9] K.-C. Tseng, C.-C. Huang, and C.-A. Cheng, “A Single-Switch Converter with High Step-up Gain and Low Diode Voltage Stress Suitable for Green Power-Source Conversion,” IEEE J. Emerg. Sel. Top. Power Electron., vol. 04, no. 2, pp. 363–372, Jul. 2016.

[10] H. C. Liu and F. Li, “Novel High Step-Up DC-DC Converter with an Active Coupled-Inductor Network for a Sustainable Energy System,” IEEE Trans. Power Electron., vol. 30, no. 12, pp. 6476–6482, Dec. 2015.

[11] K. C. Tseng and C. C. Huang, “High step-up high-efficiency interleaved converter with voltage multiplier module for renewable energy system,” IEEE Trans. Ind. Electron., vol. 61, no. 3, pp. 1311–1319, Mar. 2014.

[12] A. A. A. Freitas, F. L. M. Antunes, S. Daher, E. M. Sá Júnior, and F. L. Tofoli, “High-voltage gain dc–dc boost converter with coupled inductors for photovoltaic systems,” IET Power Electron., vol. 8, no. 10, pp. 1885–1892, Sept. 2015.

[13] M. Shang, and H. Wang, “A ZVS integrated single-input-dual-output converter for high step-up applications,” in Proc. IEEE Energy Conversion Congress and Exposition, Milwaukee, WI, Sept. 2016.

[14] W. Li, Y. Zhao, J. Wu, and X. He, “Interleaved High Step-Up Converter With Winding-Cross-Coupled Inductor and Voltage Multiplier Cells,” IEEE Trans. Power Electron., vol. 27, no. 1, pp. 133–143, Jan. 2012.

[15] L. He and Y. Liao, “An Advanced Current-Autobalance High Step-Up Converter With a Multicoupled Inductor and Voltage Multiplier for a Renewable Power Generation System,” IEEE Trans. Power Electron., vol. 31, no. 10, pp. 6992–7005, Oct. 2016.

[16] H. W. Seong, H. S. Kim, K. B. Park, G. W. Moon, and M. J. Youn, “High step-up DC-DC converters using zero-voltage switching boost integration technique and light-load frequency modulation control,” IEEE Trans. Power Electron., vol. 27, no. 3, pp. 1383–1400, Jul. 2012.

[17] Y. Tang, D. Fu, T. Wang, and Z. Xu, “Hybrid Switched-Inductor Converters for High Step-Up Conversion,” IEEE Trans. Ind. Electron., vol. 62, no. 3, pp. 1480–1490, Oct. 2015.

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