a zvs three-port dc/dc converter for high-voltage bus...

10688 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 11, NOVEMBER 2019

A ZVS Three-Port DC/DC Converter forHigh-Voltage Bus-Based Photovoltaic Systems

Junyun Deng , Student Member, IEEE, Haoyu Wang , Senior Member, IEEE, and Ming Shang

Abstract—In high-voltage bus-based photovoltaic systems, apower electronic interface is required to manage the power flow inbetween the photovoltaic (PV) panel, battery, and the high-voltagedc bus. In this paper, a novel three-port dc/dc topology is pro-posed for this application. Pulsewidth and phase-shift offer twodegrees of freedom to effectively regulate the power flows. On theprimary side, the input current ripple is reduced due to the in-terleaved structure. This avoids the usage of the bulky electrolyticcapacitors on the PV terminal. On the secondary side, a voltagesixfolder rectifier is employed to boost the step-up ratio. This re-duces the transformer’s secondary-side turns number. Moreover,the voltage stresses of secondary-side MOSFETs and diodes are re-duced to one-third of the output voltage. Zero-voltage switchingand zero-current switching are realized among all power MOSFETsand diodes, respectively, and in an extended range. A 500-W con-verter prototype, linking a battery pack, a PV panel, and a 760 Vdc bus, is designed and tested to verify the proof-of-concept. Boththe circuit functionality and theoretical analysis are validated bythe experimental results.

Index Terms—High-voltage bus, phase-shift modulation,pulsewidth modulation (PWM), three-port converter (TPC), zero-voltage switching (ZVS).

I. INTRODUCTION

IN PHOTOVOLTAIC (PV) based microgrid systems, 760 Vhigh-voltage dc bus compatible with half-bridge inverter,

three-phase four-wire inverter, and neutral point clamp inverteris becoming an attractive solution [1]–[4]. Due to the powermismatch between the PV generator and the load, rechargeablebattery is required to serve as the energy reserve. Therefore,in the high-voltage bus based microgrid systems, a three-portconverter (TPC) is necessary to manage the power flow among

Manuscript received July 9, 2018; revised September 18, 2018 and December1, 2018; accepted January 18, 2019. Date of publication January 29, 2019; dateof current version August 29, 2019. Recommended for publication by AssociateEditor D. Vinnikov. This work was supported in part by the National NaturalScience Foundation of China under Grant 51607113 and in part by the ShanghaiSailing Program under Grant 16YF1407600. (Corresponding author: HaoyuWang.)

J. Deng is with the Power Electronics and Renewable Energies Labora-tory, School of Information Science and Technology, ShanghaiTech Univer-sity, Shanghai 201210, China, and also with the Chinese Academy of Sciences,Shanghai Institute of Microsystem and Information Technology, Universityof Chinese Academy of Sciences, Shanghai 200050, China (e-mail:, [email protected]).

H. Wang and M. Shang are with the Power Electronics and Renew-able Energies Laboratory, School of Information Science and Technol-ogy, ShanghaiTech University, Shanghai 201210, China (e-mail:, [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2019.2895976

Fig. 1. Structure of three-port 760 V dc bus-based PV microgrid.

the PV panel, battery, and the high-voltage bus. The diagram ofsuch a microgrid system is illustrated in Fig. 1.

To realize the TPC, the conventional method is to use multiplediscrete converters [5], [6]. This jeopardizes the power densityand conversion efficiency. Moreover, different control strate-gies, such as maximum power point tracking (MPPT), batterycharging/discharging and load regulation need to be addressedseparately.

To improve, the concept of integrated TPC has been proposed.The integrated solution is featured with reused circuit compo-nents, reduced power conversion stages, and centralized controlstrategy. Due to those advantages, integrated TPC topologiesand the corresponding control strategies have attracted wideresearch attention in recent years.

Integrated TPC topologies can be classified into three cate-gories: non-isolated TPCs, three-port isolated TPCs, and two-port isolated TPCs. By integrating coupled inductors into boostor buck–boost topologies, multiple non-isolated TPCs can bederived [7]–[10]. The high voltage gain with a moderate dutycycle can be achieved. However, non-isolated TPCs are usuallynot considered due to the requirement of galvanic isolation inhigh-voltage bus applications.

Alternatively, some isolated three-port TPCs are proposed in[11]–[14]. Those converters are usually based on half-bridge,boost-half-bridge, or full-bridge structures. A three-windingtransformer is employed to realize multi-directional power flow.The transformer turns ratio can be easily customized to accom-modate different voltage levels. However, the switch count ishigh, which leads to increased manufacturing cost and conduc-tion loss. Furthermore, the design of the magnetic componentsis complicated.

Compared with three-port isolated solution, two-port isolatedTPC is more attractive. It offers galvanic isolation between thehigh and low voltage sides, and easily accommodates differentvoltage levels. Furthermore, it is featured with reduced switchcount and simpler transformer design. By integrating the boostconverter into the phase-shift-full-bridge (PSFB) converter, a

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DENG et al.: ZVS THREE-PORT DC/DC CONVERTER FOR HIGH-VOLTAGE BUS-BASED PHOTOVOLTAIC SYSTEMS 10689

group of zero-voltage switching (ZVS) TPCs is proposed in[15]–[17]. However, there are some intrinsic disadvantages in-herited from PSFB topology, [18]: High conduction loss in thefreewheeling stage; constrained ZVS range on the primary sideMOSFETs; duty cycle loss due to the existence of output fil-ter inductor; and voltage spike and reverse recovery issues onsecondary diodes. To improve, topologies without the output in-ductor are proposed in [19] and [20]. The freewheeling currentis reduced and the duty cycle loss is eliminated. Zero-currentswitching (ZCS) for the secondary-side diodes is achieved, andthe voltage spikes are eliminated due to the clamping effect ofthe output capacitor. However, the current ripple on the PV panelis large, while large ripple current might degrade the lifetime ofthe PV panel [21]. In [22], a current-fed two-port bidirectionaldc/dc converter is proposed to reduce current ripples. Via PWMcontrol on the primary side, the amplitudes of the transformerinput and output voltages are well matched. This reduces the cir-culating loss and extends the ZVS range. The phase shift controlregulates the output power magnitude and direction. However,the existing control strategy cannot be directly deployed to theTPC due to the introduction of the third port. In [23], the inter-leaving technique is introduced to the primary side to suppressthe current ripple. However, in the discontinuous conductionmode (DCM), both the current stress and conduction loss arelarge, and the primary side ZVS range is constrained. In [24],a ZVS multiport bidirectional dc/dc converter is proposed forhybrid energy storage systems. The secondary side is based anactive full bridge rectifier. In [25], a three-port three-phase bidi-rectional converter is proposed. Due to the interleaved structure,the power capacity is enhanced and the current ripple is reduced.In addition, MPPT and output power control are regulated bytwo control variables independently. To extend the ZVS range,a TPC integrating boost and LLC topologies is proposed in [26].However, it adopts pulsewidth and pulse-frequency hybrid regu-lation scheme and this control scheme is difficult to implement.

It is worth mentioning that most of the state-of-the-art two-port isolated TPCs adopt half/full bridge rectification stage onthe output side. Therefore, to realize a high step-up ratio, atransformer with large secondary-side turns number is required.This degrades the system power density. In addition, the volt-age stresses of the secondary-side switches equal to the outputvoltage or twice of the output voltage. This brings challenges tothe optimal selection of semiconductors in high-voltage appli-cations. Cascaded H-bridge converter is another option in highvoltage applications, due to modular structure and simple con-trol [27]–[30]. However, it usually suffers from an imbalance ofcapacitor voltages [29], [30].

In [31] and [32], the voltage quadrupler rectifier is adopted inhigh-voltage bus based PV systems. This rectifier owns the ben-efits of moderate secondary-side turns number and low voltagestresses on the high-voltage side. However, the current ripplesof the PV panel are large. In addition, the voltage regulationis based on singular pulse-frequency or phase-shift modulation.Thus, it is infeasible to deploy those topologies into the three-port applications.

A novel two-port isolated integrated TPC is proposed inthis paper. The initial idea is partially presented in [33].

Fig. 2. Schematic of the proposed three-port topology.

The proposed topology is derived from interleaved boost topol-ogy and active voltage sixfolder rectifier. The phase-shift onthe active rectifier brings another modulation scheme, whichaccommodates the three-port power flow control. This makesit a good candidate for high-voltage bus based PV systems. Incomparison with the prior arts, it demonstrates the followingadvantages:

1) the PV panel current ripple is reduced remarkably;2) ZVS and ZCS ranges are effectively extended;3) a high step-up ratio is realized with a moderate transformer

secondary-side turns number;4) the voltage stresses on the secondary-side semiconductors

are reduced to one-third of the output voltage;5) smooth transitions are achieved between different work-

ing modes.This paper is organized as follows. Section II presents the

topological description and modes analysis. In Section III, theconverter features are analyzed in detail. The design consider-ation and control strategy are given in Section IV. Section Vpresents the experimental results. Section VI concludes thepaper.

II. DESCRIPTION OF THE PROPOSED CONVERTER

A. Topology Description and Derivation

Fig. 2 shows the schematic of the proposed TPC. The primary-side circuit is the parallel of two synchronized rectified boostunits, including two inductors (L1 and L2) and four powersMOSFETs S1–S4 . The driving signals for S1 and S2 (S3 and S4) arecomplementary with certain deadband. The two parallel phaselegs are driven in an interleaved manner with 180° phase-shift.The duty cycle of S1’s gate signal is defined as D. The powerflow from the PV panel to the battery can be regulated by D.The transformer turns ratio is defined as 1:n. On the secondaryside, S5 and S6 are driven complementarily with fixed 0.5 dutycycle. Certain phase-shift (β) between the switch patterns of S1and S6 is enforced to regulate the power delivered to the load.The phase-shift ratio is defined as Dph = β/π.

The secondary side active rectifier of the proposed topologyorigins from a passive sixfolder rectifier [see Fig. 3(a)]. Theschematics of the active versions are plotted in Fig. 3(b) to (d).The active versions enable secondary-side phase-shift control.Therefore, control of power flows in two paths in the TPC canbe well implemented.

In the perspective of three-port integration, the proposedconverter is derived from the integration of interleaved


Fig. 3. (a) Passive sixfolder rectifier. (b) Active sixfolder rectifiers 1. (c) Activesixfolder rectifiers 2. (d) Active sixfolder rectifiers 3.

synchronized-rectified boost topology [see Fig. 4(a)] and full-bridge-phase-shift topology with active sixfolder rectifier [seeFig. 4(b)]. This integration enables power flow from PV to load,as shown in Fig. 4(c).

B. Working Modes and Operational Principles

Due to the time-varying nature of the PV panel, the oper-ation of the converter can be classified as daytime mode andnight mode. The power conversion process in different workingmodes is illustrated in Fig. 5. In daytime mode, the PV power isdelivered to the load. The battery functions as an energy bufferto compensate the power mismatch. In night mode, the PV panelis decoupled. The power is delivered from the battery to the load.

Based on the range of D and β, the steady-state operationhas four different states. In this paper, the main operation statewith D < 0.5 and β > 0 is discussed and analyzed in detail. Inthis state, there are 14 operation modes in one switching period.Considering the circuit symmetry, only 7 operation modes in ahalf switching period are presented.

L1 and L2 are equal and are sufficiently large to maintaincontinuous inductor currents. The secondary-side capacitancesare sufficiently large with ignorable voltage ripples. Accordingto the principles of the proposed secondary-side rectifiers,the relationship between the amplitude of Vcd and Vo can beexpressed as

Vcd = Vo/6. (1)

Thus, the normalized voltage conversion ratio k is defined as

k =VO

6nVbat. (2)

The following analysis is based on the assumption that k > 1.The key waveforms are plotted in Fig. 6 and the correspondingequivalent circuits are presented in Fig. 7.

Fig. 4. Equivalent circuits in different power flow paths. (a) PV to battery.(b) Battery to load. (c) PV to load.

Fig. 5. Working modes. (a) Daytime mode. (b) Night mode.

Mode I. [t0 , t1): Before t0, S2,4,5 are ON and the secondary-side diodes D2,4 conduct. iLlk is negative. L1 and L2 are en-ergized by the PV panel. C5 and C6 are charged while C4 isdischarged.

At t0 , S2 is turned OFF. The inductor current flows from thesource to drain of S1 . L1 releases power to the battery while L2continues to be energized. During the deadband, the negativecurrent discharges the output capacitors (Coss) of S1,2 . In thismode, iLlk is expressed as

iLlk (t) =nVbat + Vo/6

Llk(t − t0) + iLlk (t0) . (3)

Mode II. [t1 , t2): At t1 , S1 is naturally turned on with ZVS.At the end of this mode, D2 and D4 are turned OFF naturallywithout reverse-recovery losses. iLlk begins to flow through S5and continues to decrease.


Fig. 6. Critical steady-state waveforms.

Mode III. [t2 , t3): During this mode, C1 is charged while C2is discharged. Llk continues to release power. Mode III endswhen iLlk crosses zero.

Mode IV. [t3 , t4): The equivalent circuit in this mode is iden-tical t Mode III. However, at t3 , iLlk becomes positive andincreases linearly. iS5 becomes positive. This means iS5 onlyflows S5’ channel. At t4 , S5 is turned OFF; the body diode of S6 ,D1 , and D3 begin to conduct.

Mode V. [t4 , t5): During this mode, iS6 is still negative. Thismeans the ZVS for the secondary-side MOSFETs occurs naturallywithout any deadband. iLlk decreases linearly. At the end of thismode, S1 is turned OFF. In Mode V, iLlk is expressed as

iLlk (t) =nVbat − Vo/6

Llk(t − t4) + iLlk (t4) . (4)

Mode VI. [t5 , t6): This mode is similar to Mode I. During thisshort interval, Coss of S2 is discharged to zero. This creates aZVS condition for S2 . At t5 , L1 begins to be energized by thePV panel. In this mode, iLlk is expressed as

iLlk (t) = −Vo/6Llk

(t − t6) + iLlk (t6). (5)

Mode VII. [t6 , t7): At t6 , S2’ channel conducts with zerovoltage. At the end of this mode, S4 is turned OFF and the bodydiode of S3 conducts. At t7 , iLlk has the same amplitude butreverse direction compared with its initial value at t0

iLlk (t0) = −iLlk (t7) . (6)

III. MODELING AND ANALYSIS

A. Circuit Modeling and Output Power Analysis

The proposed topology can be simplified into an equivalentcircuit, as shown in Fig. 8(a). The typical waveforms of vab andvcd are demonstrated in Fig. 8(b).

According to the Fourier analysis, vab and vcd can beexpressed as

vab =∑

i=1,3,5,...

4Vp

iπcos

(iα

2

)sin (iω0t)

vcd =∑

i=1,3,5,...

4Vs

iπsin [i (ω0t − β − α/2)] (7)

where

α =

{2 (0.5 − D) π, (D < 0.5)2 (D − 0.5) π, (D > 0.5) .

(8)

The amplitudes of vab and vcd can be derived

{Vp = Vbat

Vs = Vo/6.(9)

The output power with D < 0.5 can be derived as

Po =∑

i=1,3,5,...

PB ,icos [i (0.5 − D) π]

× sin {i [β + (0.5 − D) π]} (10)

where β + (0.5 − D)π < π, and PB,i is the normalized power

PB,i =4nVoVbat

3i3π3fsLlk. (11)

In order to simplify the analysis, only the fundamental compo-nent is considered. The corresponding result is plotted in Fig. 9.As indicated, the output power curve is symmetrical to D = 0.5;β and 2Dπ − β correspond to the same Po . Thus, there are twosymmetric phase-shift regulation ranges [0, Dπ) and [Dπ, Dπ+ 0.5π). In [0, Dπ), Po increases with the increase of phase-shift angle. While in [Dπ, Dπ + 0.5π), Po decreases with theincrease of phase-shift angle. Practically, the phase-shift angleis constrained in one specific range.

In this proposed topology, a certain circulating/reactive poweris necessary to maintain ZVS condition. The reactive power withD < 0.5 is derived as (12), and the corresponding result is plotted


Fig. 7. Converter equivalent circuits. (a) Mode I, t0 � t < t1 . (b) Mode II, t1 � t < t2 . (c) Mode III, t2 � t < t3 . (d) Mode IV, t3 �t < t4 . (e) Mode V, t4 � t <t5 . (f) Mode VI, t5 � t < t6 . (g) Mode VII, t6 � t < t7 .

Fig. 8. Circuit modeling. (a) Equivalent circuit. (b) Critical voltage wave-forms.

in Fig. 10

Q =∑

i=1,3,5,...

PB ,i cos [i (0.5 − D) π]

×{

cos [i (0.5 − D)π]k

− cosi [β + (0.5 − D) π]}

.

(12)

However, the reactive power also leads to increased conduc-tion loss and current stresses. In the perspective of efficiencyimprovements, the reactive power should be reduced. To sim-plify the analysis, only the fundamental component is consid-ered. According to (12) and Fig. 10, some design guidelinescan be extracted: Q increases with the increase of β. Since Po

corresponds to two symmetric β, the smaller β is preferred; kalso affects Q. When β is small, Q is minimized around k = 1;

Fig. 9. Curves of output power versus phase-shift ratio under different dutycycles (k >1).

When D = 0.5, α equals zero. This results in increased Q; SmallQ corresponds to large Llk .

B. Voltage Gain

The primary side is essentially an interleaved boost converter.Thus, the relationship between Vpv and Vbat is derived as

Vbat =Vpv

D. (13)

When the gate signals of the secondary-side MOSFETs are re-moved, the MOFSETs function as diodes. The corresponding βequals zero and the secondary side becomes a passive voltagemultiplier. Thus

Vo = 6nVbat . (14)


Fig. 10. Curves of reactive power versus phase-shift ratio under different dutycycles (k >1).

Fig. 11. Curves of voltage gain versus D’ under different turns ratios.

The corresponding voltage gain is

G′ = Vo/Vpv =6n

D. (15)

The gain curves versus D′(1 − D) with different transformerturns ratios are plotted in Fig. 11. As indicated, although thetransformer turns ratio and the duty cycle are moderate, a gen-eral high voltage gain is achieved with passive voltage multiplierrectifier. As aforementioned, β is constrained in [0, Dπ) to min-imize Q. In this range, the voltage gain increases as β increases.

Hence, the minimum voltage gain with β equals to zero is

Gmin = G′. (16)

Furthermore, when the gate signals of the secondary-sideMOSFETs are high, phase-shift control is activated. Due to theadded control degree of freedom, the voltage gain regulationrange is changed from a single curve to a two-dimension plane.Compared with passive voltage multiplier rectifier, the regula-tion flexibility of voltage gain is enhanced. Therefore, a higherstep-up ratio can be achieved.

Fig. 12. ZVS conditions for primary-side MOSFETs.

C. Current Stress Analysis

According to the steady-state analysis in (2)–(6)

iLlk (t0) =nVbat

4Llkfs(k − 2D − 4Dphk)

iLlk (t4) =nVbat

4Llkfs(k − 2D + 4Dphk)

iLlk (t5) =nVbat

4Llkfs(k + 2D + 4Dphk − 4Dk) . (17)

Thus, the peak current is derived as

imax = iLlk (t4) =nVbat

4Llkfs(k − 2D + 4Dphk) . (18)

As indicated by (18), large Llk corresponds to small currentstress, and large β leads to large current stress. This also endorsesthat β should be constrained in [0, Dπ).

D. Soft Switching

1) Secondary-Side Switches: To ensure ZVS, Coss of MOS-FET should be fully discharged before the channel conducts. Asshown in Fig. 3, a negative current exists before the gate signal isapplied. This indicates a clear ZVS. Meanwhile, the secondary-side diodes’ turn-OFF di/dt is constrained by Llk . This ensures asecure ZCS turn-OFF of the diodes. Hence, the reverse recoveryissues can be effectively mitigated.

2) Primary-Side mosfets: As demonstrated in Fig. 12,the ZVS condition of the primary-side MOSFETs can beexpressed as

⎧⎪⎪⎪⎨

⎪⎪⎪⎩

S1 : iL1(tS1) − niLlk (tS1) > Imin

S2 : iL1(tS2) − niLlk (tS2) < −Imin

S3 : iL2(tS3) + niLlk (tS3) > Imin

S4 : iL2(tS4) + niLlk (tS4) < −Imin

(19)

where ts1∼ ts4 are the turn-ON time of S1∼ S4 , respectively.In the energy storage perspective, the minimum current tocharge and discharge Coss of two complementary MOSFETs isdefined as

Imin =

√2 · Coss · Vbat

2

Llk. (20)

To achieve ZVS, assuming Imin is constant during the deadtime, the following condition should be satisfied:

Imintdead ≥ 2CossVbat . (21)


Fig. 13. ZVS boundaries for primary-side MOSFETs. (a) S1 ,3 . (b) S2 ,4 (Vpv =30V, Vbat = 60 V and Vo = 760 V).

According to the basic principles of the boost converter, iL1and iL2 are derived as

{iL1(tS1) = iL2(tS3) = Pp v

2Vp v+ Vp v

2L (1 − D)TS

iL1(tS2) = iL2(tS4) = Pp v

2Vp v− Vp v

2L (1 − D)TS .(22)

According to the steady-state analysis of the primary-sidecircuit, iLlk is expressed as

{iLlk (tS1) = −iLlk (tS3) = iLlk (t0) < 0

iLlk (tS2) = −iLlk (tS4) = iLlk (t5) > 0.(23)

Due to the law of energy conservation, Ppv is expressed as

Ppv = Po − Pbat ≥ 0. (24)

By substituting (20)–(24) into (19)⎧⎪⎪⎪⎪⎪⎪⎨

⎪⎪⎪⎪⎪⎪⎩

S1 : Po + V b a t2 D 2 (1−D )LfS

− 2 [niL lk (t0 ) + Im in ] DVbat > Pbat

S2 : Po − V b a t2 D 2 (1−D )LfS

− 2 [niL lk (t5 ) − Im in ] DVbat < Pbat

S3 : Po + V b a t2 D 2 (1−D )LfS

− 2 [niL lk (t0 ) + Im in ] DVbat > Pbat

S4 : Po − V b a t2 D 2 (1−D )LfS

− 2 [niL lk (t5 ) − Im in ] DVbat < Pbat .

(25)

It should be noted that the ZVS conditions for S1 and S3are identical. So it is with S2 and S4 . According to (25) andFig. 13, the ZVS condition for the proposed converter is ratherdifferent from the traditional PSFB converter. This is mainly dueto the existence of L1 and L2 . The ZVS boundary of the upperMOSFETs (S1 and S3) is higher than the power line (Po = Pbat).This means the upper MOSFETs operate under ZVS inherently.

However, ZVS for the lower MOSFETs (S2 and S4) is de-termined by the output/battery power. Therefore, ZVS of thelower switches is more important. In addition, the ZVS rangeis affected by the inductances and battery working modes. Gen-erally, small inductance leads to a large inductor current ripple

and wider ZVS range. The battery charging mode with Pbat >0 is featured with a wider ZVS in the lower MOSFETs.

The conventional pulsewidth and phase-shift hybrid mod-ulated TPCs are prone to operate in the DCM in light loadcondition. In this mode, the primary-side switches turn ON withiLlk equals zero. According to (19), the ZVS for the lower MOS-FETs is difficult to achieve. In the proposed converter, the DCMoperation is naturally avoided. Therefore, the light load ZVSperformance is enhanced.

E. Loss Analysis

Since all MOSFETs can achieve ZVS turning-ON and all diodescan achieve ZCS turning-OFF, the main losses include MOSFET

turn-OFF loss, conduction loss, and the magnetic loss.1) mosfet Turn-off Loss: The turn-OFF loss is crucial due

to the relatively high turn-OFF current in phase-shift control.Due to the symmetry of the primary side MOSFETs, the turn-OFF currents for S1 and S3 (S2 and S4) are equal, respectively.Therefore, only the turn-OFF currents of S1 and S2 are analyzed

{is1,off = − [iL1(t5) − niLlk (t5)]

is2,off = iL1(t0) − niLlk (t0).(26)

According to the basic principles of buck/boost converter{

iL1(t0) = Ppv2Vpv

+ Vpv2L (1 − D) TS

iL1(t5) = Ppv2Vpv

− Vpv2L (1 − D) TS .

(27)

By substituting (17) and (27) into (26), the turn-OFF currentis1(toff ) and is2(toff ) can be calculated as

⎧⎪⎪⎪⎪⎪⎨

⎪⎪⎪⎪⎪⎩

is1,off = DVb a t2L (1 − D) TS − Ppv

2DVb a t

+n2 Vb a t4Ll k fs

(k + 2D + 4Dphk − 4Dk)

is2,off = DVb a t2L (1 − D) TS + Ppv

2DVb a t

+n2 Vb a t4Ll k fs

(2D + 4Dphk − k) .

(28)

For the secondary side MOSFETs, according to the circuit sym-metry and the operation mode, the turn-OFF currents for S5 andS6 are identical and can be derived as

is5,off = is6,off =12iLlk (t4) =

nVbat

8Llkfs(k − 2D + 4Dphk) .

(29)During the turn-OFF process of MOSFET, the turn-OFF loss

occurs in two periods t1 and t2 [33]. During t1 , the drain-to-source Vds increases from 0 V to Vds,off and the current keepsis,off . During t2 , the drain-to-source Vds keeps Vds,off and thecurrent decreases from is,off to 0 A. However, the energy storedin Coss will be recycled at turn-ON moment due to ZVS. Tosimplify the analysis, the voltage and current waveforms arelinearized. Therefore, the turn-OFF loss can be calculated as

Ploss(off ) =[Vds(off ) × is(off )

2× (t1 + t2)

−12× Coss × Vds(off )

2]× fs (30)


where t1 and t2 can be estimated from the datasheet, fs is theswitching frequency, and Vds,off is the reverse blocking voltage.

Therefore, to decrease the turn-OFF losses, the reduction ofturn-OFF current is required.

2) Conduction Loss for Switches: On the primary side, MOS-FETs S1 and S3 (S2 and S4) have identical root-mean-square(RMS) current. On the secondary side, S5 and S6 have identi-cal RMS current. So it is with all the secondary-side diodes.Therefore, the conduction loss can be calculated as

Pcod = 2(R1I

21rms + R1I

22rms + R2I

23rms

)) + 4VD I4rms

(31)where R1 and R2 are the ON resistances of the primary-side andthe secondary-side MOSFETs, respectively. VD is the forwardvoltage drop for the secondary-side diodes. I1rms , I2rms , I3rms ,and I4rms are the RMS current of S1 (S3), S2 (S4), S5 (S6), andthe secondary side diodes, respectively.

3) Capacitors Conduction Loss: The conduction loss forone capacitor can be calculated as

Ploss,cap = RESRIcap2 (32)

where RESR is equivalent series resistance of capacitors andIcap is RMS value of ripple current.

4) Driving Loss: According to [34], the driving loss can becalculated as

Pdriv = VDRV × QG × fs (33)

where VDRV is the gate drive voltage and Qg is total gate charge.5) Magnetic Loss: The magnetic losses include two parts:

coil loss and core loss. The copper loss can be calculated as

Pcu = ρwlwAw

I2rms (34)

where ρ, lw , Aw are the parameters of the conductors and Irmsare the RMS current. It should be noted that Litz wire and in-terleaved winding help to mitigate the skin effect and proximityeffect.

Steinmetz’s equation is used to estimate the core loss

Pf e = Kcfsα

(ΔB

2

)β

(35)

where Kc , α, and β are provided from the datasheet, and ΔB isthe variation of the magnetic flux. ΔB can be calculated basedon the Faraday law of electromagnetic induction.

According to the above analysis, the power losses are ana-lyzed and plotted in Fig. 14.

IV. DESIGN CONSIDERATIONS AND CONTROL STRATEGY

A. Design Consideration

1) Transformer Turns Ratio: For the PV panel’s terminalvoltage varies under different irradiance intensities, the trans-former turns ratio needs to be designed to accommodate thevoltage range of the PV panel. Therefore, the turns ratio is de-signed as

n =DVo

6Vpv min. (36)

Fig. 14. Power loss breakdown at peak power.

TABLE ICOMPARISON OF COMPONENT VOLTAGE STRESSES

2) Leakage Inductance: On one hand, the maximum Po de-creases when Llk increases. On the other hand, small Llk leadsto high reactive power and large current stresses. Therefore, thetradeoff between the power capacity and efficiency need to beconsidered to determine Llk . To guarantee the rated Po over thewhole load range, Llk should meet the inequation

Llk ≤ K4nVoVbat

3π3fsPrate(37)

where K is a factor determined by the load range. So by thecalculation, Llk is set to be 35 μH.

3) Secondary-Side Switches and Capacitors: The voltageratings of the secondary-side switches and capacitors need tobe analyzed to facilitate the selection of components. Theirvoltage stresses are summarized and compared with the con-ventional structures in Table I.

As shown, the voltage stresses of the secondary-side switchesand capacitors are much smaller than the conventional struc-tures. This makes the proposed converter more suitable forhigh-voltage applications. According to Table I, 300 V ratedswitches are selected, and 450, 250, and 200 V rated capacitorsare selected. Silicon MOSFETs with low on-resistance and siliconSchottky diodes with low forward voltage drops can be adopteddue to the reduction of voltage stresses.

B. Control Strategy

The classical control strategy on TPC in [35] is applied tothe proposed converter. The digital control scheme is plotted inFig. 15. On the primary side, the PV input voltage regulation


Fig. 15. Schematic of the control strategy.

TABLE IICOMPONENT PARAMETERS OF THE PROTOTYPE

(IVR) is used to achieve MPPT. The battery voltage regulation(BVR) and battery current regulation (BCR) are used to preventovervoltage and overcurrent. IVR, BVR, and BCR battery man-agement can be considered as a protection function to preventovercurrent or overvoltage scenarios. Normally, only MPPT andoutput voltage regulation (OVR) are active. To reduce the cur-rent ripple, the driving signals between S1,2 and S3,4 have 180°controlled by OVR to keep the output voltage constant. The dutycycle of S5,6 is ensured to equal 0.5 by the voltage referencevref .

V. EXPERIMENTAL RESULTS

To verify the effectiveness of the proposed converter, a 500 Wconverter prototype is designed. The critical design parametersof the prototype are listed in Table II. The picture of the testbench is given in Fig. 16. Fig. 17 shows the picture of the pro-totype. The PV panel is emulated by a programmable dc powersource. The battery pack is emulated by a programmable dcpower source in parallel with a programmable electric load.This electric load is configured in the constant voltage mode tomimic the behavior of the battery. TMS320F28335 from TexasInstruments is used to implement the digital control algorithm.The experiment waveforms are acquired in daytime mode. Thenight mode is indeed a special case of the daytime mode (power

Fig. 16. Picture of the laboratory setup.

Fig. 17. Picture of the designed TPC prototype.

Fig. 18. Interleaved current waveforms.

only flows from the battery to load). The experimental wave-forms in night mode are similar to the demonstrated waveforms.Thus, the daytime mode is implemented to test the designed con-verter. Fig. 18 shows the experimental steady-state waveformsof the inductor currents on the primary side. As demonstrated,the current ripple on the PV terminal is significantly reduced.Due to the different working ranges of the control variables,the steady-state waveforms in different operational modes are


Fig. 19. Steady-state waveforms of vab , vcd , and iL lk . (a) D < 0.5 and β >0. (b) D < 0.5 and β < 0.

captured in Fig. 19. The experimental results agree with theanalysis.

The critical switching waveforms are captured in Figs. 20and 21. As shown in Fig. 20, there is no overlap between therising edge of vgs and falling edge of vds . This validates ZVS ofthe primary side MOSFETs. Similarly, Fig. 20 proofs that ZVS isrealized on the secondary-side MOSFETs (S5 and S6). The diodecurrent waveforms are captured in Fig. 21. As shown, the diodesare turned off with low di/dt without any reverse recovery. Thesoft-switching results agree with the previous analysis.

An experiment is designed to test the mode transition be-tween daytime mode and night mode. The dynamic responsesof the prototype are captured in Fig. 22. Fig. 22(a) shows thetransitions incurred by the step change of the PV terminal. Asdemonstrated, the PV power steps from 125 W to 0 W at t0 ,which emulates the step change from daytime mode to nightmode. The battery current increases immediately and the bat-tery power compensates the decrease of PV power to keep Po

constant. The PV power is resumed at t1 , which emulates thestep change from night mode to daytime mode. The batterycurrent decreases immediately and the battery power compen-sates the increase of PV power to keep Po constant.

Fig. 22(b) shows the dynamic response of the prototype versusload change. As shown, when the load current steps from 0.24 to0.45 A, the output voltage responses fast with 50 V undershoot.This experiment validates that a robust response is ensured whenthe PV panel power and load power varies.

Fig. 20. Soft-switching waveforms of the primary-side MOSFETs. (a) S1 ,2 .(b) S3 ,4 .

Fig. 21. Soft-switching waveforms of the secondary-side switches. (a) S5 andD1 . (b) S6 and D3 .


Fig. 22. Dynamic responses. (a) Working mode transition. (b) Load powertransition.

Fig. 23. Measured efficiency versus output power in different power flowpaths.

Fig. 24. Measured efficiency versus output power with different battery volt-ages.

The conversion efficiency is evaluated in three different powertransfer paths (PV to battery, battery to load, and PV to load).The results are shown in Fig. 23. The efficiency data is cal-ibrated with a high-precision power analyzer (PPA4530 from

Newtons4th Ltd). As shown, in PV to battery path, the powerflows through the interleaved boost converter. The measuredpeak efficiency is 98.2%. In battery to load path, the powerflows through the transformer and secondary-side rectifier. Themeasured peak efficiency is 96.1%. In PV to load path, thevoltage is first stepped up, and then the power flows through thetransformer and secondary-side rectifier. The measured peak ef-ficiency is 95.9%. Fig. 24 shows the measured efficiency versusoutput power with different battery voltages.

VI. CONCLUSION

This paper proposes a novel integrated three-port dc/dcconverter with high step-up ratio for high-voltage bus-basedmicrogrid systems. The proposed topology is regulated byprimary-side pulsewidth and secondary-side phase-shift. It isfeatured with high degree of integration and high power density.Extended ZVS and ZCS can be achieved in all MOSFETs anddiodes, respectively. This results in low switching losses andhigh efficiency. Due to the voltage sixfolder rectifier structure,the voltage stresses of the secondary-side components are re-markably reduced. In comparison with prior arts, the current rip-ple of the PV panel is reduced due to the interleaving structure.Topology features, operational principles, and circuit character-istics are analyzed in detail in this paper. A 500-W converterprototype is designed and demonstrates good efficiency per-formance. The theoretical analysis results are validated by theexperimental results. Robust dynamic performance validates thecontrol scheme and regulating strategy.

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Junyun Deng (S’18) received the B.S. degree in elec-tric engineering and automation from the HuazhongUniversity of Science and Technology, Wuhan,China, in 2017. He is currently working toward theM.S. degree at the School of Information Scienceand Technology, ShanghaiTech University, Shanghai,China.

His research includes multiport dc/dc converterand bidirectional dc/dc converter.

Haoyu Wang (S’12–M’14–SM’18) received thebachelor’s degree with distinguished honor in elec-trical engineering from Zhejiang University inHangzhou, China, and the master’s and Ph.D. de-grees from the University of Maryland, College Park,MD, USA, both in electrical engineering.

He is currently a Tenure Track Assistant Professorwith the School of Information Science and Technol-ogy, ShanghaiTech University, Shanghai, China. Hisresearch interests include power electronics, plug-inelectric and hybrid electric vehicles, the applications

of wide bandgap semiconductors, renewable energy harvesting, and power man-agement integrated circuits.

Dr. Wang is an Associate Editor for the IEEE TRANSACTIONS ON TRANS-PORTATION ELECTRIFICATION, and an Associate Editor for the CPSS Transac-tions on Power Electronics and Applications.

Ming Shang was born in Jiangsu Province, China.He received the B.S. degree from the College of In-formation and Control Engineering, China Universityof Petroleum, Qingdao, China, in 2015, and the M.S.degree in microelectronics and solid-state electronicsfrom the Chinese Academy of Sciences, Shanghai In-stitute of Microsystem and Information Technology,Shanghai, China, in 2018.

From 2015 to 2018, he was a Graduate ResearchAssistant with the Power Electronics and RenewableEnergies Laboratory, School of Information Science

and Technology, ShanghaiTech University, Shanghai, China. He is currently anEngineer with Inovance Technology Co. Ltd, Suzhou, China.

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