NTUEE IC Design

Tutorial of HW3

Hung-Chi KuoAdvisor: Tzi-Dar Chiueh

2015/11/27

Version 1 : Chun-Hao Liu

Version 2 : Xin-Yu Shih

Version 3 : Yi Chen

Version 4 : Hung-Chi Kuo

2

Outline

• Introduction to Verilog

– Module

– Value & Number

– Data Type

• Simulation : NC-Verilog and nWave

Flow Chart

3

Truth

Table

K-map: Design

each bit of

output

Draw a gate-

level circuit

diagram

Verilog code:

build circuit

lib.v

Test:

testbench

ncverilog

Paper Works

Introduction to Verilog

Module

Value & Number

Data Type

Truth

Table

K-map: Design

each bit of

output

Draw a gate-

level circuit

diagram

Verilog code:

build circuit

lib.v

Test:

testbench

ncverilog

5

Top-Down Design Flow

C/C++/Matlab

NC-Verilog

NC-VerilogDesign Vision

(DV)

HSPICE/Nanosim

Astro/

SECadence

Front-End

Back-End

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What is Verilog ?

• Verilog is a Hardware Description Language

– Describe digital electronic system at multiple

levels of abstraction

– Model the timing

– Express the concurrency of the system operation

– Test the system

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Levels of Abstraction

Transistor Level

Gate Level

Register Transfer Level

Behavior Level

Algorithm

System

concept

Increasing

behavioral

abstraction

Increasing

detailed

realization &

complexity

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Levels of Abstraction in Verilog

• Behavioral

– Structural and procedural like the C programming

language, ex. if…else, case.

• Register Transfer Level (RTL)

– Describe the flow of data between registers and how

a design process these data.

• Structural (Gate Level)

– Describe gate-level and switch-level circuits.

Low

High

• Create an Verilog file “*.v”

• Edit with text editors such as WordPad or Notepad++

• Comments: //(single row) or /* */(multiple row)

• Case sensitive

• ; at the end of each row

Verilog Syntax

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module ADDER (out, in1, in2); //need ;

output [2:0] out;

input [1:0] in1, in2;

wire c;

FA1 fa0 (c, out[0], in1[0], in2[0], 1’b0);

FA1 fa1 (out[2], out[1], in1[1], in2[1], c);

endmodule //doesn’t need ;

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Verilog Module

• Basic building blocks .

• Begin with module, end with endmodule

module <module name> (<port lists>);

//module description

endmodule

module ADDER (out, in1, in2);

endmodule

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Module Ports

• Modules communicate through ports

– Input port

– Output port

module FD2 (Q, D, CLK, RESET);

output Q;

input D, CLK, RESET;

endmodule

4-Value Logic System

• 0 – zero, false, low

• 1 – one, true, high

• Z – high impedance, floating

• X – unknown, occurs at un-initialized storage elements or

un-resolvable logic conflicts

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Value and Number

• <size>’<radix><value>

– Size

• The size in bits

• Default size is 32 bits

– Radix

• b (binary), o (octal), d (decimal), h (hexadecimal)

• Default radix is decimal

– Value

• Any legal number in selected radix

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Value and Number – Examples

underline usage

– 16’b0001_0101_0001_1111

– 32’h12ab_f001

4’b1001 // 4-bit binary

5’D31 // 5-bit decimal

12’h7ff // 12-bit hexadecimal

7 // 32-bit decimal

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Data Type : Wire

• wire

– wire [MSB:LSB] variables;

– Need to be declared before calling

– Input, output are default to be wire

– Default as one bit

output [2:0] out; //3 bits: out[2], out[1], out[0]

input [1:0] in; //2 bits: in[1], in[0]

wire [3:0] c; //4 bits: c[3], c[2], c[1], c[0]

wire d; //1 bit

assign c = 4’d10; //c=4’b1010, c[3]=1, c[2]=0, c[1]=1, c[0]=0

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Wire Assignment

• assign , output portwire a;

wire b;

assign b = 1’b0;

NOT n0(a, b);

• Every wire can be only assigned once!!!wire a;

wire b;

assign b = 1’b0;

NOT n0(a, b);

assign a = 1’b0; //Wrong!!!

Module Instances (1/2)

• Create a higher-level system by connecting

lower-level components

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Module Instances (2/2)

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Net Concatenations

Representation Meaning

{b[3:0],c[2:0]} {b[3] ,b[2] ,b[1] ,b[0], c[2] ,c[1] ,c[0]}

{a,b[3:0],w,3’b101} {a,b[3] ,b[2] ,b[1] ,b[0],w,1’b1,1’b0,1’b1}

{4{w}} {w,w,w,w}

{b,{3{a,b}}} {b,a,b,a,b,a,b}

Ex.

wire [1:0] a;

wire [1:0] b;

wire [5:0] c;

assign c = {2{a[1]}, a, b}; // c = {a[1],a[1],a[1],a[0],b[1],b[0]}

Call by Order vs Call by Name

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module FD2 (Q, D, CLK, RESET);

output Q;

input D, CLK, RESET;

Call by Order

Call by Name

IC

Des

ign

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Example : Adder

module ADDER (out, in1, in2);

output [2:0] out;

input [1:0] in1, in2;

wire c;

FA1 fa0 (c, out[0], in1[0], in2[0], 1’b0);

FA1 fa1 (out[2], out[1], in1[1], in2[1], c);

endmodule

Standard Cell Library (lib.v)

• Choose what you need• Compose your circuit according to I/O

connections

module AN3(Z,A,B,C);

output Z;input A,B,C;

// netlistand g1(Z,A,B,C);

// specify block, declare local // timing constantspecify

// delay parametersspecparam Tp_A_Z = 0.275;specparam Tp_B_Z = 0.275;specparam Tp_C_Z = 0.275;// path delay (full connection)( A *> Z ) = ( Tp_A_Z );( B *> Z ) = ( Tp_B_Z );( C *> Z ) = ( Tp_C_Z );

endspecify

endmodule

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IC

Des

ign

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Standard Cell Library (lib.v)

• IV // not

• AN3 //and

• AN4

• AN2

• EN // xnor

• EN3

• EO // xor

• EO3

• FA1 // full adder

• FD1 // DFF

• FD2

• ND2 // nand

• ND3

• ND4

• NR2 // nor

• NR3

• OR2 // or

• OR3

• OR4

• HA1 // half adder

• MUX21H // 2-to-1 MUX

IC

Des

ign

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• In this HW, all the logic operation MUST consist of standard cell (defined in lib.v). You can NOTuse logic operators(&,|,^,~) or arithmetic operators(+,-,*,/) or behavioral statement(if, else).

Notification of HW3!!

• Do NOT change any module name and port name

in ADC_EADC.v, just modifiy the module

description, otherwise you can’t pass testbench.

Notification of HW3!!

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Don’t Change

NC-Verilog Simulation and nWave

Truth

Table

K-map: Design

each bit of

output

Draw a gate-

level circuit

diagram

Verilog code:

build circuit

lib.v

Test:

testbench

ncverilog

27

Test and Verify Your Circuit

• By applying input patterns and observing

output responses

Test

patterns

Device Under Test (DUT)

Output

response

Testbench: tb_*.v

in.dat *.vcd / out.dat*.v

Testbench

• Put input into circuit you design in ADC_EADC.v

• Check if the output is the same as golden output

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NC-Verilog Simulation

• Put all files in the same directory on Workstation

– ADC_EADC.v, tb_ADC.v, tb_EADC.v, lib.v, in.dat, out.dat

• Source files before simulation:

– source /usr/cadence/cshrc

– source /usr/spring_soft/CIC/verdi.cshrc

• Test ADC

– ncverilog tb_ADC.v ADC_EADC.v lib.v +access+r

• Test EADC

– ncverilog tb_EADC.v ADC_EADC.v lib.v +access+r

run.f

• Pass all test pattern

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NC-Verilog Simulation Results

• Errors

• Source

– source /usr/spring_soft/CIC/verdi.cshrc

• Execute nWave

– nWave &

nWave: Source File and Execute

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*.vcd(2)

(3)

Cancel the filter

(1)

(4)

Select Output File ADC/EADC.vcd

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Select Desired Signal

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• If there’s any workstation account/password

problem, please directly contact workstation

administrator- 邱茂菱，d01943010@ntu.edu.tw

• If you have any questions, please contact TA– 郭泓圻，EE2-232，r04943027@ntu.edu.tw

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Reminder

Thanks for your attention!

Q & A