hardware/software codesign with systemc

15
HM-ES-th1 Les 7 Hardware/Software Codesign with SystemC

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Hardware/Software Codesign with SystemC. HM-ES-th1 Les 7. Van Algoritme naar RTL. Als voorbeeld bekijken we een Single-Purpose Processor die de Greatest Common Divider uitrekent . We beginnen met een functional level SystemC model waarin het algoritme wordt beschreven. gcd. y_i. - PowerPoint PPT Presentation

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Page 1: Hardware/Software Codesign with SystemC

HM-ES-th1 Les 7

Hardware/Software Codesign with SystemC

Page 2: Hardware/Software Codesign with SystemC

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Als voorbeeld bekijken we een Single-Purpose Processor die de Greatest Common Divider uitrekent.

We beginnen met een functional level SystemC model waarin het algoritme wordt beschreven.

Van Algoritme naar RTL

gcdx_i y_i

r_o

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SystemC Untimed Model

Euclid's algorithm300 BC

template <typename T>SC_MODULE(gcd) { sc_in<T> x_i, y_i; sc_out<T> r_o; SC_CTOR(gcd) { SC_METHOD(run); sensitive << x_i << y_i; }private: void run() { T x = x_i.read(); T y = y_i.read(); while (x != y) { if (x > y) { x -= y; } else { y -= x; } } r_o.write(x); }};

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SystemC Test Bench

gcdx_i y_i

r_0

tb_gcd x_o y_o

r_i

template <typename T>SC_MODULE(tb_gcd) { sc_in<T> r_i; sc_out<T> x_o, y_o; SC_CTOR(tb_gcd) { SC_THREAD(run); }private: void check(const T& x, const T& y, const T& r) { wait(10, SC_NS); x_o.write(x); y_o.write(y); wait(10, SC_NS); assert(r_i.read() == r); } void run() { check(0, 0, 0);

check(234, 96, 6); check(12345, 67891, 1); check(12345, 67890, 15); check(12345, 12345, 12345); wait(10, SC_NS); x_o.write(0); y_o.write(0); sc_stop();// ...

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SystemC sc_main

Nu kunnen we timing informatie aan het model toevoegen om te kijken of dit algoritme aan de timing eisen voldoet.

int sc_main(int argc, char *argv[]) { gcd<unsigned int> gcd("gcd"); tb_gcd<unsigned int> tb_gcd("tb_gcd"); sc_buffer<unsigned int> x, y, r; gcd.x_i(x); gcd.y_i(y); gcd.r_o(r);

tb_gcd.x_o(x); tb_gcd.y_o(y); tb_gcd.r_i(r);

sc_start();

return 0;}

Page 6: Hardware/Software Codesign with SystemC

template <typename T>SC_MODULE(gcd) {// idem void run() { while(1) { wait(); T x = x_i.read(); T y = y_i.read(); wait(10, SC_NS); while (x != y) { if (x > y) { x -= y; } else { y -= x; } wait(10, SC_NS); } r_o.write(x); } }};

6

SystemC approximately-timed

Voeg wait(…, SC_NS) statements toe!

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SystemC approximately-timedtemplate <typename T>SC_MODULE(tb_gcd) {// idem void check(const T& x, const T& y, const T& r) { auto start_time_stamp = sc_time_stamp(); x_o.write(x); y_o.write(y); wait(); wait(10, SC_NS); assert(r_i.read() == r); auto end_time_stamp = sc_time_stamp(); cout << "@: " << sc_time_stamp() << ": gcd(" << x << "," << y << ") = " << r << " duration: " << end_time_stamp - start_time_stamp << endl; }

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Stel dat dit voldoet aan de timing specificaties.We maken nu een nauwkeuriger model door het clock

signaal clk toe te voegen.We voegen meteen een go_i en done_o handshake

signaal toe. Waarom?

SystemC cycle accurate

gcdgo_i x_i y_i

done_o r_oclk

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SystemC cycle accurate

done_o

x_i

y_i

go_i

r_o

gcdgo_i x_i y_i

done_o r_oclk

template <typename T>SC_MODULE(gcd) { sc_in_clk clk; sc_in<bool> go_i; sc_in<T> x_i, y_i; sc_out<bool> done_o; sc_out<T> r_o; SC_CTOR(gcd) { SC_THREAD(run); sensitive << clk.pos();

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SystemC cycle accuratevoid run() { wait(); while(1) { do { wait(); } while (!go_i.read()); T x = x_i.read(); T y = y_i.read(); wait(); while (go_i.read() && x != y) { if (x > y) { x -= y; } else { y -= x; } wait(); } if (go_i.read()) { r_o.write(x); done_o.write(true); }

do { wait(); } while (go_i.read()); done_o.write(false); }}

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SystemC cycle accuratetemplate <typename T>SC_MODULE(tb_gcd) { sc_in<bool> done_i; sc_in<T> r_i; sc_out<bool> go_o; sc_out<T> x_o, y_o; SC_CTOR(tb_gcd) { SC_THREAD(run); sensitive << done_i; }private: void check(const T& x, const T& y, const T& r) { auto start_time_stamp = sc_time_stamp(); x_o.write(x); y_o.write(y); go_o.write(true); wait(); assert(r_i.read() == r); auto end_time_stamp = sc_time_stamp(); cout << "@: " << sc_time_stamp() << ": gcd(" << x << "," << y << ") = " << r << " duration: " << end_time_stamp - start_time_stamp << endl; go_o.write(false); wait();

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SystemC RTLGa ervan uit dat de benodigde RTL componenten

beschikbaar zijn (zie hand-outs).Ontwerp en implementeer Datapath en Controller.

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Combinational components

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Sequential components

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single-purpose processor basic model

controller and datapath

controller datapath

externalcontrolinputs

externalcontrol outputs

externaldata

inputs

externaldata

outputs

datapathcontrolinputs

datapathcontroloutputs

… …

a view inside the controller and datapath

controller datapath

… …

stateregister

next-stateand

controllogic

registers

functionalunits