h.-g. moser max-planck-institut für physik, münchen position sensitive detectors in hep silicon...

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H.-G. Moser Max-Planck- Institut für Physik, München Position Sensitive Detectors in HEP Silicon Detectors for Tracking and Vertexing Status: Past and Present Detectors Challenges: Radiation Hardness (LHC) Thin Detectors 3D Detectors Challenges: Precision (e+e-) DEPFETs MAPS SOI Vertical Integration Conclusions and Outlook 1

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Slide 1Position Sensitive Detectors in HEP
Silicon Detectors for Tracking and Vertexing
Status: Past and Present Detectors
Challenges: Radiation Hardness (LHC)
From Wikipedia, the free encyclopedia:
A Position Sensitive Device and/or Position Sensitive Detector (PSD) is an optical position sensor (OPS), that can measure a position of a light spot in one or two-dimensions on a sensor surface.
In particle physics we use this principle to measure
- Impact point of ionizing particles (tracker or vertex detector)
Or, in astronomy and photon science
Conversion point of a x-ray photon
Disclaimer:
Most of the talk will be on tracking detectors, ignoring largely x-ray detectors
Solid state devices other than silicon are ignored as well
Position sensitive detectors
Position Sensing Versus Imaging
Can imagers be used as trackers and vice versa?
e.g. typical imaging sensors like CCDs have been successfully used in trackers (SLD)
Main difference:
Trackers: single particles (MIPS)
Rate < kHz > 10 kHz
Pitch <10µm >10µm
Area small large
(single chip) (tiles, buttable)
However, new applications in x-ray imaging at synchrotrons may ask for very fast sensors
Belle II PXD with 1% occupancy (simulated)
XMM Newton X-xray astronomy
*
Introduction: Diode
Depleted thickness:
Principles of Position Sensitive Detectors
Position Resolution: Segmentation
Silicon Strip Detectors
double sided: 2-dimensional information
Silicon Drift Detectors & CCDs
*
Readout Electronics
Thermal noise input FET: ~ C/t1/2
1/f noise: ~ FET parameters, independent of t
Shot noise: ~( Ileak t)1/2
A real sensor/readout scheme….
Module Layout
*
Layout: Pixel Detectors
Readout ASIC bump bonded (flip chip) on sensor
Rather large material overhead (ASICs, structural material, cooling, services
Flip chip bonding
‘standard’ in industry
Cost driver!
Some History
~1990
~ 100 Si-sensors, <100k channels
LHC detectors
Pixels: 1744 modules, 80 x 106 channels
CMS
200 m² of strip sensors (single sided)
11 x 106 readout channels
~1m² of pixel sensors, 60x106 channels
ALICE
Challenges: Radiation Damage
Shifts threshold voltages of transistors
Creates parasitic channels (‘shorts’) (e.g. in n-in-n and n-in-p sensors)
Not any more a problem in modern DSM CMOS with extremely thin gate oxides
*
+ + + + + + + + + + + + + + + + + + + + + + +
Radiation Damage
Particle knock off lattice atoms
(NIEL, non ionizing energy loss
Mid gap generation levels
increase of leakage current
Shallow traps:
*
Trapping: reduce drift distance
Increased capacitance
*
ILC/CLIC
SuperKEKB
SuperB
-> ultra thin detectors
Radiation damage not as bad as at LHC/sLHC but still an issue
Furthermore: high occupancy due to background
=> Monolithic detectors: DEPFET
*
tight schedule (2015) while ILC is beyond 2020
need to develop a complete detector system
R&D for and experience with B factories will boost sensor technologies for linear colliders
ILC
H.-G. Moser Max-Planck-Institut für Physik, München
Detector Concepts
problems: power and material!
charge generation in small epi-layer
problems: power, speed , small signal
DEPFETs: depleted bulk with integrated amplification
MAPS: Monolithic Active Pixel Sensors:
intergrated CMOS electronics using “standard” CMOS:
problems: speed, small signal (epi, drift)
SOI: use depleted handle wafer as sensor
very non-standard process
Needs advanced technology
DEPFET
µ: mobility (p-channel: holes)
Vg: gate voltage
Vth: threshold voltage
A charge q in the internal gate influences a mirror charge aq in the channel
(a <1, for stray capacitance)
This mirror charge is compensated by a change of the gate voltage:
DV = a q / C = a q / (Cox W L)
*
L
W
d
Belle II PXD
Two layer detector
*
*
Belle II module
diodes and large mechanical samples
Wafer bonding
SOI process
Processing
450mm
50mm
CMOS Sensors
CMOS Sensors are used as optical sensors e.g. in digital cameras replacing CCDs
Advantage:
Cheap (CMOS)
R. Turchetta (2000)
only p-well possible for FET (n-MOS)
no p-MOS transistors (only in periphery)
Charge collection by diffusion in thin epi-layer (slow, small signal)
Successful prototypes
H.-G. Moser Max-Planck-Institut für Physik, München
CMOS Sensors: MAPS
576 x 1152 pixels, 18.4 µm pitch
13.7 x 21.5 mm² (active: 10.6 x 21.2 mm²)
In pixel CDS
Used in the EUDET telescope (thinned, 50µm)
Evolution for the STAR vertex detector:
928 x 1152 pixels, 20.7 µm
(almost twice the size)
Thinned to 50µm
Advanced CMOS Sensors
but still suffers from slow collection of small signal (VIPIX)
INMAPS (RAL): deep p-well shields
PMOS completely
10-20 µm depleted
High resistivity epi (IPHC) from XFAB
1 kWcm -> ~ 14 µm depleted
Charge collection within 5 ns
Remark: with complex electronics power becomes a problem
*
SOI
Handle wafer: Detector grade silicon
Top wafer: CMOS electronics
Project by KEK
deep implants in handle wafer
*
3D Interconnection
Basic Problem:
3D Interconnection:
Two or more layers (=“tiers”) of thinned semiconductor devices interconnected to form a “monolithic” circuit.
Different layers can be made in different technology
(BiCMOS, deep sub-m CMOS, SiGe,…..).
Inherently offering thin chips & high interconnection density (= small pitch)
3D is driven by industry (continue with Moore’s law, increase speed, reduce power)
HEP tracking detectors can profit from this R&D
=> Pioneered at Fermilab (R. Yarema), 3DIC collaboration (Tezzaron)
*
Advantages even for single layer
Make use of smaller feature size (gain space)
-> move periphery in between pixels (can keep double column logic)
-> backside contacts with vias possible
-> no cantilever needed, 4-side abuttable
Periphery, column logic, services
Conventional Layout 3D Layout
Ongoing R&D (examples)
tapered vias by IZM
Essential: FEI3 available on wafers!
MPI Munich: innterconnection of ATLAS FEI3 with EMFT SLID technology (eutectic bonding) and tungsten vias (3 x 10 µm)
Interconnection with 100% yield has been achieved.
TSV to follow
*
Support & Cooling
Both concepts rely on air cooling, excluding high density sensors with fast readout
Need for active cooling adds material!
Develop low mass support & cooling:
INFN for superB
0.15 % X0 + sensor & flex
Aim for 0.3% X0
Monolithic device
< 0.2% X0
X-ray Detectors
High intensity SASE light sources are challenging for detectors
High dynamic range
Short exposure time (XFEL: 200ns spacing)
Many techniques and ideas used in HEP trackers can be used for x-ray sensors
(hybrid pixel detectors)
Pilatus 6M, 12.5 Hz frame rate
DEPFET based DSSC: 5 MHz frame rate
*
Summary
Position sensitive silicon detectors have reached maturity and are an integral part of modern particle physics detectors
LHC: large areas of silicon (up to 200 m2)
radiation hard up to 1014 n/cm2 (strips)
1015 n/cm2 (pixel)
Performance limited by trapping
B-factories, linear collider: low mass, high resolution, high rate
Integration of electronics and sensors
a) Monolithic detectors
b) 3D integration
*
Pixel Detectors in HEP
Complex electronics
Monolithic sensors
Presently the complexity of the in pixel electronics is limited
CMOS sensors (MAPS)
‘standard CMOS’ process
small signal, slow charge collection
DEPFET
sensorwafer