andrei nomerotski 1 andrei nomerotski, university of oxford instr08, novosibirsk 29 february 2008...
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Andrei Nomerotski
1
Andrei Nomerotski, University of Oxford
INSTR08, Novosibirsk 29 February 2008
Silicon Detectors
for Tracking and Vertexing
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Silicon Detectors
Using silicon diode as s detector 1951: first observation of signals in reversely biased p-n
junction from ’s
Development for tracking stimulated by need to measure short-lived charm/beauty quarks and tau lepton in ’70
1980, J.Kemmer: first proposed to use planar process developed in industry to produce strip silicon detectors Fast, localized charge deposition 3 micron intrinsic
resolution Planar process dimensions precise to 1 micron, low cost
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Vertex Detectors SLD data events with clear primary (left) and secondary
(right) vertices
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Trackers
200 MeV protons hitting CMS pixel module at shallow angle(Roland Horisberger, PSI)
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Silicon for Vertex Detectors Resolution at IP for two layers with resolution
r1/r2 should be as small as possible
for =10 m, r1/r2=0.5, b = 20 m
multiple scattering r2 can’t be large Beampipe 5 cm, thickness 1 mm Be = 0.3% X0
28 m at IP for P = 1 GeV
Two conclusionsFirst layer as close as possible to Interaction Point
As thin as possible
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Silicon for Tracking
Precise measurement of curvature excellent momentum resolution
Low occupancy per strip excellent pattern recognition
2D 3D information Strip detectors: ghosts
complicate pattern recognition
Pixel detectors – best possible pattern recognition
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Strip Detectors Depleted p-n diodes Fast and efficient charge
collection by drift in electric field
4 fC in 300 micron of Si
Each strip has capacitance to backplane and neighbours
Noise is typically dominated by serial contributions scales with detector capacitance
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Strips vs Pixels Strip detectors
Large capacitance, 10 pF Large signal, 24000 e Large noise, 2000 e
Well established area – dozens of small, large and huge trackers and vertex detectors in operation since ’90
New development: strips in depth of sensor – 3D silicon strips
Pixel detectors Small capacitance Extra low noise, 10-100 e Could do with small signal
Opens variety of interesting options
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Pixel Detectors Hybrid pixels – well established for LHC
Bump bonding Sophisticated electronics
Collect charge from thinner sensors use wafers with 5-25 micron epi-layer, closer to industry mainstream
CMOS and CCD based detectors Collect by diffusion in reasonable time, 100 ns
Readout First move charge to the side
CCD Silicon Drift detectors
Integrate electronics and detector – a lot of interesting recent developments
Solder bump
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OutlineNew requirements for next generation machine for Particle Physics (LC
and SLHC) New technologies available in industry
Column Parallel CCDsStorage Pixel Detectors, ISISFine Pixel CCDs
Chronopixels Vertical integration of sensors and electronicsSilicon On Insulator
DEPFETSilicon Drift Detectors
System issuesSilicon Tracker for ILCMaterialSerial Powering
Applications
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I will not discuss in this talk :
Active Pixel Sensors (APS) Talk by Lars Eklund
3D and active edge silicon Talk by Daniel Pennicard
LHC and other existing trackers / vertex detectors Multiple talks in this session
Radiation hardness issues Review by Gianluigi Casse
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Linear Collider : Precise Thin Detectors
E%30
t t event at 350 GeV
ILC physics demands excellent Vertexing (b,c,t) and Tracking
Vertex detector characteristics
point resolution 3 m
Thickness ~ 0.1 % X0
5-6 layers
Inner radius ~ 1.5 cm
(IP) < 5 m 10 m/(p sin3/2 )
best SLD 8 m 33 m/(p sin3/2 ))
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Linear Collider Physics Case Higgs:
Model independent observation Establish mass generation
mechanism SUSY
Symmetry breaking mechanism Measure properties of
supersymmetrical particles
Precision Access to higher energy scale
Higgs can be reconstructed through recoil mass independently of its decay channel
Will require excellent flavour ID
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Flavour Identification Main motivation for vertex detector
for LC Combine several variables into
Neural Net Vertex mass – main contributor Vertex momentum Decay length Decay length significance Jet Probability
Vertex charge Charge of tracks associated to vertex Allows to distinguish between b and
anti-b quarks
b c light
LCFI collaboration
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The Readout Challenge
What readout speed is needed? Massive e+e- background from beamstrahlung : pairs
radiated in intense EM fields of bunches Need to read out once occupancy = 1%
20 times per train = 20 kHz per 1 Mpixel frame Different approaches
Time stamping In situ storage Rolling shatter Super-fine segmentation
337 ns
2820x
0.2 s
0.95 ms
LC Beam Time Structure:
= one train
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“Classic CCD”Readout time
NM/fout
N
M
N
Column Parallel CCD
Readout time = N/fout
M
LCFI develops CCD (Charged Coupled Device) based sensors
Column Parallel CCD
Readout time shorten by orders of magnitide
Need 50 MHz clock to achieve 20 kHz / frame
Main difficulty: distribution of 20 A clocks at 50 MHz
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● CPC2 wafer (100 .cm/25 μm epi and 1.5k.cm/50 μm epi)
ISIS1
Second generation CPCCD sensor: CPC2
The whole image area serves as a distributed busline
Designed to reach 50 MHz operation
Busline-free CPC2
104 mm
CPC2-10
CPC2-40
CPC2-70
CPC2
LCFI
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CPCCD Testing Achieved low-noise operation
at 20 MHz Used CPR2 to read out and
CPD1 to drive large devices CPD1 provides 20 A clock at
50 MHz CPR2 : 128 ADC, cluster
finding and sparse readout, works at 9 MHz
Amplitude spectrum of 5.9 keV 55Fe X-rays at 20 MHz
CPC2-40CPR2
CPD1
Pedestalpeak Photo-
peak
LCFI
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● New ideas to reduce high CCD capacitance
● Open phase CCD, “Pedestal Gate CCD”, “Shaped Channel CCD”
● Could reduce Cig by ~4
● e2V Technologies produced 27 types of small CCDs to check these
ideas
CPCCD with Low Capacitance
LCFI
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ISIS – In-Situ Storage Image Sensor
Each pixel has internal memory implemented as CCD register Charge collected under a photogate Charge is transferred to 20-pixel storage CCD in situ Conversion to voltage and readout in the 200 ms-long
quiet period after collision
ISIS1 “proof of principle” constructed at e2V
LCFI
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Tests with 55Fe X-ray source:
ISIS1 with and without p-well tested
Correct charge storage in 5 time slices and consequent readout
Charge collection through photogate demonstrated
Tested in testbeam in 2007
ISIS2 design in preparation, submission in April 2008
ISIS Proof of Principle
LCFI
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Fine Pixel CCD Idea: use pixel of ~5m to keep occupancy low
Fully depleted epitaxial layer to minimize the number of hit pixels due to charge spread by diffusion
Accumulate hit signals for one train (1 ms) and read out between trains (200 ms) should be very robust
Results for test structures: possible to deplete fully S7170 SPL24mm, highest resistivity 24m thick epi-layer, Hamamatsu Used laser to induce signal
Projection
Y. Sugimoto, KEK
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Next generation FPCCD
12m pixel size 24m epitaxial layer 512x512 pixels 6.1mm2 image area 4 different design of output
amp To be delivered at the end of
2007
8.2 mm
7.5 mm
Y. Sugimoto, KEK
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What is 3D Circuit Integration?
A 3D chip is comprised of several layers of semiconductor devices which have been thinned, bonded together, and interconnected to form a “monolithic” circuit.
Opto Electronics
Digital layer
Analog Layer
Sensor Layer
Optical Fiber I n Optical Fiber Out
Designer’s Dream
50 um
Four Key Enabling Technologies Wafer thinning (to <25m) Precision alignment
Better than 1 micron Bonding of thinned wafers Interconnection of wafers by
metal vias
All possible now
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3D Integration is Future Mainstream in Industry
Industry is moving toward 3D to improve circuit performance. Reduce R, L, C for higher speed Reduce chip I/O pads Provide increased functionality Reduce interconnect power and crosstalk
Utilizes technology developed for Silicon-on-Insulator devices
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Examples of 3D Sensor Integration
Epoxy bonded 3D connected imager (RTI/DRS)
8 micron pitch, 50 micron thick oxide bonded imager (Lincoln Labs)
8 micron pitch DBI (oxide-metal) bonded PIN imager (Ziptronix)
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Silicon on Insulator Thin active circuit layer on an
insulating substrate ~200 nm of silicon on a “buried”
oxide (BOX) on a “handle” wafer.
The handle wafer can be high quality, detector grade silicon
Opens the possibility of integration of electronics and fully depleted detectors
in a single wafer with very fine pitch little additional processing.
Important for 3D integration
(Soitech illustration)
Steps for SOI wafer formation
Active
BOX
Substrate(detector material)
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Key Technologies for SOI/3D1) Bonding between layers
Oxide to oxide fusion Copper/tin bonding Polymer/adhesive bonding
2) Wafer thinning Grinding, lapping, etching
3) Through wafer via formation and metallization
With isolation Without isolation
4) High precision alignment
Polymer
(BCB)
SiO2bond
Cu SnCu3Sn
(eutectic bond)
Direct bond interconnect
SEM of 3 vias using Bosch process
Via usingoxide etchprocess(LincolnLabs)
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Thin Silicon After silicon is thinned to 50 micron or less it
becomes flexible and eventually transparent
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SOI Concept for HEP
Backside implanted after thinningBefore frontside wafer processingOr laser annealed after processing
High resistivitySilicon wafer,Thinned to 50-100 microns
Active edge processing
Minimal interconnects, low node capacitance
not to scale
R.Lipton, R.Yarema (Fermilab)
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3D Pixel Design for ILC Vertex Detector R&D program at Fermilab
Goal - demonstrate ability to implement a complex pixel design with all required ILC properties in a 20 micron square pixel
Previous technologies limited to very simple circuitry or large pixels
3D chip design using MIT Lincoln Labs 0.18 um SOI process. 3D density allows analog pulse height digitization, sparse
readout, high resolution time stamp, all in a 20 micron pitch pixel.
Time stamping and sparse readout occur in the pixel, Hit address found on array perimeter
64 x 64 pixel demonstrator version of 1k x 1K array Submitted to 3 tier DARPA multi project run at LL
Sensor to be added later
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3D Geometry
Sample1
Sample2 Vth
Sample 1
To analog output buses
S. TrigDelay
Digital time stamp bus5
Pad to sensor
Analog T.S.b0 b1 b2 b3 b4
Analog time output bus
Analog ramp bus
Write data
Read data
Test input S.R.I njectpulse
I n
OutS
RQ
Y address
X address
D FF
Pixelskiplogic
Token I n
Token out
Readall
Read dataData clk
Tier 1
Tier 2
Tier 3
Chip designers:Tom ZimmermanGregory Deptuch Jim Hoff
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Full 3D Pixel Circuit Pixel cell Tot 175 transistors in 20x20
µm pixel 3 Tiers with tot 22 µm height Unlimited use of PMOS and
NMOS Allows 100 % diode fill
factor
Received back in Nov 2007, testing underway
High resistivity substrateBOX
Tier 1
Tier 2
Tier 3
20 um
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Depleted FET
fully depleted sensitive volume, charge collection by drift
internal amplification q-I conversion: 0.4 nA/e, scales with gate length and
bias current
Charge collection in "off" state, read out on demand
J. Kemmer & G. Lutz, 1987
DEpleted P-channel FET
n x mpixel
IDRAIN
DEPFET- matrix
VGATE, OFF
off
off
on
off
VGATE, ON
gate
drain VCLEAR, OFF
off
off
reset
off
VCLEAR, ON
reset
output
0 suppression
VCLEAR-Control
Row wise read-out ("rolling shutter")
select row with external gate, read current,
clear DEPFET, read current again the
difference is the signal
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DEPFET: Noise versus bandwidth
1.6 e ENC at =10 s 25 e ENC at =33ns (30MHz)
Measurements of a single pixel with an external high bandwidth amplifier.
High speed readout => high bandwidth => short shaping timesThermal noise of the DEPFET transistor ~ 1/SQRT()
MPI, Germany
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DEPFET Testbeam
Pixel size 36 x 28.5 m2
Timing 320 nsec S/N = 110 Resolution 2 m
MPI, Germany
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Silicon Drift Detectors p+ segmentation on both sides
of silicon Complete depletion of wafer
from segmented n+ anodes on one side
Distance measured by drift time
Small load capacitance – excellent noise performance
Position resolution 2 m in lab, 10 m in
testbeam, 30 m in experiments
Applications SDD fully functioning in
STAR SVT since 2001, will be used by ALICE (1.3 m2)
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Controlled Drift Detector Channel stops confine
charge to parallel drifting channels
Potential minimum near top surface
Control of drift field: “integrate-readout” modes
Similar to CCD but charge moved by constant field
Drift time 1-2 s/cm 20 m in 2-4 ns CPCCD 20 m in 20 ns
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CDD Results
Produced prototypes with 6.1 mm drift length
Compton electron and other types of imaging with excellent position and timing resolution
Design of 10.2 mm long drift detector (1x3 cm2 total area) in progress (COMPTON, INFN Milano)
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Silicon Tracker for ILC Modules overlap to eliminate
projective cracks
Sensors are ~92mm on a side Each sensor has is readout
independently by KPIX chip Bump bonded directly to sensor 0.2 x 0.5 mm2 readout cells
4 layer Cu / kapton cable that carries power, signals, and bias
T.Nelson, SLAC
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Thinning Technology at MPI Semiconductor Laboratory
sensor wafer
handle wafer
1. implant backsideon sensor wafer
2. bond sensor waferto handle wafer
3. thin sensor sideto desired thickness
4. process DEPFETson top side
5. structure resist,etch backside upto oxide/implant
Industry: TraciT, GrenobleHLL HLL main lab HLL special lab
sensor wafer
handle wafer
1. implant backsideon sensor wafer
2. bond sensor waferto handle wafer
3. thin sensor sideto desired thickness
4. process DEPFETson top side
5. structure resist,etch backside upto oxide/implant
Industry: TraciT, GrenobleHLL HLL main lab HLL special lab
sensor wafer
handle wafer
1. implant backsideon sensor wafer
2. bond sensor waferto handle wafer
3. thin sensor sideto desired thickness
4. process DEPFETson top side
5. structure resist,etch backside upto oxide/implant
Industry: TraciT, GrenobleHLL HLL main lab HLL special lab
sensor wafer
handle wafer
1. implant backsideon sensor wafer
2. bond sensor waferto handle wafer
3. thin sensor sideto desired thickness
4. process DEPFETson top side
5. structure resist,etch backside upto oxide/implant
Industry: TraciT, GrenobleHLL HLL main lab HLL special lab
sensor wafer
handle wafer
1. implant backsideon sensor wafer
2. bond sensor waferto handle wafer
3. thin sensor sideto desired thickness
4. process DEPFETson top side
5. structure resist,etch backside upto oxide/implant
Industry: TraciT, GrenobleHLL HLL main lab HLL special lab
sensor wafer
handle wafer
1. implant backsideon sensor wafer
2. bond sensor waferto handle wafer
3. thin sensor sideto desired thickness
4. process DEPFETson top side
5. structure resist,etch backside upto oxide/implant
Industry: TraciT, GrenobleHLL HLL main lab HLL special lab
sensor wafer
handle wafer
1. implant backsideon sensor wafer
2. bond sensor waferto handle wafer
3. thin sensor sideto desired thickness
4. process DEPFETson top side
5. structure resist,etch backside upto oxide/implant
Industry: TraciT, GrenobleHLL HLL main lab HLL special lab
sensor wafer
handle wafer
1. implant backsideon sensor wafer
2. bond sensor waferto handle wafer
3. thin sensor sideto desired thickness
4. process DEPFETson top side
5. structure resist,etch backside upto oxide/implant
Industry: TraciT, GrenobleHLL HLL main lab HLL special lab
sensor wafer
handle wafer
1. implant backsideon sensor wafer
2. bond sensor waferto handle wafer
3. thin sensor sideto desired thickness
4. process DEPFETson top side
5. structure resist,etch backside upto oxide/implant
Industry: TraciT, GrenobleHLL HLL main lab HLL special lab
sensor wafer
handle wafer
1. implant backsideon sensor wafer
2. bond sensor waferto handle wafer
3. thin sensor sideto desired thickness
4. process DEPFETson top side
5. structure resist,etch backside upto oxide/implant
Industry: TraciT, GrenobleHLL HLL main lab HLL special lab
1) Process backside of thick detector wafer (structured) implant.
2) Bond detector wafer on handle wafer (SOI).
3) Thin detector wafer to desired thickness (grinding & etching).
4) Process front side of the detector wafer in a standard (single sided) process line.
5) Etch handle wafer.If necessary: add Al-contactsLeave frame for stiffening and handling, if wanted
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Thinning : mechanical samples6” wafer with diodes and large mechanical samples
Thinned area: 10cm x 1.2 cm (ILC vertex detector dummy)
Possibility to structure handling frame(reduce material, keep stiffness)
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Mechanics: Foams
Goal : 0.1% X0
Properties: Open-cell foam Macroscopically uniform No tensioning needed
Good results with 3% RVC (Reticulated Vitreous Carbon) prototype
Also: Silicon Carbide foam LCFI
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Power Distribution
Power is a crucial issue for the vertex detector CP CCD 20 amps x 200 modules = 4000 amps of clock MAPS or SOI 20-100W x 100(DF)@1V = 2000 - 10,000 amps
Vertex detector technology is sexy - but power engineering is just as important Serial powering (think Xmas lights) can lower instantaneous
current Understand noise, engineer regulators, understand interconnects
Or/and DC-DC converters
Lower CCD capacitance Routing in and out
Include something capable of providing 2-10kW in simulation
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Atlas SLHC design but applicable elsewhere
Initial tests indicate good noise performance
• Instantaneous power = average power x (50-100) 20W ave.=>2kW
• At 1.5 V peak current ~666 A, 3 cm diam. of copper/side needed for 50mV drop
• Serial powering can reduce peak currents
– Requires individual ladder regulators (3D integrated?)
– V*n, I/n, V tolerances relaxed with local regulation
Serial Power
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X-Rays in Silicon Visible photon range few m 20keV X-ray range 5 m 100 keV X-ray range 80 m For larger energies need different
materials (higher Z)
6 keV X-rays, 1 ms exposure time(Cornell) Appl. Phys. Lett. 83 (2003) 1671
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MAMBO - Monolithic Active pixel Matrix with Binary cOunters in SOI Technology OKI 0.15µm
Counting pixel detector with integrated readout for X-ray or electron microscope imaging
Similar to Medipix but monolithic
64x64 26x26 m pixels 12-bit counter, 1 MHz 350 m thick sensor
First version produced and tested in 2007
good separate performance of analogue and digital parts
Second version submitted to OKI
26 x 26 m2
total: 280 transistors
G.Deptuch, Fermilab
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Preservation of Mechanical Recording
Disc: groove moves from side to side
Audio is encoded in micron scale features which are >100 meters long
• Used ATLAS silicon module survey camera for scanning• Software filters out noise