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Confidential and Proprietary

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Augusto Panecatl Technical Information and Customer Support

ARM Cortex M0+®

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Cortex-M0 processors

Cortex-M series processors have been specifically developed for the microcontroller industry where the need for fast, highly deterministic, interrupt management is coupled with the desire for extremely low gate count and lowest possible power consumption.

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Energy efficiency• Run at lower MHz or during shorter activity periods• Architected support for sleep modes

Smaller code• High density instruction set• Achieve more per byte than 8/16-bit devices

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Ease of use• Global standard across multiple vendors• Code compatibility

High Performance

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Cortex-M0 Processors

Cortex-M family processors are all binary upwards compatible, enabling software reuse and a seamless progression from one Cortex-M processor to another.

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Cortex M Scalability

Code fully upward compatible with Kinetis K Cortex-M4

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ARM Cortex-M0+ : The True 8-bit Replacement

• The smallest, lowest-power ARM processor on the market

• Processor consumption as low as 9μA/MHz*

• Outstanding results of 1.77 CoreMark/MHz

• I/O low-power improvements with single cycle access to critical peripherals (GPIO …)

• Relocatable vector table allows for dynamic exception handlers by moving the vector table into RAM

• Micro trace buffer brings fast debug advantages of trace to low-end MCUs

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Cortex-M0+

• 32-bit RISC processor

• 2-stage pipeline von Neumann architecture

• ARMv6-M architecture

• 16-bit Thumb instruction set with Thumb-2 technology.

• Load-Store Architecture

• 56 Instructions

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Simplified Block Diagram

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Nested Vectored Interrupt Controller (NVIC)

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Programmers model

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Memory model

• 4GB of memory address space• Code Region • SRAM Region• Peripheral Region• RAM Region• Device Region• Internal Private Peripheral Bus

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Sleep Mode

SLEEPONEXIT bit set

ISRActive

Mode Sleep Mode

WFI or WFE

ISR exit

ARM Cortex-M0+ Processor: Low Power by Design

Dedicated features built-in the processor: • WFI & WFE instructions: set core into SLEEP

and Wait-For-Event/Interrupt• Sleep-on-Exit: automatic SLEEP after interrupt

execution• Few cycles to switch between run and sleep

DEEP SLEEP for longer sleep period:• CPU and NVIC unpowered • WIC monitors wake-up sources• Static processor leakage in nW

KINETIS L implementation:• Asynchronous WIC (AWIC)• Multiple WU sources: periph/LV/NMI• Additionnal LLWU for low leakage wake up

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Ultra-low Power Modes

Mode Definition

Run MCU can be run at full speed. Supports Compute Operation clocking option where bus and system clock are disabled for lowest power core processing and energy-saving peripherals with an alternate asynchronous clock source are operational.

VLP Run(VLPR)

MCU maximum frequency is restricted to 4MHz core/platform and 1 MHz bus/flash clock. Supports Compute Operation clocking option. LVD protection is off and flash programming is disallowed.

Wait Allows all peripherals to function, while CPU goes to sleep reducing power consumption. No Compute Operation clocking option.

VLP Wait(VLPW)

Similar to VLP Run, with CPU in sleep to further reduce power. No Compute Operation clocking option.

StopMCU is in static state with LVD protection on. Energy-saving peripherals are operational with Asynchronous DMA (ADMA) feature that can wake-up DMA to perform transfer and return to current mode when complete. AWIC detects wake-up source for CPU. Lowest power mode with option to keep PLL active.

VLP Stop(VLPS)

MCU is in static state with LVD protection off. Energy-saving peripherals are operational with ADMA feature. AWIC detects wake-up source for CPU.

LL Stop(LLS)

MCU is in low leakage state retention power mode. LLWU detects wake-up source for CPU including LPTMR, RTC, TSI, CMP, and select pin interrupts. Fast <4.3us wake-up.

VLL Stop 3 (VLLS3)

MCU is placed in a low leakage mode powering down most internal logic. All system RAM contents are retained and I/O states held. LLWU controls wake-up source for CPU similar to LLS mode.

VLL Stop 1(VLLS1)

Similar to VLLS3 with no RAM or register file retention.

VLL Stop 0(VLLS0)

Pin wakeup supported. LPTMR, RTC, TSI and CMP wake-up supported with external clock. No RAM or register file retention. Optional POR brown-out detection circuitry.

Expands beyond typical run, sleep and deep sleep modes with power options designed to maximize battery life in varying applications

RU

NS

LE

EP

DE

EP

SL

EE

P

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Analog Interfaces

System

Peripheral Bus

Energy Management

Power On Reset

Low Voltage Detector

Voltage Regulator

Clock Management

FLL

Timers

SRTC Temp. Compensated

I/O PortsCommunication

I2C x 212-bit DAC

HSCMP

Flash8-256K

RAM1-32K

Debug(SWD)

COP

RST

Unique ID

DMA 4-ch

TSI x 16ch

Up to 80 GPIO(4 High Dive)

w/ 25 interrupt

LPO(1KHz

)

RST/Input

LPTMR

Crystal Oscillator (low & high

range)

16b LPTPM 6ch x1, 2ch x 2

SPI x 2

ADC (SAR w/ DMA)12/16-bit, up to 16ch

Kinetis L Series: Master Block Diagram

RunOperation in: Wait VLLS

1 VLLS

0Stop/VLPS

VLLS3

UART x2

Connectivity

USB FS/LS Transceiver

V Regulator

HMI

Segment LCD51x8/55x4

PLL

ARM Cortex-M0+ Core Ultra-low power48MHz bus freq.

Packages: 16QFN, 20WLCSP, 24QFN, 32LQFP, 32QFN, 35WLCSP, 48LQFP, 48QFN, 64LQFP, 80LQFP, 100LQFP, 121MBGA

LPUARTx1

IISx1

USB Controller

PIT2ch, 32bit

LS Osc(32KHz)

ULP Osc(4MHz)

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